2 * linux/arch/arm/mach-ebsa110/isamem.c
4 * Copyright (C) 2001 Russell King
6 * Perform "ISA" memory and IO accesses. The EBSA110 has some "peculiarities"
7 * in the way it handles accesses to odd IO ports on 16-bit devices. These
8 * devices have their D0-D15 lines connected to the processors D0-D15 lines.
9 * Since they expect all byte IO operations to be performed on D0-D7, and the
10 * StrongARM expects to transfer the byte to these odd addresses on D8-D15,
11 * we must use a trick to get the required behaviour.
13 * The trick employed here is to use long word stores to odd address -1. The
14 * glue logic picks this up as a "trick" access, and asserts the LSB of the
15 * peripherals address bus, thereby accessing the odd IO port. Meanwhile, the
16 * StrongARM transfers its data on D0-D7 as expected.
18 * Things get more interesting on the pass-1 EBSA110 - the PCMCIA controller
19 * wiring was screwed in such a way that it had limited memory space access.
20 * Luckily, the work-around for this is not too horrible. See
21 * __isamem_convert_addr for the details.
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/types.h>
30 static u32 __isamem_convert_addr(void *addr)
32 u32 ret, a = (u32) addr;
35 * The PCMCIA controller is wired up as follows:
36 * +---------+---------+---------+---------+---------+---------+
37 * PCMCIA | 2 2 2 2 | 1 1 1 1 | 1 1 1 1 | 1 1 | | |
38 * | 3 2 1 0 | 9 8 7 6 | 5 4 3 2 | 1 0 9 8 | 7 6 5 4 | 3 2 1 0 |
39 * +---------+---------+---------+---------+---------+---------+
40 * CPU | 2 2 2 2 | 2 1 1 1 | 1 1 1 1 | 1 1 1 | | |
41 * | 4 3 2 1 | 0 9 9 8 | 7 6 5 4 | 3 2 0 9 | 8 7 6 5 | 4 3 2 x |
42 * +---------+---------+---------+---------+---------+---------+
44 * This means that we can access PCMCIA regions as follows:
45 * 0x*10000 -> 0x*1ffff
46 * 0x*70000 -> 0x*7ffff
47 * 0x*90000 -> 0x*9ffff
48 * 0x*f0000 -> 0x*fffff
50 ret = (a & 0xf803fe) << 1;
51 ret |= (a & 0x03fc00) << 2;
55 if ((a & 0x20000) == (a & 0x40000) >> 1)
63 * read[bwl] and write[bwl]
65 u8 __readb(void *addr)
67 u32 ret, a = __isamem_convert_addr(addr);
76 u16 __readw(void *addr)
78 u32 a = __isamem_convert_addr(addr);
86 u32 __readl(void *addr)
88 u32 ret, a = __isamem_convert_addr(addr);
94 ret |= __raw_getw(a + 4) << 16;
98 EXPORT_SYMBOL(__readb);
99 EXPORT_SYMBOL(__readw);
100 EXPORT_SYMBOL(__readl);
102 void __writeb(u8 val, void *addr)
104 u32 a = __isamem_convert_addr(addr);
112 void __writew(u16 val, void *addr)
114 u32 a = __isamem_convert_addr(addr);
122 void __writel(u32 val, void *addr)
124 u32 a = __isamem_convert_addr(addr);
130 __raw_putw(val >> 16, a + 4);
133 EXPORT_SYMBOL(__writeb);
134 EXPORT_SYMBOL(__writew);
135 EXPORT_SYMBOL(__writel);
137 #define SUPERIO_PORT(p) \
138 (((p) >> 3) == (0x3f8 >> 3) || \
139 ((p) >> 3) == (0x2f8 >> 3) || \
140 ((p) >> 3) == (0x378 >> 3))
147 * The SuperIO registers use sane addressing techniques...
149 if (SUPERIO_PORT(port))
150 ret = __raw_getb(ISAIO_BASE + (port << 2));
152 u32 a = ISAIO_BASE + ((port & ~1) << 1);
155 * Shame nothing else does
170 * The SuperIO registers use sane addressing techniques...
172 if (SUPERIO_PORT(port))
173 ret = __raw_getw(ISAIO_BASE + (port << 2));
175 u32 a = ISAIO_BASE + ((port & ~1) << 1);
178 * Shame nothing else does
194 EXPORT_SYMBOL(__inb);
195 EXPORT_SYMBOL(__inw);
196 EXPORT_SYMBOL(__inl);
198 void __outb(u8 val, int port)
201 * The SuperIO registers use sane addressing techniques...
203 if (SUPERIO_PORT(port))
204 __raw_putb(val, ISAIO_BASE + (port << 2));
206 u32 a = ISAIO_BASE + ((port & ~1) << 1);
209 * Shame nothing else does
218 void __outw(u16 val, int port)
223 * The SuperIO registers use sane addressing techniques...
225 if (SUPERIO_PORT(port))
228 off = (port & ~1) << 1;
233 __raw_putw(val, ISAIO_BASE + off);
236 void __outl(u32 val, int port)
241 EXPORT_SYMBOL(__outb);
242 EXPORT_SYMBOL(__outw);
243 EXPORT_SYMBOL(__outl);
245 extern void __arch_writesb(unsigned long virt, const void *from, int len);
246 extern void __arch_writesw(unsigned long virt, const void *from, int len);
247 extern void __arch_writesl(unsigned long virt, const void *from, int len);
248 extern void __arch_readsb(unsigned long virt, void *from, int len);
249 extern void __arch_readsw(unsigned long virt, void *from, int len);
250 extern void __arch_readsl(unsigned long virt, void *from, int len);
252 void outsb(unsigned int port, const void *from, int len)
256 if (SUPERIO_PORT(port))
259 off = (port & ~1) << 1;
264 __raw_writesb(ISAIO_BASE + off, from, len);
267 void insb(unsigned int port, void *from, int len)
271 if (SUPERIO_PORT(port))
274 off = (port & ~1) << 1;
279 __raw_readsb(ISAIO_BASE + off, from, len);
282 EXPORT_SYMBOL(outsb);
285 void outsw(unsigned int port, const void *from, int len)
289 if (SUPERIO_PORT(port))
292 off = (port & ~1) << 1;
297 __raw_writesw(ISAIO_BASE + off, from, len);
300 void insw(unsigned int port, void *from, int len)
304 if (SUPERIO_PORT(port))
307 off = (port & ~1) << 1;
312 __raw_readsw(ISAIO_BASE + off, from, len);
315 EXPORT_SYMBOL(outsw);
318 void outsl(unsigned int port, const void *from, int len)
320 panic("outsl not supported on this architecture");
323 void insl(unsigned int port, void *from, int len)
325 panic("insl not supported on this architecture");