2 * linux/arch/arm/mach-h720x/cpu-h7202.c
4 * Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de>
5 * 2003 Robert Schwebel <r.schwebel@pengutronix.de>
6 * 2004 Sascha Hauer <s.hauer@pengutronix.de>
8 * processor specific stuff for the Hynix h7201
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
16 #include <linux/init.h>
17 #include <linux/interrupt.h>
18 #include <linux/module.h>
19 #include <asm/types.h>
20 #include <asm/hardware.h>
22 #include <asm/arch/irqs.h>
23 #include <asm/mach/irq.h>
24 #include <asm/mach/time.h>
25 #include <linux/device.h>
26 #include <linux/serial_8250.h>
29 static struct resource h7202ps2_resources[] = {
33 .flags = IORESOURCE_MEM,
38 .flags = IORESOURCE_IRQ,
42 static struct platform_device h7202ps2_device = {
45 .num_resources = ARRAY_SIZE(h7202ps2_resources),
46 .resource = h7202ps2_resources,
49 static struct plat_serial8250_port serial_platform_data[] = {
51 .membase = SERIAL0_BASE,
56 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
59 .membase = SERIAL1_BASE,
64 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
67 .membase = SERIAL2_BASE,
72 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
75 .membase = SERIAL3_BASE,
80 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
85 static struct platform_device serial_device = {
89 .platform_data = serial_platform_data,
93 static struct platform_device *devices[] __initdata = {
98 /* Although we have two interrupt lines for the timers, we only have one
99 * status register which clears all pending timer interrupts on reading. So
100 * we have to handle all timer interrupts in one place.
103 h7202_timerx_demux_handler(unsigned int irq_unused, struct irqdesc *desc,
104 struct pt_regs *regs)
106 unsigned int mask, irq;
108 mask = CPU_REG (TIMER_VIRT, TIMER_TOPSTAT);
110 if ( mask & TSTAT_T0INT ) {
111 write_seqlock(&xtime_lock);
113 write_sequnlock(&xtime_lock);
114 if( mask == TSTAT_T0INT )
120 desc = irq_desc + irq;
123 desc->handle(irq, desc, regs);
131 * Timer interrupt handler
134 h7202_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
136 h7202_timerx_demux_handler(0, NULL, regs);
141 * mask multiplexed timer irq's
143 static void inline mask_timerx_irq (u32 irq)
146 bit = 2 << ((irq == IRQ_TIMER64B) ? 4 : (irq - IRQ_TIMER1));
147 CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) &= ~bit;
151 * unmask multiplexed timer irq's
153 static void inline unmask_timerx_irq (u32 irq)
156 bit = 2 << ((irq == IRQ_TIMER64B) ? 4 : (irq - IRQ_TIMER1));
157 CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) |= bit;
160 static struct irqchip h7202_timerx_chip = {
161 .ack = mask_timerx_irq,
162 .mask = mask_timerx_irq,
163 .unmask = unmask_timerx_irq,
166 static struct irqaction h7202_timer_irq = {
167 .name = "h7202 Timer Tick",
168 .flags = SA_INTERRUPT,
169 .handler = h7202_timer_interrupt
173 * Setup TIMER0 as system timer
175 void __init h7202_init_time(void)
177 CPU_REG (TIMER_VIRT, TM0_PERIOD) = LATCH;
178 CPU_REG (TIMER_VIRT, TM0_CTRL) = TM_RESET;
179 CPU_REG (TIMER_VIRT, TM0_CTRL) = TM_REPEAT | TM_START;
180 CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) = ENABLE_TM0_INTR | TIMER_ENABLE_BIT;
182 setup_irq(IRQ_TIMER0, &h7202_timer_irq);
185 struct sys_timer h7202_timer = {
186 .init = h7202_init_time,
187 .offset = h720x_gettimeoffset,
190 void __init h7202_init_irq (void)
194 CPU_REG (GPIO_E_VIRT, GPIO_MASK) = 0x0;
196 for (irq = IRQ_TIMER1;
197 irq < IRQ_CHAINED_TIMERX(NR_TIMERX_IRQS); irq++) {
198 mask_timerx_irq(irq);
199 set_irq_chip(irq, &h7202_timerx_chip);
200 set_irq_handler(irq, do_edge_IRQ);
201 set_irq_flags(irq, IRQF_VALID );
203 set_irq_chained_handler(IRQ_TIMERX, h7202_timerx_demux_handler);
208 void __init init_hw_h7202(void)
211 CPU_REG (PMU_BASE, PMU_PLL_CTRL) |= PLL_2_EN | PLL_1_EN | PLL_3_MUTE;
213 (void) platform_add_devices(devices, ARRAY_SIZE(devices));