2 * linux/arch/arm/mach-integrator/integrator_cp.c
4 * Copyright (C) 2003 Deep Blue Solutions Ltd
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License.
10 #include <linux/types.h>
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/list.h>
14 #include <linux/device.h>
15 #include <linux/slab.h>
16 #include <linux/string.h>
17 #include <linux/sysdev.h>
19 #include <asm/hardware.h>
22 #include <asm/setup.h>
23 #include <asm/mach-types.h>
24 #include <asm/hardware/amba.h>
25 #include <asm/hardware/amba_kmi.h>
26 #include <asm/hardware/icst525.h>
28 #include <asm/arch/lm.h>
30 #include <asm/mach/arch.h>
31 #include <asm/mach/flash.h>
32 #include <asm/mach/irq.h>
33 #include <asm/mach/mmc.h>
34 #include <asm/mach/map.h>
38 #define INTCP_PA_MMC_BASE 0x1c000000
39 #define INTCP_PA_AACI_BASE 0x1d000000
41 #define INTCP_PA_FLASH_BASE 0x24000000
42 #define INTCP_FLASH_SIZE SZ_32M
44 #define INTCP_PA_CLCD_BASE 0xc0000000
46 #define INTCP_VA_CIC_BASE 0xf1000040
47 #define INTCP_VA_PIC_BASE 0xf1400000
48 #define INTCP_VA_SIC_BASE 0xfca00000
50 #define INTCP_PA_ETH_BASE 0xc8000000
51 #define INTCP_ETH_SIZE 0x10
53 #define INTCP_VA_CTRL_BASE 0xfcb00000
54 #define INTCP_FLASHPROG 0x04
55 #define CINTEGRATOR_FLASHPROG_FLVPPEN (1 << 0)
56 #define CINTEGRATOR_FLASHPROG_FLWREN (1 << 1)
60 * f1000000 10000000 Core module registers
61 * f1100000 11000000 System controller registers
62 * f1200000 12000000 EBI registers
63 * f1300000 13000000 Counter/Timer
64 * f1400000 14000000 Interrupt controller
65 * f1600000 16000000 UART 0
66 * f1700000 17000000 UART 1
67 * f1a00000 1a000000 Debug LEDs
68 * f1b00000 1b000000 GPIO
71 static struct map_desc intcp_io_desc[] __initdata = {
72 { IO_ADDRESS(INTEGRATOR_HDR_BASE), INTEGRATOR_HDR_BASE, SZ_4K, MT_DEVICE },
73 { IO_ADDRESS(INTEGRATOR_SC_BASE), INTEGRATOR_SC_BASE, SZ_4K, MT_DEVICE },
74 { IO_ADDRESS(INTEGRATOR_EBI_BASE), INTEGRATOR_EBI_BASE, SZ_4K, MT_DEVICE },
75 { IO_ADDRESS(INTEGRATOR_CT_BASE), INTEGRATOR_CT_BASE, SZ_4K, MT_DEVICE },
76 { IO_ADDRESS(INTEGRATOR_IC_BASE), INTEGRATOR_IC_BASE, SZ_4K, MT_DEVICE },
77 { IO_ADDRESS(INTEGRATOR_UART0_BASE), INTEGRATOR_UART0_BASE, SZ_4K, MT_DEVICE },
78 { IO_ADDRESS(INTEGRATOR_UART1_BASE), INTEGRATOR_UART1_BASE, SZ_4K, MT_DEVICE },
79 { IO_ADDRESS(INTEGRATOR_DBG_BASE), INTEGRATOR_DBG_BASE, SZ_4K, MT_DEVICE },
80 { IO_ADDRESS(INTEGRATOR_GPIO_BASE), INTEGRATOR_GPIO_BASE, SZ_4K, MT_DEVICE },
81 { 0xfc900000, 0xc9000000, SZ_4K, MT_DEVICE },
82 { 0xfca00000, 0xca000000, SZ_4K, MT_DEVICE },
83 { 0xfcb00000, 0xcb000000, SZ_4K, MT_DEVICE },
86 static void __init intcp_map_io(void)
88 iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc));
91 #define cic_writel __raw_writel
92 #define cic_readl __raw_readl
93 #define pic_writel __raw_writel
94 #define pic_readl __raw_readl
95 #define sic_writel __raw_writel
96 #define sic_readl __raw_readl
98 static void cic_mask_irq(unsigned int irq)
100 irq -= IRQ_CIC_START;
101 cic_writel(1 << irq, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
104 static void cic_unmask_irq(unsigned int irq)
106 irq -= IRQ_CIC_START;
107 cic_writel(1 << irq, INTCP_VA_CIC_BASE + IRQ_ENABLE_SET);
110 static struct irqchip cic_chip = {
112 .mask = cic_mask_irq,
113 .unmask = cic_unmask_irq,
116 static void pic_mask_irq(unsigned int irq)
118 irq -= IRQ_PIC_START;
119 pic_writel(1 << irq, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
122 static void pic_unmask_irq(unsigned int irq)
124 irq -= IRQ_PIC_START;
125 pic_writel(1 << irq, INTCP_VA_PIC_BASE + IRQ_ENABLE_SET);
128 static struct irqchip pic_chip = {
130 .mask = pic_mask_irq,
131 .unmask = pic_unmask_irq,
134 static void sic_mask_irq(unsigned int irq)
136 irq -= IRQ_SIC_START;
137 sic_writel(1 << irq, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
140 static void sic_unmask_irq(unsigned int irq)
142 irq -= IRQ_SIC_START;
143 sic_writel(1 << irq, INTCP_VA_SIC_BASE + IRQ_ENABLE_SET);
146 static struct irqchip sic_chip = {
148 .mask = sic_mask_irq,
149 .unmask = sic_unmask_irq,
153 sic_handle_irq(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
155 unsigned long status = sic_readl(INTCP_VA_SIC_BASE + IRQ_STATUS);
158 do_bad_IRQ(irq, desc, regs);
163 irq = ffs(status) - 1;
164 status &= ~(1 << irq);
166 irq += IRQ_SIC_START;
168 desc = irq_desc + irq;
169 desc->handle(irq, desc, regs);
173 static void __init intcp_init_irq(void)
178 * Disable all interrupt sources
180 pic_writel(0xffffffff, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
181 pic_writel(0xffffffff, INTCP_VA_PIC_BASE + FIQ_ENABLE_CLEAR);
183 for (i = IRQ_PIC_START; i <= IRQ_PIC_END; i++) {
186 if (i == IRQ_CP_CPPLDINT)
190 set_irq_chip(i, &pic_chip);
191 set_irq_handler(i, do_level_IRQ);
192 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
195 cic_writel(0xffffffff, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
196 cic_writel(0xffffffff, INTCP_VA_CIC_BASE + FIQ_ENABLE_CLEAR);
198 for (i = IRQ_CIC_START; i <= IRQ_CIC_END; i++) {
199 set_irq_chip(i, &cic_chip);
200 set_irq_handler(i, do_level_IRQ);
201 set_irq_flags(i, IRQF_VALID);
204 sic_writel(0x00000fff, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
205 sic_writel(0x00000fff, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR);
207 for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) {
208 set_irq_chip(i, &sic_chip);
209 set_irq_handler(i, do_level_IRQ);
210 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
213 set_irq_handler(IRQ_CP_CPPLDINT, sic_handle_irq);
214 pic_unmask_irq(IRQ_CP_CPPLDINT);
220 #define CM_LOCK (IO_ADDRESS(INTEGRATOR_HDR_BASE)+INTEGRATOR_HDR_LOCK_OFFSET)
221 #define CM_AUXOSC (IO_ADDRESS(INTEGRATOR_HDR_BASE)+0x1c)
223 static const struct icst525_params cp_auxvco_params = {
232 static void cp_auxvco_set(struct clk *clk, struct icst525_vco vco)
236 val = readl(CM_AUXOSC) & ~0x7ffff;
237 val |= vco.v | (vco.r << 9) | (vco.s << 16);
239 writel(0xa05f, CM_LOCK);
240 writel(val, CM_AUXOSC);
244 static struct clk cp_clcd_clk = {
246 .params = &cp_auxvco_params,
247 .setvco = cp_auxvco_set,
250 static struct clk cp_mmci_clk = {
258 static int intcp_flash_init(void)
262 val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
263 val |= CINTEGRATOR_FLASHPROG_FLWREN;
264 writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
269 static void intcp_flash_exit(void)
273 val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
274 val &= ~(CINTEGRATOR_FLASHPROG_FLVPPEN|CINTEGRATOR_FLASHPROG_FLWREN);
275 writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
278 static void intcp_flash_set_vpp(int on)
282 val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
284 val |= CINTEGRATOR_FLASHPROG_FLVPPEN;
286 val &= ~CINTEGRATOR_FLASHPROG_FLVPPEN;
287 writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
290 static struct flash_platform_data intcp_flash_data = {
291 .map_name = "cfi_probe",
293 .init = intcp_flash_init,
294 .exit = intcp_flash_exit,
295 .set_vpp = intcp_flash_set_vpp,
298 static struct resource intcp_flash_resource = {
299 .start = INTCP_PA_FLASH_BASE,
300 .end = INTCP_PA_FLASH_BASE + INTCP_FLASH_SIZE - 1,
301 .flags = IORESOURCE_MEM,
304 static struct platform_device intcp_flash_device = {
308 .platform_data = &intcp_flash_data,
311 .resource = &intcp_flash_resource,
314 static struct resource smc91x_resources[] = {
316 .start = INTCP_PA_ETH_BASE,
317 .end = INTCP_PA_ETH_BASE + INTCP_ETH_SIZE - 1,
318 .flags = IORESOURCE_MEM,
321 .start = IRQ_CP_ETHINT,
322 .end = IRQ_CP_ETHINT,
323 .flags = IORESOURCE_IRQ,
327 static struct platform_device smc91x_device = {
330 .num_resources = ARRAY_SIZE(smc91x_resources),
331 .resource = smc91x_resources,
334 static struct platform_device *intcp_devs[] __initdata = {
340 * It seems that the card insertion interrupt remains active after
341 * we've acknowledged it. We therefore ignore the interrupt, and
342 * rely on reading it from the SIC. This also means that we must
343 * clear the latched interrupt.
345 static unsigned int mmc_status(struct device *dev)
347 unsigned int status = readl(0xfca00004);
348 writel(8, 0xfcb00008);
353 static struct mmc_platform_data mmc_data = {
354 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
355 .status = mmc_status,
358 static struct amba_device mmc_device = {
361 .platform_data = &mmc_data,
364 .start = INTCP_PA_MMC_BASE,
365 .end = INTCP_PA_MMC_BASE + SZ_4K - 1,
366 .flags = IORESOURCE_MEM,
368 .irq = { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 },
372 static struct amba_device aaci_device = {
377 .start = INTCP_PA_AACI_BASE,
378 .end = INTCP_PA_AACI_BASE + SZ_4K - 1,
379 .flags = IORESOURCE_MEM,
381 .irq = { IRQ_CP_AACIINT, NO_IRQ },
385 static struct amba_device clcd_device = {
388 .coherent_dma_mask = ~0,
391 .start = INTCP_PA_CLCD_BASE,
392 .end = INTCP_PA_CLCD_BASE + SZ_4K - 1,
393 .flags = IORESOURCE_MEM,
396 .irq = { IRQ_CP_CLCDCINT, NO_IRQ },
400 static struct amba_device *amba_devs[] __initdata = {
406 static void __init intcp_init(void)
410 clk_register(&cp_clcd_clk);
411 clk_register(&cp_mmci_clk);
413 platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs));
415 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
416 struct amba_device *d = amba_devs[i];
417 amba_device_register(d, &iomem_resource);
421 #define TIMER_CTRL_IE (1 << 5) /* Interrupt Enable */
423 static void __init intcp_init_time(void)
425 integrator_time_init(1000000 / HZ, TIMER_CTRL_IE);
428 MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
429 MAINTAINER("ARM Ltd/Deep Blue Solutions Ltd")
430 BOOT_MEM(0x00000000, 0x16000000, 0xf1600000)
431 BOOT_PARAMS(0x00000100)
433 INITIRQ(intcp_init_irq)
434 INITTIME(intcp_init_time)
435 INIT_MACHINE(intcp_init)