2 * arch/arm/mach-iop3xx/iop331-pci.c
4 * PCI support for the Intel IOP331 chipset
6 * Author: Dave Jiang (dave.jiang@intel.com)
7 * Copyright (C) 2003 Intel Corp.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/kernel.h>
15 #include <linux/pci.h>
16 #include <linux/slab.h>
18 #include <linux/init.h>
19 #include <linux/ioport.h>
23 #include <asm/system.h>
24 #include <asm/hardware.h>
25 #include <asm/mach/pci.h>
27 #include <asm/arch/iop331.h>
32 #define DBG(x...) printk(x)
34 #define DBG(x...) do { } while (0)
38 * This routine builds either a type0 or type1 configuration command. If the
39 * bus is on the 80331 then a type0 made, else a type1 is created.
41 static u32 iop331_cfg_address(struct pci_bus *bus, int devfn, int where)
43 struct pci_sys_data *sys = bus->sysdata;
46 if (sys->busnr == bus->number)
47 addr = 1 << (PCI_SLOT(devfn) + 16) | (PCI_SLOT(devfn) << 11);
49 addr = bus->number << 16 | PCI_SLOT(devfn) << 11 | 1;
51 addr |= PCI_FUNC(devfn) << 8 | (where & ~3);
57 * This routine checks the status of the last configuration cycle. If an error
58 * was detected it returns a 1, else it returns a 0. The errors being checked
59 * are parity, master abort, target abort (master and target). These types of
60 * errors occure during a config cycle where there is no device, like during
61 * the discovery stage.
63 static int iop331_pci_status(void)
69 * Check the status registers.
71 status = *IOP331_ATUSR;
74 DBG("\t\t\tPCI: P0 - status = 0x%08x\n", status);
75 *IOP331_ATUSR = status & 0xf900;
78 status = *IOP331_ATUISR;
81 DBG("\t\t\tPCI: P1 - status = 0x%08x\n", status);
82 *IOP331_ATUISR = status & 0x679f;
89 * Simply write the address register and read the configuration
90 * data. Note that the 4 nop's ensure that we are able to handle
91 * a delayed abort (in theory.)
93 static inline u32 iop331_read(unsigned long addr)
105 : "r" (addr), "r" (IOP331_OCCAR), "r" (IOP331_OCCDR));
111 * The read routines must check the error status of the last configuration
112 * cycle. If there was an error, the routine returns all hex f's.
115 iop331_read_config(struct pci_bus *bus, unsigned int devfn, int where,
116 int size, u32 *value)
118 unsigned long addr = iop331_cfg_address(bus, devfn, where);
119 u32 val = iop331_read(addr) >> ((where & 3) * 8);
121 if( iop331_pci_status() )
126 return PCIBIOS_SUCCESSFUL;
130 iop331_write_config(struct pci_bus *bus, unsigned int devfn, int where,
133 unsigned long addr = iop331_cfg_address(bus, devfn, where);
137 val = iop331_read(addr);
138 if (!iop331_pci_status() == 0)
139 return PCIBIOS_SUCCESSFUL;
141 where = (where & 3) * 8;
144 val &= ~(0xff << where);
146 val &= ~(0xffff << where);
148 *IOP331_OCCDR = val | value << where;
158 : "r" (value), "r" (addr),
159 "r" (IOP331_OCCAR), "r" (IOP331_OCCDR));
162 return PCIBIOS_SUCCESSFUL;
165 static struct pci_ops iop331_ops = {
166 .read = iop331_read_config,
167 .write = iop331_write_config,
171 * When a PCI device does not exist during config cycles, the XScale gets a
172 * bus error instead of returning 0xffffffff. This handler simply returns.
175 iop331_pci_abort(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
177 DBG("PCI abort: address = 0x%08lx fsr = 0x%03x PC = 0x%08lx LR = 0x%08lx\n",
178 addr, fsr, regs->ARM_pc, regs->ARM_lr);
181 * If it was an imprecise abort, then we need to correct the
182 * return address to be _after_ the instruction.
191 * Scan an IOP331 PCI bus. sys->bus defines which bus we scan.
193 struct pci_bus *iop331_scan_bus(int nr, struct pci_sys_data *sys)
195 return pci_scan_bus(sys->busnr, &iop331_ops, sys);
198 void iop331_init(void)
200 DBG("PCI: Intel 80331 PCI init code.\n");
201 DBG("\tATU: IOP331_ATUCMD=0x%04x\n", *IOP331_ATUCMD);
202 DBG("\tATU: IOP331_OMWTVR0=0x%04x, IOP331_OIOWTVR=0x%04x\n",
205 DBG("\tATU: IOP331_ATUCR=0x%08x\n", *IOP331_ATUCR);
206 DBG("\tATU: IOP331_IABAR0=0x%08x IOP331_IALR0=0x%08x IOP331_IATVR0=%08x\n", *IOP331_IABAR0, *IOP331_IALR0, *IOP331_IATVR0);
207 DBG("\tATU: IOP331_ERBAR=0x%08x IOP331_ERLR=0x%08x IOP331_ERTVR=%08x\n", *IOP331_ERBAR, *IOP331_ERLR, *IOP331_ERTVR);
208 DBG("\tATU: IOP331_IABAR2=0x%08x IOP331_IALR2=0x%08x IOP331_IATVR2=%08x\n", *IOP331_IABAR2, *IOP331_IALR2, *IOP331_IATVR2);
209 DBG("\tATU: IOP331_IABAR3=0x%08x IOP331_IALR3=0x%08x IOP331_IATVR3=%08x\n", *IOP331_IABAR3, *IOP331_IALR3, *IOP331_IATVR3);
211 /* redboot changed, reset IABAR0 to something sane */
212 /* fixes master aborts in plugged in cards */
213 /* will clean up later and work nicely with redboot */
214 *IOP331_IABAR0 = 0x00000004;
215 hook_fault_code(16+6, iop331_pci_abort, SIGBUS, "imprecise external abort");