2 config ARCH_SUPPORTS_BIG_ENDIAN
7 menu "Intel IXP4xx Implementation Options"
9 comment "IXP4xx Platforms"
13 depends on ARCH_IXP4XX
15 Say 'Y' here if you want your kernel to support the Gateworks
16 Avila Network Platform. For more information on this platform,
17 see Documentation/arm/IXP4xx.
19 config ARCH_ADI_COYOTE
21 depends on ARCH_IXP4XX
23 Say 'Y' here if you want your kernel to support the ADI
24 Engineering Coyote Gateway Reference Platform. For more
25 information on this platform, see Documentation/arm/IXP4xx.
29 depends on ARCH_IXP4XX
31 Say 'Y' here if you want your kernel to support Intel's
32 IXDP425 Development Platform (Also known as Richfield).
33 For more information on this platform, see Documentation/arm/IXP4xx.
36 # IXCDP1100 is the exact same HW as IXDP425, but with a different machine
37 # number from the bootloader due to marketing monkeys, so we just enable it
38 # by default if IXDP425 is enabled.
42 depends on ARCH_IXDP425
47 depends on ARCH_IXP4XX
49 Say 'Y' here if you want your kernel to support the Motorola
50 PrPCM1100 Processor Mezanine Module. For more information on
51 this platform, see Documentation/arm/IXP4xx.
54 # Avila and IXDP share the same source for now. Will change in future
58 depends on ARCH_IXDP425 || ARCH_AVILA
61 comment "IXP4xx Options"
63 config IXP4XX_INDIRECT_PCI
64 bool "Use indirect PCI memory access"
65 depends on ARCH_IXP4XX
67 IXP4xx provides two methods of accessing PCI memory space:
69 1) A direct mapped window from 0x48000000 to 0x4bffffff (64MB).
70 To access PCI via this space, we simply ioremap() the BAR
71 into the kernel and we can use the standard read[bwl]/write[bwl]
72 macros. This is the preffered method due to speed but it
73 limits the system to just 64MB of PCI memory. This can be
74 problamatic if using video cards and other memory-heavy devices.
76 2) If > 64MB of memory space is required, the IXP4xx can be
77 configured to use indirect registers to access PCI This allows
78 for up to 128MB (0x48000000 to 0x4fffffff) of memory on the bus.
79 The disadvantadge of this is that every PCI access requires
80 three local register accesses plus a spinlock, but in some
81 cases the performance hit is acceptable. In addition, you cannot
82 mmap() PCI devices in this case due to the indirect nature
85 By default, the direct method is used. Choose this option if you
86 need to use the indirect method instead. If you don't know
87 what you need, leave this option unselected.