2 * arch/arm/mach-ixp4xx/common-pci.c
4 * IXP4XX PCI routines for all platforms
6 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
8 * Copyright (C) 2002 Intel Corporation.
9 * Copyright (C) 2003 Greg Ungerer <gerg@snapgear.com>
10 * Copyright (C) 2003-2004 MontaVista Software, Inc.
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
18 #include <linux/sched.h>
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/interrupt.h>
23 #include <linux/init.h>
24 #include <linux/ioport.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
27 #include <linux/device.h>
28 #include <asm/dma-mapping.h>
32 #include <asm/sizes.h>
33 #include <asm/system.h>
34 #include <asm/mach/pci.h>
35 #include <asm/hardware.h>
36 #include <asm/sizes.h>
40 * IXP4xx PCI read function is dependent on whether we are
41 * running A0 or B0 (AppleGate) silicon.
43 int (*ixp4xx_pci_read)(u32 addr, u32 cmd, u32* data);
46 * Base address for PCI regsiter region
48 unsigned long ixp4xx_pci_reg_base = 0;
51 * PCI cfg an I/O routines are done by programming a
52 * command/byte enable register, and then read/writing
53 * the data from a data regsiter. We need to ensure
54 * these transactions are atomic or we will end up
55 * with corrupt data on the bus or in a driver.
57 static spinlock_t ixp4xx_pci_lock = SPIN_LOCK_UNLOCKED;
60 * Read from PCI config space
62 static void crp_read(u32 ad_cbe, u32 *data)
65 spin_lock_irqsave(&ixp4xx_pci_lock, flags);
66 *PCI_CRP_AD_CBE = ad_cbe;
67 *data = *PCI_CRP_RDATA;
68 spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
72 * Write to PCI config space
74 static void crp_write(u32 ad_cbe, u32 data)
77 spin_lock_irqsave(&ixp4xx_pci_lock, flags);
78 *PCI_CRP_AD_CBE = CRP_AD_CBE_WRITE | ad_cbe;
79 *PCI_CRP_WDATA = data;
80 spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
83 static inline int check_master_abort(void)
85 /* check Master Abort bit after access */
86 unsigned long isr = *PCI_ISR;
88 if (isr & PCI_ISR_PFE) {
89 /* make sure the Master Abort bit is reset */
90 *PCI_ISR = PCI_ISR_PFE;
91 pr_debug("%s failed\n", __FUNCTION__);
98 int ixp4xx_pci_read_errata(u32 addr, u32 cmd, u32* data)
104 spin_lock_irqsave(&ixp4xx_pci_lock, flags);
109 * PCI workaround - only works if NP PCI space reads have
110 * no side effects!!! Read 8 times. last one will be good.
112 for (i = 0; i < 8; i++) {
114 *data = *PCI_NP_RDATA;
115 *data = *PCI_NP_RDATA;
118 if(check_master_abort())
121 spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
125 int ixp4xx_pci_read_no_errata(u32 addr, u32 cmd, u32* data)
130 spin_lock_irqsave(&ixp4xx_pci_lock, flags);
134 /* set up and execute the read */
137 /* the result of the read is now in NP_RDATA */
138 *data = *PCI_NP_RDATA;
140 if(check_master_abort())
143 spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
147 int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data)
152 spin_lock_irqsave(&ixp4xx_pci_lock, flags);
156 /* set up the write */
159 /* execute the write by writing to NP_WDATA */
160 *PCI_NP_WDATA = data;
162 if(check_master_abort())
165 spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
169 static u32 ixp4xx_config_addr(u8 bus_num, u16 devfn, int where)
174 addr = BIT(32-PCI_SLOT(devfn)) | ((PCI_FUNC(devfn)) << 8) |
178 addr = (bus_num << 16) | ((PCI_SLOT(devfn)) << 11) |
179 ((PCI_FUNC(devfn)) << 8) | (where & ~3) | 1;
185 * Mask table, bits to mask for quantity of size 1, 2 or 4 bytes.
186 * 0 and 3 are not valid indexes...
188 static u32 bytemask[] = {
196 static u32 local_byte_lane_enable_bits(u32 n, int size)
199 return (0xf & ~BIT(n)) << CRP_AD_CBE_BESL;
201 return (0xf & ~(BIT(n) | BIT(n+1))) << CRP_AD_CBE_BESL;
207 static int local_read_config(int where, int size, u32 *value)
210 pr_debug("local_read_config from %d size %d\n", where, size);
212 crp_read(where & ~3, &data);
213 *value = (data >> (8*n)) & bytemask[size];
214 pr_debug("local_read_config read %#x\n", *value);
215 return PCIBIOS_SUCCESSFUL;
218 static int local_write_config(int where, int size, u32 value)
220 u32 n, byte_enables, data;
221 pr_debug("local_write_config %#x to %d size %d\n", value, where, size);
223 byte_enables = local_byte_lane_enable_bits(n, size);
224 if (byte_enables == 0xffffffff)
225 return PCIBIOS_BAD_REGISTER_NUMBER;
226 data = value << (8*n);
227 crp_write((where & ~3) | byte_enables, data);
228 return PCIBIOS_SUCCESSFUL;
231 static u32 byte_lane_enable_bits(u32 n, int size)
234 return (0xf & ~BIT(n)) << 4;
236 return (0xf & ~(BIT(n) | BIT(n+1))) << 4;
242 static int read_config(u8 bus_num, u16 devfn, int where, int size, u32 *value)
244 u32 n, byte_enables, addr, data;
246 pr_debug("read_config from %d size %d dev %d:%d:%d\n", where, size,
247 bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn));
251 byte_enables = byte_lane_enable_bits(n, size);
252 if (byte_enables == 0xffffffff)
253 return PCIBIOS_BAD_REGISTER_NUMBER;
255 addr = ixp4xx_config_addr(bus_num, devfn, where);
256 if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_CONFIGREAD, &data))
257 return PCIBIOS_DEVICE_NOT_FOUND;
259 *value = (data >> (8*n)) & bytemask[size];
260 pr_debug("read_config_byte read %#x\n", *value);
261 return PCIBIOS_SUCCESSFUL;
264 static int write_config(u8 bus_num, u16 devfn, int where, int size, u32 value)
266 u32 n, byte_enables, addr, data;
268 pr_debug("write_config_byte %#x to %d size %d dev %d:%d:%d\n", value, where,
269 size, bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn));
272 byte_enables = byte_lane_enable_bits(n, size);
273 if (byte_enables == 0xffffffff)
274 return PCIBIOS_BAD_REGISTER_NUMBER;
276 addr = ixp4xx_config_addr(bus_num, devfn, where);
277 data = value << (8*n);
278 if (ixp4xx_pci_write(addr, byte_enables | NP_CMD_CONFIGWRITE, data))
279 return PCIBIOS_DEVICE_NOT_FOUND;
281 return PCIBIOS_SUCCESSFUL;
285 * Generalized PCI config access functions.
287 static int ixp4xx_read_config(struct pci_bus *bus, unsigned int devfn,
288 int where, int size, u32 *value)
290 if (bus->number && !PCI_SLOT(devfn))
291 return local_read_config(where, size, value);
292 return read_config(bus->number, devfn, where, size, value);
295 static int ixp4xx_write_config(struct pci_bus *bus, unsigned int devfn,
296 int where, int size, u32 value)
298 if (bus->number && !PCI_SLOT(devfn))
299 return local_write_config(where, size, value);
300 return write_config(bus->number, devfn, where, size, value);
303 struct pci_ops ixp4xx_ops = {
304 .read = ixp4xx_read_config,
305 .write = ixp4xx_write_config,
312 static int abort_handler(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
317 local_read_config(PCI_STATUS, 2, &status);
318 pr_debug("PCI: abort_handler addr = %#lx, isr = %#x, "
319 "status = %#x\n", addr, isr, status);
321 /* make sure the Master Abort bit is reset */
322 *PCI_ISR = PCI_ISR_PFE;
323 status |= PCI_STATUS_REC_MASTER_ABORT;
324 local_write_config(PCI_STATUS, 2, status);
327 * If it was an imprecise abort, then we need to correct the
328 * return address to be _after_ the instruction.
338 * Setup DMA mask to 64MB on PCI devices. Ignore all other devices.
340 static int ixp4xx_pci_platform_notify(struct device *dev)
342 if(dev->bus == &pci_bus_type) {
343 *dev->dma_mask = SZ_64M - 1;
344 dev->coherent_dma_mask = SZ_64M - 1;
345 dmabounce_register_dev(dev, 2048, 4096);
350 static int ixp4xx_pci_platform_notify_remove(struct device *dev)
352 if(dev->bus == &pci_bus_type) {
353 dmabounce_unregister_dev(dev);
358 int dma_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size)
360 return (dev->bus == &pci_bus_type ) && ((dma_addr + size) >= SZ_64M);
363 void __init ixp4xx_pci_preinit(void)
365 unsigned long processor_id;
367 asm("mrc p15, 0, %0, cr0, cr0, 0;" : "=r"(processor_id) :);
370 * Determine which PCI read method to use
372 if (!(processor_id & 0xf)) {
373 printk("PCI: IXP4xx A0 silicon detected - "
374 "PCI Non-Prefetch Workaround Enabled\n");
375 ixp4xx_pci_read = ixp4xx_pci_read_errata;
377 ixp4xx_pci_read = ixp4xx_pci_read_no_errata;
380 /* hook in our fault handler for PCI errors */
381 hook_fault_code(16+6, abort_handler, SIGBUS, "imprecise external abort");
383 pr_debug("setup PCI-AHB(inbound) and AHB-PCI(outbound) address mappings\n");
386 * We use identity AHB->PCI address translation
387 * in the 0x48000000 to 0x4bffffff address space
389 *PCI_PCIMEMBASE = 0x48494A4B;
392 * We also use identity PCI->AHB address translation
393 * in 4 16MB BARs that begin at the physical memory start
395 *PCI_AHBMEMBASE = (PHYS_OFFSET & 0xFF000000) +
396 ((PHYS_OFFSET & 0xFF000000) >> 8) +
397 ((PHYS_OFFSET & 0xFF000000) >> 16) +
398 ((PHYS_OFFSET & 0xFF000000) >> 24) +
401 if (*PCI_CSR & PCI_CSR_HOST) {
402 printk("PCI: IXP4xx is host\n");
404 pr_debug("setup BARs in controller\n");
407 * We configure the PCI inbound memory windows to be
408 * 1:1 mapped to SDRAM
410 local_write_config(PCI_BASE_ADDRESS_0, 4, PHYS_OFFSET + 0x00000000);
411 local_write_config(PCI_BASE_ADDRESS_1, 4, PHYS_OFFSET + 0x01000000);
412 local_write_config(PCI_BASE_ADDRESS_2, 4, PHYS_OFFSET + 0x02000000);
413 local_write_config(PCI_BASE_ADDRESS_3, 4, PHYS_OFFSET + 0x03000000);
416 * Enable CSR window at 0xff000000.
418 local_write_config(PCI_BASE_ADDRESS_4, 4, 0xff000008);
421 * Enable the IO window to be way up high, at 0xfffffc00
423 local_write_config(PCI_BASE_ADDRESS_5, 4, 0xfffffc01);
425 printk("PCI: IXP4xx is target - No bus scan performed\n");
428 printk("PCI: IXP4xx Using %s access for memory space\n",
429 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
436 pr_debug("clear error bits in ISR\n");
437 *PCI_ISR = PCI_ISR_PSE | PCI_ISR_PFE | PCI_ISR_PPE | PCI_ISR_AHBE;
440 * Set Initialize Complete in PCI Control Register: allow IXP4XX to
441 * respond to PCI configuration cycles. Specify that the AHB bus is
442 * operating in big endian mode. Set up byte lane swapping between
443 * little-endian PCI and the big-endian AHB bus
446 *PCI_CSR = PCI_CSR_IC | PCI_CSR_ABE | PCI_CSR_PDS | PCI_CSR_ADS;
448 *PCI_CSR = PCI_CSR_IC;
454 int ixp4xx_setup(int nr, struct pci_sys_data *sys)
456 struct resource *res;
461 res = kmalloc(sizeof(*res) * 2, GFP_KERNEL);
464 * If we're out of memory this early, something is wrong,
465 * so we might as well catch it here.
467 panic("PCI: unable to allocate resources?\n");
469 memset(res, 0, sizeof(*res) * 2);
471 local_write_config(PCI_COMMAND, 2, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
473 res[0].name = "PCI I/O Space";
474 res[0].start = 0x00001000;
475 res[0].end = 0xffff0000;
476 res[0].flags = IORESOURCE_IO;
478 res[1].name = "PCI Memory Space";
479 res[1].start = 0x48000000;
480 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
481 res[1].end = 0x4bffffff;
483 res[1].end = 0x4fffffff;
485 res[1].flags = IORESOURCE_MEM;
487 request_resource(&ioport_resource, &res[0]);
488 request_resource(&iomem_resource, &res[1]);
490 sys->resource[0] = &res[0];
491 sys->resource[1] = &res[1];
492 sys->resource[2] = NULL;
494 platform_notify = ixp4xx_pci_platform_notify;
495 platform_notify_remove = ixp4xx_pci_platform_notify_remove;
500 struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys)
502 return pci_scan_bus(sys->busnr, &ixp4xx_ops, sys);
506 * We override these so we properly do dmabounce otherwise drivers
507 * are able to set the dma_mask to 0xffffffff and we can no longer
510 * We just return true on everyhing except for < 64MB in which case
511 * we will fail miseralby and die since we can't handle that case.
514 pci_set_dma_mask(struct pci_dev *dev, u64 mask)
516 if (mask >= SZ_64M - 1 )
523 pci_dac_set_dma_mask(struct pci_dev *dev, u64 mask)
525 if (mask >= SZ_64M - 1 )
532 pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
534 if (mask >= SZ_64M - 1 )
540 EXPORT_SYMBOL(pci_set_dma_mask);
541 EXPORT_SYMBOL(pci_dac_set_dma_mask);
542 EXPORT_SYMBOL(pci_set_consistent_dma_mask);
543 EXPORT_SYMBOL(ixp4xx_pci_read);
544 EXPORT_SYMBOL(ixp4xx_pci_write);