1 /* linux/arch/arm/mach-bast/dma.c
3 * (c) 2003,2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
8 * http://www.simtec.co.uk/products/EB2410ITX/
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 * 18-Nov-2004 BJD Removed error for loading onto stopped channel
16 * 10-Nov-2004 BJD Ensure all external symbols exported for modules
17 * 10-Nov-2004 BJD Use sys_device and sysdev_class for power management
18 * 08-Aug-2004 BJD Apply rmk's suggestions
19 * 21-Jul-2004 BJD Ported to linux 2.6
20 * 12-Jul-2004 BJD Finished re-write and change of API
21 * 06-Jul-2004 BJD Rewrote dma code to try and cope with various problems
22 * 23-May-2003 BJD Created file
23 * 19-Aug-2003 BJD Cleanup, header fix, added URL
25 * This file is based on the Sangwook Lee/Samsung patches, re-written due
26 * to various ommisions from the code (such as flexible dma configuration)
27 * for use with the BAST system board.
29 * The re-write is pretty much complete, and should be good enough for any
30 * possible DMA function
33 #include <linux/config.h>
35 #ifdef CONFIG_S3C2410_DMA_DEBUG
39 #include <linux/module.h>
40 #include <linux/init.h>
41 #include <linux/sched.h>
42 #include <linux/spinlock.h>
43 #include <linux/interrupt.h>
44 #include <linux/sysdev.h>
45 #include <linux/slab.h>
46 #include <linux/errno.h>
47 #include <linux/delay.h>
49 #include <asm/system.h>
51 #include <asm/hardware.h>
55 #include <asm/mach/dma.h>
56 #include <asm/arch/map.h>
59 static void __iomem *dma_base;
61 /* dma channel state information */
62 s3c2410_dma_chan_t s3c2410_chans[S3C2410_DMA_CHANNELS];
64 /* debugging functions */
66 #define BUF_MAGIC (0xcafebabe)
68 #define dmawarn(fmt...) printk(KERN_DEBUG fmt)
70 #define dma_regaddr(chan, reg) ((chan)->regs + (reg))
73 #define dma_wrreg(chan, reg, val) writel((val), (chan)->regs + (reg))
76 dma_wrreg(s3c2410_dma_chan_t *chan, int reg, unsigned long val)
78 pr_debug("writing %08x to register %08x\n",(unsigned int)val,reg);
79 writel(val, dma_regaddr(chan, reg));
84 #define dma_rdreg(chan, reg) readl((chan)->regs + (reg))
86 /* captured register state for debug */
88 struct s3c2410_dma_regstate {
93 unsigned long dmsktrig;
96 #ifdef CONFIG_S3C2410_DMA_DEBUG
100 * simple debug routine to print the current state of the dma registers
104 dmadbg_capture(s3c2410_dma_chan_t *chan, struct s3c2410_dma_regstate *regs)
106 regs->dcsrc = dma_rdreg(chan, S3C2410_DMA_DCSRC);
107 regs->disrc = dma_rdreg(chan, S3C2410_DMA_DISRC);
108 regs->dstat = dma_rdreg(chan, S3C2410_DMA_DSTAT);
109 regs->dcon = dma_rdreg(chan, S3C2410_DMA_DCON);
110 regs->dmsktrig = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG);
114 dmadbg_showregs(const char *fname, int line, s3c2410_dma_chan_t *chan,
115 struct s3c2410_dma_regstate *regs)
117 printk(KERN_DEBUG "dma%d: %s:%d: DCSRC=%08lx, DISRC=%08lx, DSTAT=%08lx DMT=%02lx, DCON=%08lx\n",
118 chan->number, fname, line,
119 regs->dcsrc, regs->disrc, regs->dstat, regs->dmsktrig,
124 dmadbg_showchan(const char *fname, int line, s3c2410_dma_chan_t *chan)
126 struct s3c2410_dma_regstate state;
128 dmadbg_capture(chan, &state);
130 printk(KERN_DEBUG "dma%d: %s:%d: ls=%d, cur=%p, %p %p\n",
131 chan->number, fname, line, chan->load_state,
132 chan->curr, chan->next, chan->end);
134 dmadbg_showregs(fname, line, chan, &state);
137 #define dbg_showregs(chan) dmadbg_showregs(__FUNCTION__, __LINE__, (chan))
138 #define dbg_showchan(chan) dmadbg_showchan(__FUNCTION__, __LINE__, (chan))
140 #define dbg_showregs(chan) do { } while(0)
141 #define dbg_showchan(chan) do { } while(0)
142 #endif /* CONFIG_S3C2410_DMA_DEBUG */
144 #define check_channel(chan) \
145 do { if ((chan) >= S3C2410_DMA_CHANNELS) { \
146 printk(KERN_ERR "%s: invalid channel %d\n", __FUNCTION__, (chan)); \
151 /* s3c2410_dma_stats_timeout
153 * Update DMA stats from timeout info
157 s3c2410_dma_stats_timeout(s3c2410_dma_stats_t *stats, int val)
162 if (val > stats->timeout_longest)
163 stats->timeout_longest = val;
164 if (val < stats->timeout_shortest)
165 stats->timeout_shortest = val;
167 stats->timeout_avg += val;
170 /* s3c2410_dma_waitforload
172 * wait for the DMA engine to load a buffer, and update the state accordingly
176 s3c2410_dma_waitforload(s3c2410_dma_chan_t *chan, int line)
178 int timeout = chan->load_timeout;
181 if (chan->load_state != S3C2410_DMALOAD_1LOADED) {
182 printk(KERN_ERR "dma%d: s3c2410_dma_waitforload() called in loadstate %d from line %d\n", chan->number, chan->load_state, line);
186 if (chan->stats != NULL)
187 chan->stats->loads++;
189 while (--timeout > 0) {
190 if ((dma_rdreg(chan, S3C2410_DMA_DSTAT) << (32-20)) != 0) {
191 took = chan->load_timeout - timeout;
193 s3c2410_dma_stats_timeout(chan->stats, took);
195 switch (chan->load_state) {
196 case S3C2410_DMALOAD_1LOADED:
197 chan->load_state = S3C2410_DMALOAD_1RUNNING;
201 printk(KERN_ERR "dma%d: unknown load_state in s3c2410_dma_waitforload() %d\n", chan->number, chan->load_state);
208 if (chan->stats != NULL) {
209 chan->stats->timeout_failed++;
217 /* s3c2410_dma_loadbuffer
219 * load a buffer, and update the channel state
223 s3c2410_dma_loadbuffer(s3c2410_dma_chan_t *chan,
224 s3c2410_dma_buf_t *buf)
226 unsigned long reload;
228 pr_debug("s3c2410_chan_loadbuffer: loading buff %p (0x%08lx,0x%06x)\n",
229 buf, (unsigned long)buf->data, buf->size);
232 dmawarn("buffer is NULL\n");
236 /* check the state of the channel before we do anything */
238 if (chan->load_state == S3C2410_DMALOAD_1LOADED) {
239 dmawarn("load_state is S3C2410_DMALOAD_1LOADED\n");
242 if (chan->load_state == S3C2410_DMALOAD_1LOADED_1RUNNING) {
243 dmawarn("state is S3C2410_DMALOAD_1LOADED_1RUNNING\n");
246 /* it would seem sensible if we are the last buffer to not bother
247 * with the auto-reload bit, so that the DMA engine will not try
248 * and load another transfer after this one has finished...
250 if (chan->load_state == S3C2410_DMALOAD_NONE) {
251 pr_debug("load_state is none, checking for noreload (next=%p)\n",
253 reload = (buf->next == NULL) ? S3C2410_DCON_NORELOAD : 0;
255 pr_debug("load_state is %d => autoreload\n", chan->load_state);
256 reload = S3C2410_DCON_AUTORELOAD;
259 writel(buf->data, chan->addr_reg);
261 dma_wrreg(chan, S3C2410_DMA_DCON,
262 chan->dcon | reload | (buf->size/chan->xfer_unit));
264 chan->next = buf->next;
266 /* update the state of the channel */
268 switch (chan->load_state) {
269 case S3C2410_DMALOAD_NONE:
270 chan->load_state = S3C2410_DMALOAD_1LOADED;
273 case S3C2410_DMALOAD_1RUNNING:
274 chan->load_state = S3C2410_DMALOAD_1LOADED_1RUNNING;
278 dmawarn("dmaload: unknown state %d in loadbuffer\n",
286 /* s3c2410_dma_call_op
288 * small routine to call the op routine with the given op if it has been
293 s3c2410_dma_call_op(s3c2410_dma_chan_t *chan, s3c2410_chan_op_t op)
295 if (chan->op_fn != NULL) {
296 (chan->op_fn)(chan, op);
300 /* s3c2410_dma_buffdone
302 * small wrapper to check if callback routine needs to be called, and
307 s3c2410_dma_buffdone(s3c2410_dma_chan_t *chan, s3c2410_dma_buf_t *buf,
308 s3c2410_dma_buffresult_t result)
310 pr_debug("callback_fn=%p, buf=%p, id=%p, size=%d, result=%d\n",
311 chan->callback_fn, buf, buf->id, buf->size, result);
313 if (chan->callback_fn != NULL) {
314 (chan->callback_fn)(chan, buf->id, buf->size, result);
320 * start a dma channel going
323 static int s3c2410_dma_start(s3c2410_dma_chan_t *chan)
328 pr_debug("s3c2410_start_dma: channel=%d\n", chan->number);
330 local_irq_save(flags);
332 if (chan->state == S3C2410_DMA_RUNNING) {
333 pr_debug("s3c2410_start_dma: already running (%d)\n", chan->state);
334 local_irq_restore(flags);
338 chan->state = S3C2410_DMA_RUNNING;
340 /* check wether there is anything to load, and if not, see
341 * if we can find anything to load
344 if (chan->load_state == S3C2410_DMALOAD_NONE) {
345 if (chan->next == NULL) {
346 printk(KERN_ERR "dma%d: channel has nothing loaded\n",
348 chan->state = S3C2410_DMA_IDLE;
349 local_irq_restore(flags);
353 s3c2410_dma_loadbuffer(chan, chan->next);
358 /* enable the channel */
360 if (!chan->irq_enabled) {
361 enable_irq(chan->irq);
362 chan->irq_enabled = 1;
365 /* start the channel going */
367 tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG);
368 tmp &= ~S3C2410_DMASKTRIG_STOP;
369 tmp |= S3C2410_DMASKTRIG_ON;
370 dma_wrreg(chan, S3C2410_DMA_DMASKTRIG, tmp);
372 pr_debug("wrote %08lx to DMASKTRIG\n", tmp);
375 /* the dma buffer loads should take care of clearing the AUTO
376 * reloading feature */
377 tmp = dma_rdreg(chan, S3C2410_DMA_DCON);
378 tmp &= ~S3C2410_DCON_NORELOAD;
379 dma_wrreg(chan, S3C2410_DMA_DCON, tmp);
382 s3c2410_dma_call_op(chan, S3C2410_DMAOP_START);
386 local_irq_restore(flags);
390 /* s3c2410_dma_canload
392 * work out if we can queue another buffer into the DMA engine
396 s3c2410_dma_canload(s3c2410_dma_chan_t *chan)
398 if (chan->load_state == S3C2410_DMALOAD_NONE ||
399 chan->load_state == S3C2410_DMALOAD_1RUNNING)
406 /* s3c2410_dma_enqueue
408 * queue an given buffer for dma transfer.
410 * id the device driver's id information for this buffer
411 * data the physical address of the buffer data
412 * size the size of the buffer in bytes
414 * If the channel is not running, then the flag S3C2410_DMAF_AUTOSTART
415 * is checked, and if set, the channel is started. If this flag isn't set,
416 * then an error will be returned.
418 * It is possible to queue more than one DMA buffer onto a channel at
419 * once, and the code will deal with the re-loading of the next buffer
423 int s3c2410_dma_enqueue(unsigned int channel, void *id,
424 dma_addr_t data, int size)
426 s3c2410_dma_chan_t *chan = &s3c2410_chans[channel];
427 s3c2410_dma_buf_t *buf;
430 check_channel(channel);
432 pr_debug("%s: id=%p, data=%08x, size=%d\n",
433 __FUNCTION__, id, (unsigned int)data, size);
435 buf = (s3c2410_dma_buf_t *)kmalloc(sizeof(*buf), GFP_ATOMIC);
437 pr_debug("%s: out of memory (%d alloc)\n",
438 __FUNCTION__, sizeof(*buf));
442 pr_debug("%s: new buffer %p\n", __FUNCTION__, buf);
444 //dbg_showchan(chan);
447 buf->data = buf->ptr = data;
450 buf->magic = BUF_MAGIC;
452 local_irq_save(flags);
454 if (chan->curr == NULL) {
455 /* we've got nothing loaded... */
456 pr_debug("%s: buffer %p queued onto empty channel\n",
463 pr_debug("dma%d: %s: buffer %p queued onto non-empty channel\n",
464 chan->number, __FUNCTION__, buf);
466 if (chan->end == NULL)
467 pr_debug("dma%d: %s: %p not empty, and chan->end==NULL?\n",
468 chan->number, __FUNCTION__, chan);
470 chan->end->next = buf;
474 /* if necessary, update the next buffer field */
475 if (chan->next == NULL)
478 /* check to see if we can load a buffer */
479 if (chan->state == S3C2410_DMA_RUNNING) {
480 if (chan->load_state == S3C2410_DMALOAD_1LOADED && 1) {
481 if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
482 printk(KERN_ERR "dma%d: loadbuffer:"
483 "timeout loading buffer\n",
486 local_irq_restore(flags);
491 while (s3c2410_dma_canload(chan) && chan->next != NULL) {
492 s3c2410_dma_loadbuffer(chan, chan->next);
494 } else if (chan->state == S3C2410_DMA_IDLE) {
495 if (chan->flags & S3C2410_DMAF_AUTOSTART) {
496 s3c2410_dma_ctrl(chan->number, S3C2410_DMAOP_START);
500 local_irq_restore(flags);
504 EXPORT_SYMBOL(s3c2410_dma_enqueue);
507 s3c2410_dma_freebuf(s3c2410_dma_buf_t *buf)
509 int magicok = (buf->magic == BUF_MAGIC);
516 printk("s3c2410_dma_freebuf: buff %p with bad magic\n", buf);
520 /* s3c2410_dma_lastxfer
522 * called when the system is out of buffers, to ensure that the channel
523 * is prepared for shutdown.
527 s3c2410_dma_lastxfer(s3c2410_dma_chan_t *chan)
529 pr_debug("dma%d: s3c2410_dma_lastxfer: load_state %d\n",
530 chan->number, chan->load_state);
532 switch (chan->load_state) {
533 case S3C2410_DMALOAD_NONE:
536 case S3C2410_DMALOAD_1LOADED:
537 if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
539 printk(KERN_ERR "dma%d: timeout waiting for load\n",
546 pr_debug("dma%d: lastxfer: unhandled load_state %d with no next",
547 chan->number, chan->load_state);
552 /* hopefully this'll shut the damned thing up after the transfer... */
553 dma_wrreg(chan, S3C2410_DMA_DCON, chan->dcon | S3C2410_DCON_NORELOAD);
557 #define dmadbg2(x...)
560 s3c2410_dma_irq(int irq, void *devpw, struct pt_regs *regs)
562 s3c2410_dma_chan_t *chan = (s3c2410_dma_chan_t *)devpw;
563 s3c2410_dma_buf_t *buf;
569 /* modify the channel state */
571 switch (chan->load_state) {
572 case S3C2410_DMALOAD_1RUNNING:
573 /* TODO - if we are running only one buffer, we probably
574 * want to reload here, and then worry about the buffer
577 chan->load_state = S3C2410_DMALOAD_NONE;
580 case S3C2410_DMALOAD_1LOADED:
581 /* iirc, we should go back to NONE loaded here, we
582 * had a buffer, and it was never verified as being
586 chan->load_state = S3C2410_DMALOAD_NONE;
589 case S3C2410_DMALOAD_1LOADED_1RUNNING:
590 /* we'll worry about checking to see if another buffer is
591 * ready after we've called back the owner. This should
592 * ensure we do not wait around too long for the DMA
593 * engine to start the next transfer
596 chan->load_state = S3C2410_DMALOAD_1LOADED;
599 case S3C2410_DMALOAD_NONE:
600 printk(KERN_ERR "dma%d: IRQ with no loaded buffer?\n",
605 printk(KERN_ERR "dma%d: IRQ in invalid load_state %d\n",
606 chan->number, chan->load_state);
611 /* update the chain to make sure that if we load any more
612 * buffers when we call the callback function, things should
615 chan->curr = buf->next;
618 if (buf->magic != BUF_MAGIC) {
619 printk(KERN_ERR "dma%d: %s: buf %p incorrect magic\n",
620 chan->number, __FUNCTION__, buf);
624 s3c2410_dma_buffdone(chan, buf, S3C2410_RES_OK);
627 s3c2410_dma_freebuf(buf);
631 if (chan->next != NULL) {
634 switch (chan->load_state) {
635 case S3C2410_DMALOAD_1RUNNING:
636 /* don't need to do anything for this state */
639 case S3C2410_DMALOAD_NONE:
640 /* can load buffer immediately */
643 case S3C2410_DMALOAD_1LOADED:
644 if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
646 printk(KERN_ERR "dma%d: timeout waiting for load\n",
653 case S3C2410_DMALOAD_1LOADED_1RUNNING:
657 printk(KERN_ERR "dma%d: unknown load_state in irq, %d\n",
658 chan->number, chan->load_state);
662 local_irq_save(flags);
663 s3c2410_dma_loadbuffer(chan, chan->next);
664 local_irq_restore(flags);
666 s3c2410_dma_lastxfer(chan);
668 /* see if we can stop this channel.. */
669 if (chan->load_state == S3C2410_DMALOAD_NONE) {
670 pr_debug("dma%d: end of transfer, stopping channel (%ld)\n",
671 chan->number, jiffies);
672 s3c2410_dma_ctrl(chan->number, S3C2410_DMAOP_STOP);
682 /* s3c2410_request_dma
684 * get control of an dma channel
687 int s3c2410_dma_request(unsigned int channel, s3c2410_dma_client_t *client,
690 s3c2410_dma_chan_t *chan = &s3c2410_chans[channel];
694 pr_debug("dma%d: s3c2410_request_dma: client=%s, dev=%p\n",
695 channel, client->name, dev);
697 check_channel(channel);
699 local_irq_save(flags);
704 if (client != chan->client) {
705 printk(KERN_ERR "dma%d: already in use\n", channel);
706 local_irq_restore(flags);
709 printk(KERN_ERR "dma%d: client already has channel\n", channel);
713 chan->client = client;
716 if (!chan->irq_claimed) {
717 pr_debug("dma%d: %s : requesting irq %d\n",
718 channel, __FUNCTION__, chan->irq);
720 err = request_irq(chan->irq, s3c2410_dma_irq, SA_INTERRUPT,
721 client->name, (void *)chan);
725 local_irq_restore(flags);
727 printk(KERN_ERR "%s: cannot get IRQ %d for DMA %d\n",
728 client->name, chan->irq, chan->number);
732 chan->irq_claimed = 1;
733 chan->irq_enabled = 1;
736 local_irq_restore(flags);
740 pr_debug("%s: channel initialised, %p\n", __FUNCTION__, chan);
745 EXPORT_SYMBOL(s3c2410_dma_request);
749 * release the given channel back to the system, will stop and flush
750 * any outstanding transfers, and ensure the channel is ready for the
753 * Note, although a warning is currently printed if the freeing client
754 * info is not the same as the registrant's client info, the free is still
755 * allowed to go through.
758 int s3c2410_dma_free(dmach_t channel, s3c2410_dma_client_t *client)
760 s3c2410_dma_chan_t *chan = &s3c2410_chans[channel];
763 check_channel(channel);
765 local_irq_save(flags);
768 if (chan->client != client) {
769 printk(KERN_WARNING "dma%d: possible free from different client (channel %p, passed %p)\n",
770 channel, chan->client, client);
773 /* sort out stopping and freeing the channel */
775 if (chan->state != S3C2410_DMA_IDLE) {
776 pr_debug("%s: need to stop dma channel %p\n",
779 /* possibly flush the channel */
780 s3c2410_dma_ctrl(channel, S3C2410_DMAOP_STOP);
786 local_irq_restore(flags);
791 EXPORT_SYMBOL(s3c2410_dma_free);
793 static int s3c2410_dma_dostop(s3c2410_dma_chan_t *chan)
798 pr_debug("%s:\n", __FUNCTION__);
802 local_irq_save(flags);
804 s3c2410_dma_call_op(chan, S3C2410_DMAOP_STOP);
806 tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG);
807 tmp |= S3C2410_DMASKTRIG_STOP;
808 dma_wrreg(chan, S3C2410_DMA_DMASKTRIG, tmp);
811 /* should also clear interrupts, according to WinCE BSP */
812 tmp = dma_rdreg(chan, S3C2410_DMA_DCON);
813 tmp |= S3C2410_DCON_NORELOAD;
814 dma_wrreg(chan, S3C2410_DMA_DCON, tmp);
817 chan->state = S3C2410_DMA_IDLE;
818 chan->load_state = S3C2410_DMALOAD_NONE;
820 local_irq_restore(flags);
827 * stop the channel, and remove all current and pending transfers
830 static int s3c2410_dma_flush(s3c2410_dma_chan_t *chan)
832 s3c2410_dma_buf_t *buf, *next;
835 pr_debug("%s:\n", __FUNCTION__);
837 local_irq_save(flags);
839 if (chan->state != S3C2410_DMA_IDLE) {
840 pr_debug("%s: stopping channel...\n", __FUNCTION__ );
841 s3c2410_dma_ctrl(chan->number, S3C2410_DMAOP_STOP);
848 chan->curr = chan->next = chan->end = NULL;
851 for ( ; buf != NULL; buf = next) {
854 pr_debug("%s: free buffer %p, next %p\n",
855 __FUNCTION__, buf, buf->next);
857 s3c2410_dma_buffdone(chan, buf, S3C2410_RES_ABORT);
858 s3c2410_dma_freebuf(buf);
862 local_irq_restore(flags);
869 s3c2410_dma_ctrl(dmach_t channel, s3c2410_chan_op_t op)
871 s3c2410_dma_chan_t *chan = &s3c2410_chans[channel];
873 check_channel(channel);
876 case S3C2410_DMAOP_START:
877 return s3c2410_dma_start(chan);
879 case S3C2410_DMAOP_STOP:
880 return s3c2410_dma_dostop(chan);
882 case S3C2410_DMAOP_PAUSE:
885 case S3C2410_DMAOP_RESUME:
888 case S3C2410_DMAOP_FLUSH:
889 return s3c2410_dma_flush(chan);
891 case S3C2410_DMAOP_TIMEOUT:
896 return -ENOENT; /* unknown, don't bother */
899 EXPORT_SYMBOL(s3c2410_dma_ctrl);
901 /* DMA configuration for each channel
903 * DISRCC -> source of the DMA (AHB,APB)
904 * DISRC -> source address of the DMA
905 * DIDSTC -> destination of the DMA (AHB,APD)
906 * DIDST -> destination address of the DMA
909 /* s3c2410_dma_config
911 * xfersize: size of unit in bytes (1,2,4)
912 * dcon: base value of the DCONx register
915 int s3c2410_dma_config(dmach_t channel,
919 s3c2410_dma_chan_t *chan = &s3c2410_chans[channel];
921 pr_debug("%s: chan=%d, xfer_unit=%d, dcon=%08x\n",
922 __FUNCTION__, channel, xferunit, dcon);
924 check_channel(channel);
928 dcon |= S3C2410_DCON_BYTE;
932 dcon |= S3C2410_DCON_HALFWORD;
936 dcon |= S3C2410_DCON_WORD;
940 pr_debug("%s: bad transfer size %d\n", __FUNCTION__, xferunit);
944 dcon |= S3C2410_DCON_HWTRIG;
945 dcon |= S3C2410_DCON_INTREQ;
947 pr_debug("%s: dcon now %08x\n", __FUNCTION__, dcon);
950 chan->xfer_unit = xferunit;
955 EXPORT_SYMBOL(s3c2410_dma_config);
957 int s3c2410_dma_setflags(dmach_t channel, unsigned int flags)
959 s3c2410_dma_chan_t *chan = &s3c2410_chans[channel];
961 check_channel(channel);
963 pr_debug("%s: chan=%p, flags=%08x\n", __FUNCTION__, chan, flags);
970 EXPORT_SYMBOL(s3c2410_dma_setflags);
973 /* do we need to protect the settings of the fields from
977 int s3c2410_dma_set_opfn(dmach_t channel, s3c2410_dma_opfn_t rtn)
979 s3c2410_dma_chan_t *chan = &s3c2410_chans[channel];
981 check_channel(channel);
983 pr_debug("%s: chan=%p, op rtn=%p\n", __FUNCTION__, chan, rtn);
990 EXPORT_SYMBOL(s3c2410_dma_set_opfn);
992 int s3c2410_dma_set_buffdone_fn(dmach_t channel, s3c2410_dma_cbfn_t rtn)
994 s3c2410_dma_chan_t *chan = &s3c2410_chans[channel];
996 check_channel(channel);
998 pr_debug("%s: chan=%p, callback rtn=%p\n", __FUNCTION__, chan, rtn);
1000 chan->callback_fn = rtn;
1005 EXPORT_SYMBOL(s3c2410_dma_set_buffdone_fn);
1007 /* s3c2410_dma_devconfig
1009 * configure the dma source/destination hardware type and address
1011 * source: S3C2410_DMASRC_HW: source is hardware
1012 * S3C2410_DMASRC_MEM: source is memory
1014 * hwcfg: the value for xxxSTCn register,
1015 * bit 0: 0=increment pointer, 1=leave pointer
1016 * bit 1: 0=soucre is AHB, 1=soucre is APB
1018 * devaddr: physical address of the source
1021 int s3c2410_dma_devconfig(int channel,
1022 s3c2410_dmasrc_t source,
1024 unsigned long devaddr)
1026 s3c2410_dma_chan_t *chan = &s3c2410_chans[channel];
1028 check_channel(channel);
1030 pr_debug("%s: source=%d, hwcfg=%08x, devaddr=%08lx\n",
1031 __FUNCTION__, (int)source, hwcfg, devaddr);
1033 chan->source = source;
1034 chan->dev_addr = devaddr;
1037 case S3C2410_DMASRC_HW:
1038 /* source is hardware */
1039 pr_debug("%s: hw source, devaddr=%08lx, hwcfg=%d\n",
1040 __FUNCTION__, devaddr, hwcfg);
1041 dma_wrreg(chan, S3C2410_DMA_DISRCC, hwcfg & 3);
1042 dma_wrreg(chan, S3C2410_DMA_DISRC, devaddr);
1043 dma_wrreg(chan, S3C2410_DMA_DIDSTC, (0<<1) | (0<<0));
1045 chan->addr_reg = dma_regaddr(chan, S3C2410_DMA_DIDST);
1048 case S3C2410_DMASRC_MEM:
1049 /* source is memory */
1050 pr_debug( "%s: mem source, devaddr=%08lx, hwcfg=%d\n",
1051 __FUNCTION__, devaddr, hwcfg);
1052 dma_wrreg(chan, S3C2410_DMA_DISRCC, (0<<1) | (0<<0));
1053 dma_wrreg(chan, S3C2410_DMA_DIDST, devaddr);
1054 dma_wrreg(chan, S3C2410_DMA_DIDSTC, hwcfg & 3);
1056 chan->addr_reg = dma_regaddr(chan, S3C2410_DMA_DISRC);
1060 printk(KERN_ERR "dma%d: invalid source type (%d)\n", channel, source);
1064 EXPORT_SYMBOL(s3c2410_dma_devconfig);
1066 /* system device class */
1070 static int s3c2410_dma_suspend(struct sys_device *dev, u32 state)
1072 s3c2410_dma_chan_t *cp = container_of(dev, s3c2410_dma_chan_t, dev);
1074 printk(KERN_DEBUG "suspending dma channel %d\n", cp->number);
1076 if (dma_rdreg(cp, S3C2410_DMA_DMASKTRIG) & S3C2410_DMASKTRIG_ON) {
1077 /* the dma channel is still working, which is probably
1078 * a bad thing to do over suspend/resume. We stop the
1079 * channel and assume that the client is either going to
1080 * retry after resume, or that it is broken.
1083 printk(KERN_INFO "dma: stopping channel %d due to suspend\n",
1086 s3c2410_dma_dostop(cp);
1092 static int s3c2410_dma_resume(struct sys_device *dev)
1098 #define s3c2410_dma_suspend NULL
1099 #define s3c2410_dma_resume NULL
1100 #endif /* CONFIG_PM */
1102 static struct sysdev_class dma_sysclass = {
1103 set_kset_name("s3c24xx-dma"),
1104 .suspend = s3c2410_dma_suspend,
1105 .resume = s3c2410_dma_resume,
1108 /* initialisation code */
1110 static int __init s3c2410_init_dma(void)
1112 s3c2410_dma_chan_t *cp;
1116 printk("S3C2410 DMA Driver, (c) 2003-2004 Simtec Electronics\n");
1118 dma_base = ioremap(S3C2410_PA_DMA, 0x200);
1119 if (dma_base == NULL) {
1120 printk(KERN_ERR "dma failed to remap register block\n");
1124 ret = sysdev_class_register(&dma_sysclass);
1126 printk(KERN_ERR "dma sysclass registration failed\n");
1130 for (channel = 0; channel < S3C2410_DMA_CHANNELS; channel++) {
1131 cp = &s3c2410_chans[channel];
1133 memset(cp, 0, sizeof(s3c2410_dma_chan_t));
1135 /* dma channel irqs are in order.. */
1136 cp->number = channel;
1137 cp->irq = channel + IRQ_DMA0;
1138 cp->regs = dma_base + (channel*0x40);
1140 /* point current stats somewhere */
1141 cp->stats = &cp->stats_store;
1142 cp->stats_store.timeout_shortest = LONG_MAX;
1144 /* basic channel configuration */
1146 cp->load_timeout = 1<<18;
1148 /* register system device */
1150 cp->dev.cls = &dma_sysclass;
1151 cp->dev.id = channel;
1152 ret = sysdev_register(&cp->dev);
1154 printk("DMA channel %d at %p, irq %d\n",
1155 cp->number, cp->regs, cp->irq);
1166 __initcall(s3c2410_init_dma);