1 /* linux/arch/arm/mach-s3c2410/mach-vr1000.c
3 * Copyright (c) 2003,2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * Machine support for Thorcom VR1000 board. Designed for Thorcom by
7 * Simtec Electronics, http://www.simtec.co.uk/
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 * 14-Sep-2004 BJD USB Power control
15 * 04-Sep-2004 BJD Added new uart init, and io init
16 * 21-Aug-2004 BJD Added struct s3c2410_board
17 * 06-Aug-2004 BJD Fixed call to time initialisation
18 * 05-Apr-2004 BJD Copied to make mach-vr1000.c
19 * 18-Oct-2004 BJD Updated board struct
20 * 04-Nov-2004 BJD Clock and serial configuration update
23 #include <linux/kernel.h>
24 #include <linux/types.h>
25 #include <linux/interrupt.h>
26 #include <linux/list.h>
27 #include <linux/timer.h>
28 #include <linux/init.h>
30 #include <asm/mach/arch.h>
31 #include <asm/mach/map.h>
32 #include <asm/mach/irq.h>
34 #include <asm/arch/bast-map.h>
35 #include <asm/arch/vr1000-map.h>
37 #include <asm/hardware.h>
40 #include <asm/mach-types.h>
42 //#include <asm/debug-ll.h>
43 #include <asm/arch/regs-serial.h>
49 #include "usb-simtec.h"
51 /* macros for virtual address mods for the io space entries */
52 #define VA_C5(item) ((item) + BAST_VAM_CS5)
53 #define VA_C4(item) ((item) + BAST_VAM_CS4)
54 #define VA_C3(item) ((item) + BAST_VAM_CS3)
55 #define VA_C2(item) ((item) + BAST_VAM_CS2)
57 /* macros to modify the physical addresses for io space */
59 #define PA_CS2(item) ((item) + S3C2410_CS2)
60 #define PA_CS3(item) ((item) + S3C2410_CS3)
61 #define PA_CS4(item) ((item) + S3C2410_CS4)
62 #define PA_CS5(item) ((item) + S3C2410_CS5)
64 static struct map_desc vr1000_iodesc[] __initdata = {
67 { S3C2410_VA_ISA_BYTE, PA_CS2(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
68 { S3C2410_VA_ISA_WORD, PA_CS3(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
70 /* we could possibly compress the next set down into a set of smaller tables
71 * pagetables, but that would mean using an L2 section, and it still means
72 * we cannot actually feed the same register to an LDR due to 16K spacing
75 /* bast CPLD control registers, and external interrupt controls */
76 { VR1000_VA_CTRL1, VR1000_PA_CTRL1, SZ_1M, MT_DEVICE },
77 { VR1000_VA_CTRL2, VR1000_PA_CTRL2, SZ_1M, MT_DEVICE },
78 { VR1000_VA_CTRL3, VR1000_PA_CTRL3, SZ_1M, MT_DEVICE },
79 { VR1000_VA_CTRL4, VR1000_PA_CTRL4, SZ_1M, MT_DEVICE },
81 /* peripheral space... one for each of fast/slow/byte/16bit */
82 /* note, ide is only decoded in word space, even though some registers
86 { VA_C2(VR1000_VA_DM9000), PA_CS2(VR1000_PA_DM9000), SZ_1M, MT_DEVICE },
87 { VA_C2(VR1000_VA_IDEPRI), PA_CS3(VR1000_PA_IDEPRI), SZ_1M, MT_DEVICE },
88 { VA_C2(VR1000_VA_IDESEC), PA_CS3(VR1000_PA_IDESEC), SZ_1M, MT_DEVICE },
89 { VA_C2(VR1000_VA_IDEPRIAUX), PA_CS3(VR1000_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
90 { VA_C2(VR1000_VA_IDESECAUX), PA_CS3(VR1000_PA_IDESECAUX), SZ_1M, MT_DEVICE },
93 { VA_C3(VR1000_VA_DM9000), PA_CS3(VR1000_PA_DM9000), SZ_1M, MT_DEVICE },
94 { VA_C3(VR1000_VA_IDEPRI), PA_CS3(VR1000_PA_IDEPRI), SZ_1M, MT_DEVICE },
95 { VA_C3(VR1000_VA_IDESEC), PA_CS3(VR1000_PA_IDESEC), SZ_1M, MT_DEVICE },
96 { VA_C3(VR1000_VA_IDEPRIAUX), PA_CS3(VR1000_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
97 { VA_C3(VR1000_VA_IDESECAUX), PA_CS3(VR1000_PA_IDESECAUX), SZ_1M, MT_DEVICE },
100 { VA_C4(VR1000_VA_DM9000), PA_CS4(VR1000_PA_DM9000), SZ_1M, MT_DEVICE },
101 { VA_C4(VR1000_VA_IDEPRI), PA_CS5(VR1000_PA_IDEPRI), SZ_1M, MT_DEVICE },
102 { VA_C4(VR1000_VA_IDESEC), PA_CS5(VR1000_PA_IDESEC), SZ_1M, MT_DEVICE },
103 { VA_C4(VR1000_VA_IDEPRIAUX), PA_CS5(VR1000_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
104 { VA_C4(VR1000_VA_IDESECAUX), PA_CS5(VR1000_PA_IDESECAUX), SZ_1M, MT_DEVICE },
107 { VA_C5(VR1000_VA_DM9000), PA_CS5(VR1000_PA_DM9000), SZ_1M, MT_DEVICE },
108 { VA_C5(VR1000_VA_IDEPRI), PA_CS5(VR1000_PA_IDEPRI), SZ_1M, MT_DEVICE },
109 { VA_C5(VR1000_VA_IDESEC), PA_CS5(VR1000_PA_IDESEC), SZ_1M, MT_DEVICE },
110 { VA_C5(VR1000_VA_IDEPRIAUX), PA_CS5(VR1000_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
111 { VA_C5(VR1000_VA_IDESECAUX), PA_CS5(VR1000_PA_IDESECAUX), SZ_1M, MT_DEVICE },
114 #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
115 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
116 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
118 /* uart clock source(s) */
120 static struct s3c24xx_uart_clksrc vr1000_serial_clocks[] = {
135 static struct s3c2410_uartcfg vr1000_uartcfgs[] = {
142 .clocks = vr1000_serial_clocks,
143 .clocks_size = ARRAY_SIZE(vr1000_serial_clocks),
151 .clocks = vr1000_serial_clocks,
152 .clocks_size = ARRAY_SIZE(vr1000_serial_clocks),
154 /* port 2 is not actually used */
161 .clocks = vr1000_serial_clocks,
162 .clocks_size = ARRAY_SIZE(vr1000_serial_clocks),
167 static struct platform_device *vr1000_devices[] __initdata = {
175 static struct clk *vr1000_clocks[] = {
183 static struct s3c24xx_board vr1000_board __initdata = {
184 .devices = vr1000_devices,
185 .devices_count = ARRAY_SIZE(vr1000_devices),
186 .clocks = vr1000_clocks,
187 .clocks_count = ARRAY_SIZE(vr1000_clocks),
191 void __init vr1000_map_io(void)
193 /* initialise clock sources */
195 s3c24xx_dclk0.parent = NULL;
196 s3c24xx_dclk0.rate = 12*1000*1000;
198 s3c24xx_dclk1.parent = NULL;
199 s3c24xx_dclk1.rate = 3692307;
201 s3c24xx_clkout0.parent = &s3c24xx_dclk0;
202 s3c24xx_clkout1.parent = &s3c24xx_dclk1;
204 s3c24xx_uclk.parent = &s3c24xx_clkout1;
206 s3c24xx_init_io(vr1000_iodesc, ARRAY_SIZE(vr1000_iodesc));
207 s3c2410_init_uarts(vr1000_uartcfgs, ARRAY_SIZE(vr1000_uartcfgs));
208 s3c24xx_set_board(&vr1000_board);
212 void __init vr1000_init_irq(void)
217 MACHINE_START(VR1000, "Thorcom-VR1000")
218 MAINTAINER("Ben Dooks <ben@simtec.co.uk>")
219 BOOT_MEM(S3C2410_SDRAM_PA, S3C2410_PA_UART, S3C2410_VA_UART)
220 BOOT_PARAMS(S3C2410_SDRAM_PA + 0x100)
222 INITIRQ(vr1000_init_irq)
223 .timer = &s3c2410_timer,