2 * (C) 2001-2004 Dave Jones. <davej@codemonkey.org.uk>
3 * (C) 2002 Padraig Brady. <padraig@antefacto.com>
5 * Licensed under the terms of the GNU GPL License version 2.
6 * Based upon datasheets & sample CPUs kindly provided by VIA.
8 * VIA have currently 2 different versions of Longhaul.
9 * Version 1 (Longhaul) uses the BCR2 MSR at 0x1147.
10 * It is present only in Samuel 1, Samuel 2 and Ezra.
11 * Version 2 (Powersaver) uses the POWERSAVER MSR at 0x110a.
12 * It is present in Ezra-T, Nehemiah and above.
13 * In addition to scaling multiplier, it can also scale voltage.
14 * There is provision for scaling FSB too, but this doesn't work
15 * too well in practice.
17 * BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous*
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/init.h>
23 #include <linux/cpufreq.h>
24 #include <linux/slab.h>
25 #include <linux/string.h>
28 #include <asm/timex.h>
36 #define dprintk(msg...) printk(msg)
38 #define dprintk(msg...) do { } while(0)
41 #define PFX "longhaul: "
43 static unsigned int numscales=16, numvscales;
44 static int minvid, maxvid;
45 static int can_scale_voltage;
49 /* Module parameters */
50 static int dont_scale_voltage;
51 static unsigned int fsb;
53 #define __hlt() __asm__ __volatile__("hlt": : :"memory")
55 /* Clock ratios multiplied by 10 */
56 static int clock_ratio[32];
57 static int eblcr_table[32];
58 static int voltage_table[32];
59 static unsigned int highest_speed, lowest_speed; /* kHz */
60 static int longhaul_version;
61 static struct cpufreq_frequency_table *longhaul_table;
64 static unsigned int calc_speed (int mult, int fsb)
75 static int longhaul_get_cpu_mult (void)
77 unsigned long invalue=0,lo, hi;
79 rdmsr (MSR_IA32_EBL_CR_POWERON, lo, hi);
80 invalue = (lo & (1<<22|1<<23|1<<24|1<<25)) >>22;
81 if (longhaul_version==2) {
85 if (longhaul_version==4) {
89 return eblcr_table[invalue];
94 * longhaul_set_cpu_frequency()
95 * @clock_ratio_index : bitpattern of the new multiplier.
97 * Sets a new clock ratio, and -if applicable- a new Front Side Bus
100 static void longhaul_setstate (unsigned int clock_ratio_index)
103 struct cpufreq_freqs freqs;
104 union msr_longhaul longhaul;
107 mult = clock_ratio[clock_ratio_index];
111 speed = calc_speed (mult, fsb);
112 if ((speed > highest_speed) || (speed < lowest_speed))
115 freqs.old = calc_speed (longhaul_get_cpu_mult(), fsb);
117 freqs.cpu = 0; /* longhaul.c is UP only driver */
119 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
121 dprintk (KERN_INFO PFX "FSB:%d Mult:%d.%dx\n", fsb,
124 switch (longhaul_version) {
126 rdmsrl (MSR_VIA_BCR2, bcr2.val);
127 /* Enable software clock multiplier */
128 bcr2.bits.ESOFTBF = 1;
129 bcr2.bits.CLOCKMUL = clock_ratio_index;
130 wrmsrl (MSR_VIA_BCR2, bcr2.val);
134 /* Disable software clock multiplier */
135 rdmsrl (MSR_VIA_BCR2, bcr2.val);
136 bcr2.bits.ESOFTBF = 0;
137 wrmsrl (MSR_VIA_BCR2, bcr2.val);
141 * Powersaver. (Ezra-T [C5M], Nehemiah [C5N])
142 * We can scale voltage with this too, but that's currently
143 * disabled until we come up with a decent 'match freq to voltage'
145 * We also need to do the voltage/freq setting in order depending
146 * on the direction of scaling (like we do in powernow-k7.c)
147 * Ezra-T was alleged to do FSB scaling too, but it never worked in practice.
150 rdmsrl (MSR_VIA_LONGHAUL, longhaul.val);
151 longhaul.bits.SoftBusRatio = clock_ratio_index & 0xf;
152 longhaul.bits.SoftBusRatio4 = (clock_ratio_index & 0x10) >> 4;
153 longhaul.bits.EnableSoftBusRatio = 1;
154 /* We must program the revision key only with values we
155 * know about, not blindly copy it from 0:3 */
156 longhaul.bits.RevisionKey = 3; /* SoftVID & SoftBSEL */
157 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
160 rdmsrl (MSR_VIA_LONGHAUL, longhaul.val);
161 longhaul.bits.EnableSoftBusRatio = 0;
162 longhaul.bits.RevisionKey = 3;
163 wrmsrl (MSR_VIA_LONGHAUL, longhaul.val);
166 rdmsrl (MSR_VIA_LONGHAUL, longhaul.val);
167 longhaul.bits.SoftBusRatio = clock_ratio_index & 0xf;
168 longhaul.bits.SoftBusRatio4 = (clock_ratio_index & 0x10) >> 4;
169 longhaul.bits.EnableSoftBusRatio = 1;
171 longhaul.bits.RevisionKey = 0x0;
173 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
176 rdmsrl (MSR_VIA_LONGHAUL, longhaul.val);
177 longhaul.bits.EnableSoftBusRatio = 0;
178 longhaul.bits.RevisionKey = 0xf;
179 wrmsrl (MSR_VIA_LONGHAUL, longhaul.val);
183 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
187 * Centaur decided to make life a little more tricky.
188 * Only longhaul v1 is allowed to read EBLCR BSEL[0:1].
189 * Samuel2 and above have to try and guess what the FSB is.
190 * We do this by assuming we booted at maximum multiplier, and interpolate
191 * between that value multiplied by possible FSBs and cpu_mhz which
192 * was calculated at boot time. Really ugly, but no other way to do this.
197 static int _guess (int guess, int maxmult)
201 target = ((maxmult/10)*guess);
204 target += ROUNDING/2;
210 static int guess_fsb(int maxmult)
212 int speed = (cpu_khz/1000);
214 int speeds[3] = { 66, 100, 133 };
219 for (i=0; i<3; i++) {
220 if (_guess(speeds[i],maxmult) == speed)
227 static int __init longhaul_get_ranges (void)
229 struct cpuinfo_x86 *c = cpu_data;
230 unsigned long invalue,invalue2;
231 unsigned int minmult=0, maxmult=0;
232 unsigned int multipliers[32]= {
233 50,30,40,100,55,35,45,95,90,70,80,60,120,75,85,65,
234 -1,110,120,-1,135,115,125,105,130,150,160,140,-1,155,-1,145 };
235 unsigned int j, k = 0;
236 union msr_longhaul longhaul;
237 unsigned long lo, hi;
238 unsigned int eblcr_fsb_table[] = { 66, 133, 100, -1 };
240 switch (longhaul_version) {
242 /* Ugh, Longhaul v1 didn't have the min/max MSRs.
243 Assume min=3.0x & max = whatever we booted at. */
245 maxmult = longhaul_get_cpu_mult();
246 rdmsr (MSR_IA32_EBL_CR_POWERON, lo, hi);
247 invalue = (lo & (1<<18|1<<19)) >>18;
249 fsb = eblcr_fsb_table[invalue];
251 fsb = guess_fsb(maxmult);
255 rdmsrl (MSR_VIA_LONGHAUL, longhaul.val);
257 invalue = longhaul.bits.MaxMHzBR;
258 if (longhaul.bits.MaxMHzBR4)
260 maxmult=multipliers[invalue];
262 invalue = longhaul.bits.MinMHzBR;
263 if (longhaul.bits.MinMHzBR4 == 1)
266 minmult = multipliers[invalue];
268 switch (longhaul.bits.MaxMHzFSB) {
273 case 0x2: printk (KERN_INFO PFX "Invalid (reserved) FSB!\n");
281 rdmsrl (MSR_VIA_LONGHAUL, longhaul.val);
283 //TODO: Nehemiah may have borken MaxMHzBR.
284 // need to extrapolate from FSB.
286 invalue2 = longhaul.bits.MinMHzBR;
287 invalue = longhaul.bits.MaxMHzBR;
288 if (longhaul.bits.MaxMHzBR4)
290 maxmult=multipliers[invalue];
292 maxmult=longhaul_get_cpu_mult();
294 printk(KERN_INFO PFX " invalue: %ld maxmult: %d \n", invalue, maxmult);
295 printk(KERN_INFO PFX " invalue2: %ld \n", invalue2);
299 switch (longhaul.bits.MaxMHzFSB) {
304 case 0x2: printk (KERN_INFO PFX "Invalid (reserved) FSB!\n");
313 dprintk (KERN_INFO PFX "MinMult=%d.%dx MaxMult=%d.%dx\n",
314 minmult/10, minmult%10, maxmult/10, maxmult%10);
315 highest_speed = calc_speed (maxmult, fsb);
316 lowest_speed = calc_speed (minmult,fsb);
317 dprintk (KERN_INFO PFX "FSB: %dMHz Lowestspeed=%dMHz Highestspeed=%dMHz\n",
318 fsb, lowest_speed/1000, highest_speed/1000);
320 if (lowest_speed == highest_speed) {
321 printk (KERN_INFO PFX "highestspeed == lowest, aborting.\n");
324 if (lowest_speed > highest_speed) {
325 printk (KERN_INFO PFX "nonsense! lowest (%d > %d) !\n",
326 lowest_speed, highest_speed);
330 longhaul_table = kmalloc((numscales + 1) * sizeof(struct cpufreq_frequency_table), GFP_KERNEL);
334 for (j=0; j < numscales; j++) {
336 ratio = clock_ratio[j];
339 if (ratio > maxmult || ratio < minmult)
341 longhaul_table[k].frequency = calc_speed (ratio, fsb);
342 longhaul_table[k].index = j;
346 longhaul_table[k].frequency = CPUFREQ_TABLE_END;
348 kfree (longhaul_table);
356 static void __init longhaul_setup_voltagescaling(void)
358 union msr_longhaul longhaul;
360 rdmsrl (MSR_VIA_LONGHAUL, longhaul.val);
362 if (!(longhaul.bits.RevisionID & 1))
365 minvid = longhaul.bits.MinimumVID;
366 maxvid = longhaul.bits.MaximumVID;
367 vrmrev = longhaul.bits.VRMRev;
369 if (minvid == 0 || maxvid == 0) {
370 printk (KERN_INFO PFX "Bogus values Min:%d.%03d Max:%d.%03d. "
371 "Voltage scaling disabled.\n",
372 minvid/1000, minvid%1000, maxvid/1000, maxvid%1000);
376 if (minvid == maxvid) {
377 printk (KERN_INFO PFX "Claims to support voltage scaling but min & max are "
378 "both %d.%03d. Voltage scaling disabled\n",
379 maxvid/1000, maxvid%1000);
384 dprintk (KERN_INFO PFX "VRM 8.5 : ");
385 memcpy (voltage_table, vrm85scales, sizeof(voltage_table));
386 numvscales = (voltage_table[maxvid]-voltage_table[minvid])/25;
388 dprintk (KERN_INFO PFX "Mobile VRM : ");
389 memcpy (voltage_table, mobilevrmscales, sizeof(voltage_table));
390 numvscales = (voltage_table[maxvid]-voltage_table[minvid])/5;
393 /* Current voltage isn't readable at first, so we need to
394 set it to a known value. The spec says to use maxvid */
395 longhaul.bits.RevisionKey = longhaul.bits.RevisionID; /* FIXME: This is bad. */
396 longhaul.bits.EnableSoftVID = 1;
397 longhaul.bits.SoftVID = maxvid;
398 wrmsrl (MSR_VIA_LONGHAUL, longhaul.val);
400 minvid = voltage_table[minvid];
401 maxvid = voltage_table[maxvid];
403 dprintk ("Min VID=%d.%03d Max VID=%d.%03d, %d possible voltage scales\n",
404 maxvid/1000, maxvid%1000, minvid/1000, minvid%1000, numvscales);
406 can_scale_voltage = 1;
410 static int longhaul_verify(struct cpufreq_policy *policy)
412 return cpufreq_frequency_table_verify(policy, longhaul_table);
416 static int longhaul_target (struct cpufreq_policy *policy,
417 unsigned int target_freq,
418 unsigned int relation)
420 unsigned int table_index = 0;
421 unsigned int new_clock_ratio = 0;
423 if (cpufreq_frequency_table_target(policy, longhaul_table, target_freq, relation, &table_index))
426 new_clock_ratio = longhaul_table[table_index].index & 0xFF;
428 longhaul_setstate(new_clock_ratio);
433 static unsigned int longhaul_get(unsigned int cpu)
437 return (calc_speed (longhaul_get_cpu_mult(), fsb));
440 static int __init longhaul_cpu_init (struct cpufreq_policy *policy)
442 struct cpuinfo_x86 *c = cpu_data;
446 switch (c->x86_model) {
448 cpuname = "C3 'Samuel' [C5A]";
450 memcpy (clock_ratio, samuel1_clock_ratio, sizeof(samuel1_clock_ratio));
451 memcpy (eblcr_table, samuel1_eblcr, sizeof(samuel1_eblcr));
454 case 7: /* C5B / C5C */
456 switch (c->x86_mask) {
458 cpuname = "C3 'Samuel 2' [C5B]";
459 /* Note, this is not a typo, early Samuel2's had Samuel1 ratios. */
460 memcpy (clock_ratio, samuel1_clock_ratio, sizeof(samuel1_clock_ratio));
461 memcpy (eblcr_table, samuel2_eblcr, sizeof(samuel2_eblcr));
465 cpuname = "C3 'Samuel 2' [C5B]";
467 cpuname = "C3 'Ezra' [C5C]";
468 memcpy (clock_ratio, ezra_clock_ratio, sizeof(ezra_clock_ratio));
469 memcpy (eblcr_table, ezra_eblcr, sizeof(ezra_eblcr));
475 cpuname = "C3 'Ezra-T' [C5M]";
478 memcpy (clock_ratio, ezrat_clock_ratio, sizeof(ezrat_clock_ratio));
479 memcpy (eblcr_table, ezrat_eblcr, sizeof(ezrat_eblcr));
485 switch (c->x86_mask) {
487 cpuname = "C3 'Nehemiah A' [C5N]";
488 memcpy (clock_ratio, nehemiah_a_clock_ratio, sizeof(nehemiah_a_clock_ratio));
489 memcpy (eblcr_table, nehemiah_a_eblcr, sizeof(nehemiah_a_eblcr));
492 cpuname = "C3 'Nehemiah B' [C5N]";
493 memcpy (clock_ratio, nehemiah_b_clock_ratio, sizeof(nehemiah_b_clock_ratio));
494 memcpy (eblcr_table, nehemiah_b_eblcr, sizeof(nehemiah_b_eblcr));
497 cpuname = "C3 'Nehemiah C' [C5N]";
498 memcpy (clock_ratio, nehemiah_c_clock_ratio, sizeof(nehemiah_c_clock_ratio));
499 memcpy (eblcr_table, nehemiah_c_eblcr, sizeof(nehemiah_c_eblcr));
510 printk (KERN_INFO PFX "VIA %s CPU detected. Longhaul v%d supported.\n",
511 cpuname, longhaul_version);
513 ret = longhaul_get_ranges();
517 if ((longhaul_version==2) && (dont_scale_voltage==0))
518 longhaul_setup_voltagescaling();
520 policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
521 policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
522 policy->cur = calc_speed (longhaul_get_cpu_mult(), fsb);
524 ret = cpufreq_frequency_table_cpuinfo(policy, longhaul_table);
528 cpufreq_frequency_table_get_attr(longhaul_table, policy->cpu);
533 static int __exit longhaul_cpu_exit(struct cpufreq_policy *policy)
535 cpufreq_frequency_table_put_attr(policy->cpu);
539 static struct freq_attr* longhaul_attr[] = {
540 &cpufreq_freq_attr_scaling_available_freqs,
544 static struct cpufreq_driver longhaul_driver = {
545 .verify = longhaul_verify,
546 .target = longhaul_target,
548 .init = longhaul_cpu_init,
549 .exit = longhaul_cpu_exit,
551 .owner = THIS_MODULE,
552 .attr = longhaul_attr,
555 static int __init longhaul_init (void)
557 struct cpuinfo_x86 *c = cpu_data;
559 if (c->x86_vendor != X86_VENDOR_CENTAUR || c->x86 != 6)
562 switch (c->x86_model) {
564 return cpufreq_register_driver(&longhaul_driver);
566 printk (KERN_INFO PFX "Nehemiah unsupported: Waiting on working silicon "
567 "from VIA before this is usable.\n");
570 printk (KERN_INFO PFX "Unknown VIA CPU. Contact davej@codemonkey.org.uk\n");
576 static void __exit longhaul_exit (void)
578 cpufreq_unregister_driver(&longhaul_driver);
579 kfree(longhaul_table);
582 MODULE_PARM (dont_scale_voltage, "i");
584 MODULE_AUTHOR ("Dave Jones <davej@codemonkey.org.uk>");
585 MODULE_DESCRIPTION ("Longhaul driver for VIA Cyrix processors.");
586 MODULE_LICENSE ("GPL");
588 module_init(longhaul_init);
589 module_exit(longhaul_exit);