2 * (c) 2003, 2004 Advanced Micro Devices, Inc.
3 * Your use of this code is subject to the terms and conditions of the
4 * GNU general public license version 2. See "COPYING" or
5 * http://www.gnu.org/licenses/gpl.html
8 struct powernow_k8_data {
11 u32 numps; /* number of p-states */
12 u32 batps; /* number of p-states supported on battery */
14 /* these values are constant when the PSB is used to determine
15 * vid/fid pairings, but are modified during the ->target() call
16 * when ACPI is used */
17 u32 rvo; /* ramp voltage offset */
18 u32 irt; /* isochronous relief time */
19 u32 vidmvs; /* usable value calculated from mvs */
20 u32 vstable; /* voltage stabilization time, units 20 us */
21 u32 plllock; /* pll lock time, units 1 us */
23 /* keep track of the current fid / vid */
27 /* the powernow_table includes all frequency and vid/fid pairings:
28 * fid are the lower 8 bits of the index, vid are the upper 8 bits.
29 * frequency is in kHz */
30 struct cpufreq_frequency_table *powernow_table;
32 #ifdef CONFIG_ACPI_PROCESSOR
33 /* the acpi table needs to be kept. it's only available if ACPI was
34 * used to determine valid frequency/vid/fid states */
35 struct acpi_processor_performance acpi_data;
40 /* processor's cpuid instruction support */
41 #define CPUID_PROCESSOR_SIGNATURE 1 /* function 1 */
42 #define CPUID_XFAM_MOD 0x0ff00ff0 /* extended fam, fam + model */
43 #define ATHLON64_XFAM_MOD 0x00000f40 /* extended fam, fam + model */
44 #define OPTERON_XFAM_MOD 0x00000f50 /* extended fam, fam + model */
45 #define CPUID_GET_MAX_CAPABILITIES 0x80000000
46 #define CPUID_FREQ_VOLT_CAPABILITIES 0x80000007
47 #define P_STATE_TRANSITION_CAPABLE 6
49 /* Model Specific Registers for p-state transitions. MSRs are 64-bit. For */
50 /* writes (wrmsr - opcode 0f 30), the register number is placed in ecx, and */
51 /* the value to write is placed in edx:eax. For reads (rdmsr - opcode 0f 32), */
52 /* the register number is placed in ecx, and the data is returned in edx:eax. */
54 #define MSR_FIDVID_CTL 0xc0010041
55 #define MSR_FIDVID_STATUS 0xc0010042
57 /* Field definitions within the FID VID Low Control MSR : */
58 #define MSR_C_LO_INIT_FID_VID 0x00010000
59 #define MSR_C_LO_NEW_VID 0x00001f00
60 #define MSR_C_LO_NEW_FID 0x0000002f
61 #define MSR_C_LO_VID_SHIFT 8
63 /* Field definitions within the FID VID High Control MSR : */
64 #define MSR_C_HI_STP_GNT_TO 0x000fffff
66 /* Field definitions within the FID VID Low Status MSR : */
67 #define MSR_S_LO_CHANGE_PENDING 0x80000000 /* cleared when completed */
68 #define MSR_S_LO_MAX_RAMP_VID 0x1f000000
69 #define MSR_S_LO_MAX_FID 0x003f0000
70 #define MSR_S_LO_START_FID 0x00003f00
71 #define MSR_S_LO_CURRENT_FID 0x0000003f
73 /* Field definitions within the FID VID High Status MSR : */
74 #define MSR_S_HI_MAX_WORKING_VID 0x001f0000
75 #define MSR_S_HI_START_VID 0x00001f00
76 #define MSR_S_HI_CURRENT_VID 0x0000001f
77 #define MSR_C_HI_STP_GNT_BENIGN 0x00000001
80 * There are restrictions frequencies have to follow:
81 * - only 1 entry in the low fid table ( <=1.4GHz )
82 * - lowest entry in the high fid table must be >= 2 * the entry in the
84 * - lowest entry in the high fid table must be a <= 200MHz + 2 * the entry
85 * in the low fid table
86 * - the parts can only step at 200 MHz intervals, so 1.9 GHz is never valid
87 * - lowest frequency must be >= interprocessor hypertransport link speed
88 * (only applies to MP systems obviously)
91 /* fids (frequency identifiers) are arranged in 2 tables - lo and hi */
92 #define LO_FID_TABLE_TOP 6 /* fid values marking the boundary */
93 #define HI_FID_TABLE_BOTTOM 8 /* between the low and high tables */
95 #define LO_VCOFREQ_TABLE_TOP 1400 /* corresponding vco frequency values */
96 #define HI_VCOFREQ_TABLE_BOTTOM 1600
98 #define MIN_FREQ_RESOLUTION 200 /* fids jump by 2 matching freq jumps by 200 */
100 #define MAX_FID 0x2a /* Spec only gives FID values as far as 5 GHz */
101 #define LEAST_VID 0x1e /* Lowest (numerically highest) useful vid value */
103 #define MIN_FREQ 800 /* Min and max freqs, per spec */
104 #define MAX_FREQ 5000
106 #define INVALID_FID_MASK 0xffffffc1 /* not a valid fid if these bits are set */
107 #define INVALID_VID_MASK 0xffffffe0 /* not a valid vid if these bits are set */
109 #define STOP_GRANT_5NS 1 /* min poss memory access latency for voltage change */
111 #define PLL_LOCK_CONVERSION (1000/5) /* ms to ns, then divide by clock period */
113 #define MAXIMUM_VID_STEPS 1 /* Current cpus only allow a single step of 25mV */
114 #define VST_UNITS_20US 20 /* Voltage Stabalization Time is in units of 20us */
117 * Most values of interest are enocoded in a single field of the _PSS
118 * entries: the "control" value.
123 #define PLL_L_SHIFT 20
129 #define PLL_L_MASK 0x7f
131 #define VST_MASK 0x7f
132 #define VID_MASK 0x1f
133 #define FID_MASK 0x3f
137 * Version 1.4 of the PSB table. This table is constructed by BIOS and is
138 * to tell the OS's power management driver which VIDs and FIDs are
139 * supported by this particular processor.
140 * If the data in the PSB / PST is wrong, then this driver will program the
141 * wrong values into hardware, which is very likely to lead to a crash.
144 #define PSB_ID_STRING "AMDK7PNOW!"
145 #define PSB_ID_STRING_LEN 10
147 #define PSB_VERSION_1_4 0x14
153 u16 voltagestabilizationtime;
163 /* Pairs of fid/vid values are appended to the version 1.4 PSB table. */
170 #define dprintk(msg...) printk(msg)
172 #define dprintk(msg...) do { } while(0)
175 static int core_voltage_pre_transition(struct powernow_k8_data *data, u32 reqvid);
176 static int core_voltage_post_transition(struct powernow_k8_data *data, u32 reqvid);
177 static int core_frequency_transition(struct powernow_k8_data *data, u32 reqfid);
179 static void powernow_k8_acpi_pst_values(struct powernow_k8_data *data, unsigned int index);