2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/irq.h>
25 #include <linux/interrupt.h>
26 #include <linux/init.h>
27 #include <linux/delay.h>
28 #include <linux/sched.h>
29 #include <linux/config.h>
30 #include <linux/smp_lock.h>
31 #include <linux/mc146818rtc.h>
32 #include <linux/compiler.h>
33 #include <linux/acpi.h>
38 #include <asm/timer.h>
40 #include <mach_apic.h>
44 static spinlock_t ioapic_lock = SPIN_LOCK_UNLOCKED;
47 * Is the SiS APIC rmw bug present ?
48 * -1 = don't know, 0 = no, 1 = yes
50 int sis_apic_bug = -1;
53 * # of IRQ routing registers
55 int nr_ioapic_registers[MAX_IO_APICS];
58 * Rough estimation of how many shared IRQs there are, can
61 #define MAX_PLUS_SHARED_IRQS NR_IRQS
62 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
65 * This is performance-critical, we want to do it O(1)
67 * the indexing order of this array favors 1:1 mappings
68 * between pins and IRQs.
71 static struct irq_pin_list {
73 } irq_2_pin[PIN_MAP_SIZE];
75 int vector_irq[NR_VECTORS] = { [0 ... NR_VECTORS - 1] = -1};
76 #ifdef CONFIG_PCI_USE_VECTOR
77 #define vector_to_irq(vector) \
78 (platform_legacy_irq(vector) ? vector : vector_irq[vector])
80 #define vector_to_irq(vector) (vector)
84 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
85 * shared ISA-space IRQs, so we have to support them. We are super
86 * fast in the common case, and fast for shared ISA-space IRQs.
88 static void __init add_pin_to_irq(unsigned int irq, int apic, int pin)
90 static int first_free_entry = NR_IRQS;
91 struct irq_pin_list *entry = irq_2_pin + irq;
94 entry = irq_2_pin + entry->next;
96 if (entry->pin != -1) {
97 entry->next = first_free_entry;
98 entry = irq_2_pin + entry->next;
99 if (++first_free_entry >= PIN_MAP_SIZE)
100 panic("io_apic.c: whoops");
107 * Reroute an IRQ to a different pin.
109 static void __init replace_pin_at_irq(unsigned int irq,
110 int oldapic, int oldpin,
111 int newapic, int newpin)
113 struct irq_pin_list *entry = irq_2_pin + irq;
116 if (entry->apic == oldapic && entry->pin == oldpin) {
117 entry->apic = newapic;
122 entry = irq_2_pin + entry->next;
126 static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
128 struct irq_pin_list *entry = irq_2_pin + irq;
129 unsigned int pin, reg;
135 reg = io_apic_read(entry->apic, 0x10 + pin*2);
138 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
141 entry = irq_2_pin + entry->next;
146 static void __mask_IO_APIC_irq (unsigned int irq)
148 __modify_IO_APIC_irq(irq, 0x00010000, 0);
152 static void __unmask_IO_APIC_irq (unsigned int irq)
154 __modify_IO_APIC_irq(irq, 0, 0x00010000);
157 /* mask = 1, trigger = 0 */
158 static void __mask_and_edge_IO_APIC_irq (unsigned int irq)
160 __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000);
163 /* mask = 0, trigger = 1 */
164 static void __unmask_and_level_IO_APIC_irq (unsigned int irq)
166 __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000);
169 static void mask_IO_APIC_irq (unsigned int irq)
173 spin_lock_irqsave(&ioapic_lock, flags);
174 __mask_IO_APIC_irq(irq);
175 spin_unlock_irqrestore(&ioapic_lock, flags);
178 static void unmask_IO_APIC_irq (unsigned int irq)
182 spin_lock_irqsave(&ioapic_lock, flags);
183 __unmask_IO_APIC_irq(irq);
184 spin_unlock_irqrestore(&ioapic_lock, flags);
187 void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
189 struct IO_APIC_route_entry entry;
192 /* Check delivery_mode to be sure we're not clearing an SMI pin */
193 spin_lock_irqsave(&ioapic_lock, flags);
194 *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
195 *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
196 spin_unlock_irqrestore(&ioapic_lock, flags);
197 if (entry.delivery_mode == dest_SMI)
201 * Disable it in the IO-APIC irq-routing table:
203 memset(&entry, 0, sizeof(entry));
205 spin_lock_irqsave(&ioapic_lock, flags);
206 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
207 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
208 spin_unlock_irqrestore(&ioapic_lock, flags);
211 static void clear_IO_APIC (void)
215 for (apic = 0; apic < nr_ioapics; apic++)
216 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
217 clear_IO_APIC_pin(apic, pin);
220 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
224 struct irq_pin_list *entry = irq_2_pin + irq;
225 unsigned int apicid_value;
227 apicid_value = cpu_mask_to_apicid(cpumask);
228 /* Prepare to do the io_apic_write */
229 apicid_value = apicid_value << 24;
230 spin_lock_irqsave(&ioapic_lock, flags);
235 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
238 entry = irq_2_pin + entry->next;
240 spin_unlock_irqrestore(&ioapic_lock, flags);
243 #if defined(CONFIG_IRQBALANCE)
244 # include <asm/processor.h> /* kernel_thread() */
245 # include <linux/kernel_stat.h> /* kstat */
246 # include <linux/slab.h> /* kmalloc() */
247 # include <linux/timer.h> /* time_after() */
249 # ifdef CONFIG_BALANCED_IRQ_DEBUG
250 # define TDprintk(x...) do { printk("<%ld:%s:%d>: ", jiffies, __FILE__, __LINE__); printk(x); } while (0)
251 # define Dprintk(x...) do { TDprintk(x); } while (0)
253 # define TDprintk(x...)
254 # define Dprintk(x...)
257 extern cpumask_t irq_affinity[NR_IRQS];
259 cpumask_t __cacheline_aligned pending_irq_balance_cpumask[NR_IRQS];
261 #define IRQBALANCE_CHECK_ARCH -999
262 static int irqbalance_disabled = IRQBALANCE_CHECK_ARCH;
263 static int physical_balance = 0;
265 struct irq_cpu_info {
266 unsigned long * last_irq;
267 unsigned long * irq_delta;
269 } irq_cpu_data[NR_CPUS];
271 #define CPU_IRQ(cpu) (irq_cpu_data[cpu].irq)
272 #define LAST_CPU_IRQ(cpu,irq) (irq_cpu_data[cpu].last_irq[irq])
273 #define IRQ_DELTA(cpu,irq) (irq_cpu_data[cpu].irq_delta[irq])
275 #define IDLE_ENOUGH(cpu,now) \
276 (idle_cpu(cpu) && ((now) - irq_stat[(cpu)].idle_timestamp > 1))
278 #define IRQ_ALLOWED(cpu, allowed_mask) cpu_isset(cpu, allowed_mask)
280 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(cpu_sibling_map[i]))
282 #define MAX_BALANCED_IRQ_INTERVAL (5*HZ)
283 #define MIN_BALANCED_IRQ_INTERVAL (HZ/2)
284 #define BALANCED_IRQ_MORE_DELTA (HZ/10)
285 #define BALANCED_IRQ_LESS_DELTA (HZ)
287 long balanced_irq_interval = MAX_BALANCED_IRQ_INTERVAL;
289 static unsigned long move(int curr_cpu, cpumask_t allowed_mask,
290 unsigned long now, int direction)
298 if (unlikely(cpu == curr_cpu))
301 if (direction == 1) {
310 } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) ||
311 (search_idle && !IDLE_ENOUGH(cpu,now)));
316 static inline void balance_irq(int cpu, int irq)
318 unsigned long now = jiffies;
319 cpumask_t allowed_mask;
320 unsigned int new_cpu;
322 if (irqbalance_disabled)
325 cpus_and(allowed_mask, cpu_online_map, irq_affinity[irq]);
326 new_cpu = move(cpu, allowed_mask, now, 1);
327 if (cpu != new_cpu) {
328 irq_desc_t *desc = irq_desc + irq;
331 spin_lock_irqsave(&desc->lock, flags);
332 pending_irq_balance_cpumask[irq] = cpumask_of_cpu(new_cpu);
333 spin_unlock_irqrestore(&desc->lock, flags);
337 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
340 Dprintk("Rotating IRQs among CPUs.\n");
341 for (i = 0; i < NR_CPUS; i++) {
342 for (j = 0; cpu_online(i) && (j < NR_IRQS); j++) {
343 if (!irq_desc[j].action)
345 /* Is it a significant load ? */
346 if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) <
347 useful_load_threshold)
352 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
353 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
357 static void do_irq_balance(void)
360 unsigned long max_cpu_irq = 0, min_cpu_irq = (~0);
361 unsigned long move_this_load = 0;
362 int max_loaded = 0, min_loaded = 0;
364 unsigned long useful_load_threshold = balanced_irq_interval + 10;
366 int tmp_loaded, first_attempt = 1;
367 unsigned long tmp_cpu_irq;
368 unsigned long imbalance = 0;
369 cpumask_t allowed_mask, target_cpu_mask, tmp;
371 for (i = 0; i < NR_CPUS; i++) {
376 package_index = CPU_TO_PACKAGEINDEX(i);
377 for (j = 0; j < NR_IRQS; j++) {
378 unsigned long value_now, delta;
379 /* Is this an active IRQ? */
380 if (!irq_desc[j].action)
382 if ( package_index == i )
383 IRQ_DELTA(package_index,j) = 0;
384 /* Determine the total count per processor per IRQ */
385 value_now = (unsigned long) kstat_cpu(i).irqs[j];
387 /* Determine the activity per processor per IRQ */
388 delta = value_now - LAST_CPU_IRQ(i,j);
390 /* Update last_cpu_irq[][] for the next time */
391 LAST_CPU_IRQ(i,j) = value_now;
393 /* Ignore IRQs whose rate is less than the clock */
394 if (delta < useful_load_threshold)
396 /* update the load for the processor or package total */
397 IRQ_DELTA(package_index,j) += delta;
399 /* Keep track of the higher numbered sibling as well */
400 if (i != package_index)
403 * We have sibling A and sibling B in the package
405 * cpu_irq[A] = load for cpu A + load for cpu B
406 * cpu_irq[B] = load for cpu B
408 CPU_IRQ(package_index) += delta;
411 /* Find the least loaded processor package */
412 for (i = 0; i < NR_CPUS; i++) {
415 if (i != CPU_TO_PACKAGEINDEX(i))
417 if (min_cpu_irq > CPU_IRQ(i)) {
418 min_cpu_irq = CPU_IRQ(i);
422 max_cpu_irq = ULONG_MAX;
425 /* Look for heaviest loaded processor.
426 * We may come back to get the next heaviest loaded processor.
427 * Skip processors with trivial loads.
431 for (i = 0; i < NR_CPUS; i++) {
434 if (i != CPU_TO_PACKAGEINDEX(i))
436 if (max_cpu_irq <= CPU_IRQ(i))
438 if (tmp_cpu_irq < CPU_IRQ(i)) {
439 tmp_cpu_irq = CPU_IRQ(i);
444 if (tmp_loaded == -1) {
445 /* In the case of small number of heavy interrupt sources,
446 * loading some of the cpus too much. We use Ingo's original
447 * approach to rotate them around.
449 if (!first_attempt && imbalance >= useful_load_threshold) {
450 rotate_irqs_among_cpus(useful_load_threshold);
453 goto not_worth_the_effort;
456 first_attempt = 0; /* heaviest search */
457 max_cpu_irq = tmp_cpu_irq; /* load */
458 max_loaded = tmp_loaded; /* processor */
459 imbalance = (max_cpu_irq - min_cpu_irq) / 2;
461 Dprintk("max_loaded cpu = %d\n", max_loaded);
462 Dprintk("min_loaded cpu = %d\n", min_loaded);
463 Dprintk("max_cpu_irq load = %ld\n", max_cpu_irq);
464 Dprintk("min_cpu_irq load = %ld\n", min_cpu_irq);
465 Dprintk("load imbalance = %lu\n", imbalance);
467 /* if imbalance is less than approx 10% of max load, then
468 * observe diminishing returns action. - quit
470 if (imbalance < (max_cpu_irq >> 3)) {
471 Dprintk("Imbalance too trivial\n");
472 goto not_worth_the_effort;
476 /* if we select an IRQ to move that can't go where we want, then
477 * see if there is another one to try.
481 for (j = 0; j < NR_IRQS; j++) {
482 /* Is this an active IRQ? */
483 if (!irq_desc[j].action)
485 if (imbalance <= IRQ_DELTA(max_loaded,j))
487 /* Try to find the IRQ that is closest to the imbalance
488 * without going over.
490 if (move_this_load < IRQ_DELTA(max_loaded,j)) {
491 move_this_load = IRQ_DELTA(max_loaded,j);
495 if (selected_irq == -1) {
499 imbalance = move_this_load;
501 /* For physical_balance case, we accumlated both load
502 * values in the one of the siblings cpu_irq[],
503 * to use the same code for physical and logical processors
504 * as much as possible.
506 * NOTE: the cpu_irq[] array holds the sum of the load for
507 * sibling A and sibling B in the slot for the lowest numbered
508 * sibling (A), _AND_ the load for sibling B in the slot for
509 * the higher numbered sibling.
511 * We seek the least loaded sibling by making the comparison
514 load = CPU_IRQ(min_loaded) >> 1;
515 for_each_cpu_mask(j, cpu_sibling_map[min_loaded]) {
516 if (load > CPU_IRQ(j)) {
517 /* This won't change cpu_sibling_map[min_loaded] */
523 cpus_and(allowed_mask, cpu_online_map, irq_affinity[selected_irq]);
524 target_cpu_mask = cpumask_of_cpu(min_loaded);
525 cpus_and(tmp, target_cpu_mask, allowed_mask);
527 if (!cpus_empty(tmp)) {
528 irq_desc_t *desc = irq_desc + selected_irq;
531 Dprintk("irq = %d moved to cpu = %d\n",
532 selected_irq, min_loaded);
533 /* mark for change destination */
534 spin_lock_irqsave(&desc->lock, flags);
535 pending_irq_balance_cpumask[selected_irq] =
536 cpumask_of_cpu(min_loaded);
537 spin_unlock_irqrestore(&desc->lock, flags);
538 /* Since we made a change, come back sooner to
539 * check for more variation.
541 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
542 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
547 not_worth_the_effort:
549 * if we did not find an IRQ to move, then adjust the time interval
552 balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
553 balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);
554 Dprintk("IRQ worth rotating not found\n");
558 static int balanced_irq(void *unused)
561 unsigned long prev_balance_time = jiffies;
562 long time_remaining = balanced_irq_interval;
566 /* push everything to CPU 0 to give us a starting point. */
567 for (i = 0 ; i < NR_IRQS ; i++) {
568 pending_irq_balance_cpumask[i] = cpumask_of_cpu(0);
572 set_current_state(TASK_INTERRUPTIBLE);
573 time_remaining = schedule_timeout(time_remaining);
574 if (time_after(jiffies,
575 prev_balance_time+balanced_irq_interval)) {
577 prev_balance_time = jiffies;
578 time_remaining = balanced_irq_interval;
584 static int __init balanced_irq_init(void)
587 struct cpuinfo_x86 *c;
590 cpus_shift_right(tmp, cpu_online_map, 2);
592 /* When not overwritten by the command line ask subarchitecture. */
593 if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
594 irqbalance_disabled = NO_BALANCE_IRQ;
595 if (irqbalance_disabled)
598 /* disable irqbalance completely if there is only one processor online */
599 if (num_online_cpus() < 2) {
600 irqbalance_disabled = 1;
604 * Enable physical balance only if more than 1 physical processor
607 if (smp_num_siblings > 1 && !cpus_empty(tmp))
608 physical_balance = 1;
610 for (i = 0; i < NR_CPUS; i++) {
613 irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
614 irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
615 if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
616 printk(KERN_ERR "balanced_irq_init: out of memory");
619 memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS);
620 memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS);
623 printk(KERN_INFO "Starting balanced_irq\n");
624 if (kernel_thread(balanced_irq, NULL, CLONE_KERNEL) >= 0)
627 printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq");
629 for (i = 0; i < NR_CPUS; i++) {
630 if(irq_cpu_data[i].irq_delta)
631 kfree(irq_cpu_data[i].irq_delta);
632 if(irq_cpu_data[i].last_irq)
633 kfree(irq_cpu_data[i].last_irq);
638 static int __init irqbalance_disable(char *str)
640 irqbalance_disabled = 1;
644 __setup("noirqbalance", irqbalance_disable);
646 static inline void move_irq(int irq)
648 /* note - we hold the desc->lock */
649 if (unlikely(!cpus_empty(pending_irq_balance_cpumask[irq]))) {
650 set_ioapic_affinity_irq(irq, pending_irq_balance_cpumask[irq]);
651 cpus_clear(pending_irq_balance_cpumask[irq]);
655 __initcall(balanced_irq_init);
657 #else /* !CONFIG_IRQBALANCE */
658 static inline void move_irq(int irq) { }
659 #endif /* CONFIG_IRQBALANCE */
662 void fastcall send_IPI_self(int vector)
669 apic_wait_icr_idle();
670 cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
672 * Send the IPI. The write to APIC_ICR fires this off.
674 apic_write_around(APIC_ICR, cfg);
676 #endif /* !CONFIG_SMP */
680 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
681 * specific CPU-side IRQs.
685 int pirq_entries [MAX_PIRQS];
687 int skip_ioapic_setup;
689 static int __init ioapic_setup(char *str)
691 skip_ioapic_setup = 1;
695 __setup("noapic", ioapic_setup);
697 static int __init ioapic_pirq_setup(char *str)
700 int ints[MAX_PIRQS+1];
702 get_options(str, ARRAY_SIZE(ints), ints);
704 for (i = 0; i < MAX_PIRQS; i++)
705 pirq_entries[i] = -1;
708 printk(KERN_INFO "PIRQ redirection, working around broken MP-BIOS.\n");
710 if (ints[0] < MAX_PIRQS)
713 for (i = 0; i < max; i++) {
714 printk(KERN_DEBUG "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
716 * PIRQs are mapped upside down, usually.
718 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
723 __setup("pirq=", ioapic_pirq_setup);
726 * Find the IRQ entry number of a certain pin.
728 static int __init find_irq_entry(int apic, int pin, int type)
732 for (i = 0; i < mp_irq_entries; i++)
733 if (mp_irqs[i].mpc_irqtype == type &&
734 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
735 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
736 mp_irqs[i].mpc_dstirq == pin)
743 * Find the pin to which IRQ[irq] (ISA) is connected
745 static int __init find_isa_irq_pin(int irq, int type)
749 for (i = 0; i < mp_irq_entries; i++) {
750 int lbus = mp_irqs[i].mpc_srcbus;
752 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
753 mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
754 mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
755 mp_bus_id_to_type[lbus] == MP_BUS_NEC98
757 (mp_irqs[i].mpc_irqtype == type) &&
758 (mp_irqs[i].mpc_srcbusirq == irq))
760 return mp_irqs[i].mpc_dstirq;
766 * Find a specific PCI IRQ entry.
767 * Not an __init, possibly needed by modules
769 static int pin_2_irq(int idx, int apic, int pin);
771 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
773 int apic, i, best_guess = -1;
775 Dprintk("querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
777 if (mp_bus_id_to_pci_bus[bus] == -1) {
778 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
781 for (i = 0; i < mp_irq_entries; i++) {
782 int lbus = mp_irqs[i].mpc_srcbus;
784 for (apic = 0; apic < nr_ioapics; apic++)
785 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
786 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
789 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
790 !mp_irqs[i].mpc_irqtype &&
792 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
793 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
795 if (!(apic || IO_APIC_IRQ(irq)))
798 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
801 * Use the first all-but-pin matching entry as a
802 * best-guess fuzzy result for broken mptables.
812 * This function currently is only a helper for the i386 smp boot process where
813 * we need to reprogram the ioredtbls to cater for the cpus which have come online
814 * so mask in all cases should simply be TARGET_CPUS
816 void __init setup_ioapic_dest(void)
818 int pin, ioapic, irq, irq_entry;
820 if (skip_ioapic_setup == 1)
823 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
824 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
825 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
828 irq = pin_2_irq(irq_entry, ioapic, pin);
829 set_ioapic_affinity_irq(irq, TARGET_CPUS);
836 * EISA Edge/Level control register, ELCR
838 static int __init EISA_ELCR(unsigned int irq)
841 unsigned int port = 0x4d0 + (irq >> 3);
842 return (inb(port) >> (irq & 7)) & 1;
844 printk(KERN_INFO "Broken MPtable reports ISA irq %d\n", irq);
848 /* EISA interrupts are always polarity zero and can be edge or level
849 * trigger depending on the ELCR value. If an interrupt is listed as
850 * EISA conforming in the MP table, that means its trigger type must
851 * be read in from the ELCR */
853 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
854 #define default_EISA_polarity(idx) (0)
856 /* ISA interrupts are always polarity zero edge triggered,
857 * when listed as conforming in the MP table. */
859 #define default_ISA_trigger(idx) (0)
860 #define default_ISA_polarity(idx) (0)
862 /* PCI interrupts are always polarity one level triggered,
863 * when listed as conforming in the MP table. */
865 #define default_PCI_trigger(idx) (1)
866 #define default_PCI_polarity(idx) (1)
868 /* MCA interrupts are always polarity zero level triggered,
869 * when listed as conforming in the MP table. */
871 #define default_MCA_trigger(idx) (1)
872 #define default_MCA_polarity(idx) (0)
874 /* NEC98 interrupts are always polarity zero edge triggered,
875 * when listed as conforming in the MP table. */
877 #define default_NEC98_trigger(idx) (0)
878 #define default_NEC98_polarity(idx) (0)
880 static int __init MPBIOS_polarity(int idx)
882 int bus = mp_irqs[idx].mpc_srcbus;
886 * Determine IRQ line polarity (high active or low active):
888 switch (mp_irqs[idx].mpc_irqflag & 3)
890 case 0: /* conforms, ie. bus-type dependent polarity */
892 switch (mp_bus_id_to_type[bus])
894 case MP_BUS_ISA: /* ISA pin */
896 polarity = default_ISA_polarity(idx);
899 case MP_BUS_EISA: /* EISA pin */
901 polarity = default_EISA_polarity(idx);
904 case MP_BUS_PCI: /* PCI pin */
906 polarity = default_PCI_polarity(idx);
909 case MP_BUS_MCA: /* MCA pin */
911 polarity = default_MCA_polarity(idx);
914 case MP_BUS_NEC98: /* NEC 98 pin */
916 polarity = default_NEC98_polarity(idx);
921 printk(KERN_WARNING "broken BIOS!!\n");
928 case 1: /* high active */
933 case 2: /* reserved */
935 printk(KERN_WARNING "broken BIOS!!\n");
939 case 3: /* low active */
944 default: /* invalid */
946 printk(KERN_WARNING "broken BIOS!!\n");
954 static int __init MPBIOS_trigger(int idx)
956 int bus = mp_irqs[idx].mpc_srcbus;
960 * Determine IRQ trigger mode (edge or level sensitive):
962 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
964 case 0: /* conforms, ie. bus-type dependent */
966 switch (mp_bus_id_to_type[bus])
968 case MP_BUS_ISA: /* ISA pin */
970 trigger = default_ISA_trigger(idx);
973 case MP_BUS_EISA: /* EISA pin */
975 trigger = default_EISA_trigger(idx);
978 case MP_BUS_PCI: /* PCI pin */
980 trigger = default_PCI_trigger(idx);
983 case MP_BUS_MCA: /* MCA pin */
985 trigger = default_MCA_trigger(idx);
988 case MP_BUS_NEC98: /* NEC 98 pin */
990 trigger = default_NEC98_trigger(idx);
995 printk(KERN_WARNING "broken BIOS!!\n");
1007 case 2: /* reserved */
1009 printk(KERN_WARNING "broken BIOS!!\n");
1018 default: /* invalid */
1020 printk(KERN_WARNING "broken BIOS!!\n");
1028 static inline int irq_polarity(int idx)
1030 return MPBIOS_polarity(idx);
1033 static inline int irq_trigger(int idx)
1035 return MPBIOS_trigger(idx);
1038 static int pin_2_irq(int idx, int apic, int pin)
1041 int bus = mp_irqs[idx].mpc_srcbus;
1044 * Debugging check, we are in big trouble if this message pops up!
1046 if (mp_irqs[idx].mpc_dstirq != pin)
1047 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1049 switch (mp_bus_id_to_type[bus])
1051 case MP_BUS_ISA: /* ISA pin */
1056 irq = mp_irqs[idx].mpc_srcbusirq;
1059 case MP_BUS_PCI: /* PCI pin */
1062 * PCI IRQs are mapped in order
1066 irq += nr_ioapic_registers[i++];
1068 if ((!apic) && (irq < 16))
1074 printk(KERN_ERR "unknown bus type %d.\n",bus);
1081 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1083 if ((pin >= 16) && (pin <= 23)) {
1084 if (pirq_entries[pin-16] != -1) {
1085 if (!pirq_entries[pin-16]) {
1086 printk(KERN_DEBUG "disabling PIRQ%d\n", pin-16);
1088 irq = pirq_entries[pin-16];
1089 printk(KERN_DEBUG "using PIRQ%d -> IRQ %d\n",
1097 static inline int IO_APIC_irq_trigger(int irq)
1101 for (apic = 0; apic < nr_ioapics; apic++) {
1102 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1103 idx = find_irq_entry(apic,pin,mp_INT);
1104 if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
1105 return irq_trigger(idx);
1109 * nonexistent IRQs are edge default
1114 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1115 u8 irq_vector[NR_IRQ_VECTORS] = { FIRST_DEVICE_VECTOR , 0 };
1117 #ifdef CONFIG_PCI_USE_VECTOR
1118 int assign_irq_vector(int irq)
1120 int __init assign_irq_vector(int irq)
1123 static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
1125 BUG_ON(irq >= NR_IRQ_VECTORS);
1126 if (irq != AUTO_ASSIGN && IO_APIC_VECTOR(irq) > 0)
1127 return IO_APIC_VECTOR(irq);
1129 current_vector += 8;
1130 if (current_vector == SYSCALL_VECTOR)
1133 if (current_vector >= FIRST_SYSTEM_VECTOR) {
1137 current_vector = FIRST_DEVICE_VECTOR + offset;
1140 vector_irq[current_vector] = irq;
1141 if (irq != AUTO_ASSIGN)
1142 IO_APIC_VECTOR(irq) = current_vector;
1144 return current_vector;
1147 static struct hw_interrupt_type ioapic_level_type;
1148 static struct hw_interrupt_type ioapic_edge_type;
1150 #define IOAPIC_AUTO -1
1151 #define IOAPIC_EDGE 0
1152 #define IOAPIC_LEVEL 1
1154 static inline void ioapic_register_intr(int irq, int vector, unsigned long trigger)
1156 if (use_pci_vector() && !platform_legacy_irq(irq)) {
1157 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1158 trigger == IOAPIC_LEVEL)
1159 irq_desc[vector].handler = &ioapic_level_type;
1161 irq_desc[vector].handler = &ioapic_edge_type;
1162 set_intr_gate(vector, interrupt[vector]);
1164 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1165 trigger == IOAPIC_LEVEL)
1166 irq_desc[irq].handler = &ioapic_level_type;
1168 irq_desc[irq].handler = &ioapic_edge_type;
1169 set_intr_gate(vector, interrupt[irq]);
1173 void __init setup_IO_APIC_irqs(void)
1175 struct IO_APIC_route_entry entry;
1176 int apic, pin, idx, irq, first_notcon = 1, vector;
1177 unsigned long flags;
1179 printk(KERN_DEBUG "init IO_APIC IRQs\n");
1181 for (apic = 0; apic < nr_ioapics; apic++) {
1182 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1185 * add it to the IO-APIC irq-routing table:
1187 memset(&entry,0,sizeof(entry));
1189 entry.delivery_mode = INT_DELIVERY_MODE;
1190 entry.dest_mode = INT_DEST_MODE;
1191 entry.mask = 0; /* enable IRQ */
1192 entry.dest.logical.logical_dest =
1193 cpu_mask_to_apicid(TARGET_CPUS);
1195 idx = find_irq_entry(apic,pin,mp_INT);
1198 printk(KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
1201 printk(", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
1205 entry.trigger = irq_trigger(idx);
1206 entry.polarity = irq_polarity(idx);
1208 if (irq_trigger(idx)) {
1213 irq = pin_2_irq(idx, apic, pin);
1215 * skip adding the timer int on secondary nodes, which causes
1216 * a small but painful rift in the time-space continuum
1218 if (multi_timer_check(apic, irq))
1221 add_pin_to_irq(irq, apic, pin);
1223 if (!apic && !IO_APIC_IRQ(irq))
1226 if (IO_APIC_IRQ(irq)) {
1227 vector = assign_irq_vector(irq);
1228 entry.vector = vector;
1229 ioapic_register_intr(irq, vector, IOAPIC_AUTO);
1231 if (!apic && (irq < 16))
1232 disable_8259A_irq(irq);
1234 spin_lock_irqsave(&ioapic_lock, flags);
1235 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
1236 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
1237 spin_unlock_irqrestore(&ioapic_lock, flags);
1242 printk(" not connected.\n");
1246 * Set up the 8259A-master output pin:
1248 void __init setup_ExtINT_IRQ0_pin(unsigned int pin, int vector)
1250 struct IO_APIC_route_entry entry;
1251 unsigned long flags;
1253 memset(&entry,0,sizeof(entry));
1255 disable_8259A_irq(0);
1258 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1261 * We use logical delivery to get the timer IRQ
1264 entry.dest_mode = INT_DEST_MODE;
1265 entry.mask = 0; /* unmask IRQ now */
1266 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1267 entry.delivery_mode = INT_DELIVERY_MODE;
1270 entry.vector = vector;
1273 * The timer IRQ doesn't have to know that behind the
1274 * scene we have a 8259A-master in AEOI mode ...
1276 irq_desc[0].handler = &ioapic_edge_type;
1279 * Add it to the IO-APIC irq-routing table:
1281 spin_lock_irqsave(&ioapic_lock, flags);
1282 io_apic_write(0, 0x11+2*pin, *(((int *)&entry)+1));
1283 io_apic_write(0, 0x10+2*pin, *(((int *)&entry)+0));
1284 spin_unlock_irqrestore(&ioapic_lock, flags);
1286 enable_8259A_irq(0);
1289 static inline void UNEXPECTED_IO_APIC(void)
1293 void __init print_IO_APIC(void)
1296 union IO_APIC_reg_00 reg_00;
1297 union IO_APIC_reg_01 reg_01;
1298 union IO_APIC_reg_02 reg_02;
1299 union IO_APIC_reg_03 reg_03;
1300 unsigned long flags;
1302 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1303 for (i = 0; i < nr_ioapics; i++)
1304 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1305 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
1308 * We are a bit conservative about what we expect. We have to
1309 * know about every hardware change ASAP.
1311 printk(KERN_INFO "testing the IO APIC.......................\n");
1313 for (apic = 0; apic < nr_ioapics; apic++) {
1315 spin_lock_irqsave(&ioapic_lock, flags);
1316 reg_00.raw = io_apic_read(apic, 0);
1317 reg_01.raw = io_apic_read(apic, 1);
1318 if (reg_01.bits.version >= 0x10)
1319 reg_02.raw = io_apic_read(apic, 2);
1320 if (reg_01.bits.version >= 0x20)
1321 reg_03.raw = io_apic_read(apic, 3);
1322 spin_unlock_irqrestore(&ioapic_lock, flags);
1324 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1325 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1326 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1327 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1328 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1329 if (reg_00.bits.ID >= get_physical_broadcast())
1330 UNEXPECTED_IO_APIC();
1331 if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
1332 UNEXPECTED_IO_APIC();
1334 printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1335 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1336 if ( (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
1337 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
1338 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
1339 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
1340 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
1341 (reg_01.bits.entries != 0x2E) &&
1342 (reg_01.bits.entries != 0x3F)
1344 UNEXPECTED_IO_APIC();
1346 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1347 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1348 if ( (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
1349 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
1350 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
1351 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
1352 (reg_01.bits.version != 0x20) /* Intel P64H (82806 AA) */
1354 UNEXPECTED_IO_APIC();
1355 if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
1356 UNEXPECTED_IO_APIC();
1359 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1360 * but the value of reg_02 is read as the previous read register
1361 * value, so ignore it if reg_02 == reg_01.
1363 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1364 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1365 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1366 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
1367 UNEXPECTED_IO_APIC();
1371 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1372 * or reg_03, but the value of reg_0[23] is read as the previous read
1373 * register value, so ignore it if reg_03 == reg_0[12].
1375 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1376 reg_03.raw != reg_01.raw) {
1377 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1378 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1379 if (reg_03.bits.__reserved_1)
1380 UNEXPECTED_IO_APIC();
1383 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1385 printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1386 " Stat Dest Deli Vect: \n");
1388 for (i = 0; i <= reg_01.bits.entries; i++) {
1389 struct IO_APIC_route_entry entry;
1391 spin_lock_irqsave(&ioapic_lock, flags);
1392 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
1393 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
1394 spin_unlock_irqrestore(&ioapic_lock, flags);
1396 printk(KERN_DEBUG " %02x %03X %02X ",
1398 entry.dest.logical.logical_dest,
1399 entry.dest.physical.physical_dest
1402 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1407 entry.delivery_status,
1409 entry.delivery_mode,
1414 if (use_pci_vector())
1415 printk(KERN_INFO "Using vector-based indexing\n");
1416 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1417 for (i = 0; i < NR_IRQS; i++) {
1418 struct irq_pin_list *entry = irq_2_pin + i;
1421 if (use_pci_vector() && !platform_legacy_irq(i))
1422 printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
1424 printk(KERN_DEBUG "IRQ%d ", i);
1426 printk("-> %d:%d", entry->apic, entry->pin);
1429 entry = irq_2_pin + entry->next;
1434 printk(KERN_INFO ".................................... done.\n");
1439 static void print_APIC_bitfield (int base)
1444 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1445 for (i = 0; i < 8; i++) {
1446 v = apic_read(base + i*0x10);
1447 for (j = 0; j < 32; j++) {
1457 void /*__init*/ print_local_APIC(void * dummy)
1459 unsigned int v, ver, maxlvt;
1461 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1462 smp_processor_id(), hard_smp_processor_id());
1463 v = apic_read(APIC_ID);
1464 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v));
1465 v = apic_read(APIC_LVR);
1466 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1467 ver = GET_APIC_VERSION(v);
1468 maxlvt = get_maxlvt();
1470 v = apic_read(APIC_TASKPRI);
1471 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1473 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1474 v = apic_read(APIC_ARBPRI);
1475 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1476 v & APIC_ARBPRI_MASK);
1477 v = apic_read(APIC_PROCPRI);
1478 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1481 v = apic_read(APIC_EOI);
1482 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1483 v = apic_read(APIC_RRR);
1484 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1485 v = apic_read(APIC_LDR);
1486 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1487 v = apic_read(APIC_DFR);
1488 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1489 v = apic_read(APIC_SPIV);
1490 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1492 printk(KERN_DEBUG "... APIC ISR field:\n");
1493 print_APIC_bitfield(APIC_ISR);
1494 printk(KERN_DEBUG "... APIC TMR field:\n");
1495 print_APIC_bitfield(APIC_TMR);
1496 printk(KERN_DEBUG "... APIC IRR field:\n");
1497 print_APIC_bitfield(APIC_IRR);
1499 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1500 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1501 apic_write(APIC_ESR, 0);
1502 v = apic_read(APIC_ESR);
1503 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1506 v = apic_read(APIC_ICR);
1507 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1508 v = apic_read(APIC_ICR2);
1509 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1511 v = apic_read(APIC_LVTT);
1512 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1514 if (maxlvt > 3) { /* PC is LVT#4. */
1515 v = apic_read(APIC_LVTPC);
1516 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1518 v = apic_read(APIC_LVT0);
1519 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1520 v = apic_read(APIC_LVT1);
1521 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1523 if (maxlvt > 2) { /* ERR is LVT#3. */
1524 v = apic_read(APIC_LVTERR);
1525 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1528 v = apic_read(APIC_TMICT);
1529 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1530 v = apic_read(APIC_TMCCT);
1531 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1532 v = apic_read(APIC_TDCR);
1533 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1537 void print_all_local_APICs (void)
1539 on_each_cpu(print_local_APIC, NULL, 1, 1);
1542 void /*__init*/ print_PIC(void)
1544 extern spinlock_t i8259A_lock;
1546 unsigned long flags;
1548 printk(KERN_DEBUG "\nprinting PIC contents\n");
1550 spin_lock_irqsave(&i8259A_lock, flags);
1552 v = inb(0xa1) << 8 | inb(0x21);
1553 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1555 v = inb(0xa0) << 8 | inb(0x20);
1556 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1560 v = inb(0xa0) << 8 | inb(0x20);
1564 spin_unlock_irqrestore(&i8259A_lock, flags);
1566 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1568 v = inb(0x4d1) << 8 | inb(0x4d0);
1569 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1572 static void __init enable_IO_APIC(void)
1574 union IO_APIC_reg_01 reg_01;
1576 unsigned long flags;
1578 for (i = 0; i < PIN_MAP_SIZE; i++) {
1579 irq_2_pin[i].pin = -1;
1580 irq_2_pin[i].next = 0;
1583 for (i = 0; i < MAX_PIRQS; i++)
1584 pirq_entries[i] = -1;
1587 * The number of IO-APIC IRQ registers (== #pins):
1589 for (i = 0; i < nr_ioapics; i++) {
1590 spin_lock_irqsave(&ioapic_lock, flags);
1591 reg_01.raw = io_apic_read(i, 1);
1592 spin_unlock_irqrestore(&ioapic_lock, flags);
1593 nr_ioapic_registers[i] = reg_01.bits.entries+1;
1597 * Do not trust the IO-APIC being empty at bootup
1603 * Not an __init, needed by the reboot code
1605 void disable_IO_APIC(void)
1608 * Clear the IO-APIC before rebooting:
1612 disconnect_bsp_APIC();
1616 * function to set the IO-APIC physical IDs based on the
1617 * values stored in the MPC table.
1619 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1622 #ifndef CONFIG_X86_NUMAQ
1623 static void __init setup_ioapic_ids_from_mpc(void)
1625 union IO_APIC_reg_00 reg_00;
1626 physid_mask_t phys_id_present_map;
1629 unsigned char old_id;
1630 unsigned long flags;
1633 * This is broken; anything with a real cpu count has to
1634 * circumvent this idiocy regardless.
1636 phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1639 * Set the IOAPIC ID to the value stored in the MPC table.
1641 for (apic = 0; apic < nr_ioapics; apic++) {
1643 /* Read the register 0 value */
1644 spin_lock_irqsave(&ioapic_lock, flags);
1645 reg_00.raw = io_apic_read(apic, 0);
1646 spin_unlock_irqrestore(&ioapic_lock, flags);
1648 old_id = mp_ioapics[apic].mpc_apicid;
1650 if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
1651 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1652 apic, mp_ioapics[apic].mpc_apicid);
1653 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1655 mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1658 /* Don't check I/O APIC IDs for some xAPIC systems. They have
1659 * no meaning without the serial APIC bus. */
1660 if (NO_IOAPIC_CHECK)
1663 * Sanity check, is the ID really free? Every APIC in a
1664 * system must have a unique ID or we get lots of nice
1665 * 'stuck on smp_invalidate_needed IPI wait' messages.
1667 if (check_apicid_used(phys_id_present_map,
1668 mp_ioapics[apic].mpc_apicid)) {
1669 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1670 apic, mp_ioapics[apic].mpc_apicid);
1671 for (i = 0; i < get_physical_broadcast(); i++)
1672 if (!physid_isset(i, phys_id_present_map))
1674 if (i >= get_physical_broadcast())
1675 panic("Max APIC ID exceeded!\n");
1676 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1678 physid_set(i, phys_id_present_map);
1679 mp_ioapics[apic].mpc_apicid = i;
1682 tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
1683 printk("Setting %d in the phys_id_present_map\n", mp_ioapics[apic].mpc_apicid);
1684 physids_or(phys_id_present_map, phys_id_present_map, tmp);
1689 * We need to adjust the IRQ routing table
1690 * if the ID changed.
1692 if (old_id != mp_ioapics[apic].mpc_apicid)
1693 for (i = 0; i < mp_irq_entries; i++)
1694 if (mp_irqs[i].mpc_dstapic == old_id)
1695 mp_irqs[i].mpc_dstapic
1696 = mp_ioapics[apic].mpc_apicid;
1699 * Read the right value from the MPC table and
1700 * write it into the ID register.
1702 printk(KERN_INFO "...changing IO-APIC physical APIC ID to %d ...",
1703 mp_ioapics[apic].mpc_apicid);
1705 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1706 spin_lock_irqsave(&ioapic_lock, flags);
1707 io_apic_write(apic, 0, reg_00.raw);
1708 spin_unlock_irqrestore(&ioapic_lock, flags);
1713 spin_lock_irqsave(&ioapic_lock, flags);
1714 reg_00.raw = io_apic_read(apic, 0);
1715 spin_unlock_irqrestore(&ioapic_lock, flags);
1716 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1717 panic("could not set ID!\n");
1723 static void __init setup_ioapic_ids_from_mpc(void) { }
1727 * There is a nasty bug in some older SMP boards, their mptable lies
1728 * about the timer IRQ. We do the following to work around the situation:
1730 * - timer IRQ defaults to IO-APIC IRQ
1731 * - if this function detects that timer IRQs are defunct, then we fall
1732 * back to ISA timer IRQs
1734 static int __init timer_irq_works(void)
1736 unsigned long t1 = jiffies;
1739 /* Let ten ticks pass... */
1740 mdelay((10 * 1000) / HZ);
1743 * Expect a few ticks at least, to be sure some possible
1744 * glue logic does not lock up after one or two first
1745 * ticks in a non-ExtINT mode. Also the local APIC
1746 * might have cached one ExtINT interrupt. Finally, at
1747 * least one tick may be lost due to delays.
1749 if (jiffies - t1 > 4)
1756 * In the SMP+IOAPIC case it might happen that there are an unspecified
1757 * number of pending IRQ events unhandled. These cases are very rare,
1758 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1759 * better to do it this way as thus we do not have to be aware of
1760 * 'pending' interrupts in the IRQ path, except at this point.
1763 * Edge triggered needs to resend any interrupt
1764 * that was delayed but this is now handled in the device
1769 * Starting up a edge-triggered IO-APIC interrupt is
1770 * nasty - we need to make sure that we get the edge.
1771 * If it is already asserted for some reason, we need
1772 * return 1 to indicate that is was pending.
1774 * This is not complete - we should be able to fake
1775 * an edge even if it isn't on the 8259A...
1777 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1779 int was_pending = 0;
1780 unsigned long flags;
1782 spin_lock_irqsave(&ioapic_lock, flags);
1784 disable_8259A_irq(irq);
1785 if (i8259A_irq_pending(irq))
1788 __unmask_IO_APIC_irq(irq);
1789 spin_unlock_irqrestore(&ioapic_lock, flags);
1795 * Once we have recorded IRQ_PENDING already, we can mask the
1796 * interrupt for real. This prevents IRQ storms from unhandled
1799 static void ack_edge_ioapic_irq(unsigned int irq)
1802 if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
1803 == (IRQ_PENDING | IRQ_DISABLED))
1804 mask_IO_APIC_irq(irq);
1809 * Level triggered interrupts can just be masked,
1810 * and shutting down and starting up the interrupt
1811 * is the same as enabling and disabling them -- except
1812 * with a startup need to return a "was pending" value.
1814 * Level triggered interrupts are special because we
1815 * do not touch any IO-APIC register while handling
1816 * them. We ack the APIC in the end-IRQ handler, not
1817 * in the start-IRQ-handler. Protection against reentrance
1818 * from the same interrupt is still provided, both by the
1819 * generic IRQ layer and by the fact that an unacked local
1820 * APIC does not accept IRQs.
1822 static unsigned int startup_level_ioapic_irq (unsigned int irq)
1824 unmask_IO_APIC_irq(irq);
1826 return 0; /* don't check for pending */
1829 static void end_level_ioapic_irq (unsigned int irq)
1836 * It appears there is an erratum which affects at least version 0x11
1837 * of I/O APIC (that's the 82093AA and cores integrated into various
1838 * chipsets). Under certain conditions a level-triggered interrupt is
1839 * erroneously delivered as edge-triggered one but the respective IRR
1840 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1841 * message but it will never arrive and further interrupts are blocked
1842 * from the source. The exact reason is so far unknown, but the
1843 * phenomenon was observed when two consecutive interrupt requests
1844 * from a given source get delivered to the same CPU and the source is
1845 * temporarily disabled in between.
1847 * A workaround is to simulate an EOI message manually. We achieve it
1848 * by setting the trigger mode to edge and then to level when the edge
1849 * trigger mode gets detected in the TMR of a local APIC for a
1850 * level-triggered interrupt. We mask the source for the time of the
1851 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1852 * The idea is from Manfred Spraul. --macro
1854 i = IO_APIC_VECTOR(irq);
1856 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1860 if (!(v & (1 << (i & 0x1f)))) {
1861 #ifdef APIC_MISMATCH_DEBUG
1862 atomic_inc(&irq_mis_count);
1864 spin_lock(&ioapic_lock);
1865 __mask_and_edge_IO_APIC_irq(irq);
1866 __unmask_and_level_IO_APIC_irq(irq);
1867 spin_unlock(&ioapic_lock);
1871 #ifdef CONFIG_PCI_USE_VECTOR
1872 static unsigned int startup_edge_ioapic_vector(unsigned int vector)
1874 int irq = vector_to_irq(vector);
1876 return startup_edge_ioapic_irq(irq);
1879 static void ack_edge_ioapic_vector(unsigned int vector)
1881 int irq = vector_to_irq(vector);
1883 ack_edge_ioapic_irq(irq);
1886 static unsigned int startup_level_ioapic_vector (unsigned int vector)
1888 int irq = vector_to_irq(vector);
1890 return startup_level_ioapic_irq (irq);
1893 static void end_level_ioapic_vector (unsigned int vector)
1895 int irq = vector_to_irq(vector);
1897 end_level_ioapic_irq(irq);
1900 static void mask_IO_APIC_vector (unsigned int vector)
1902 int irq = vector_to_irq(vector);
1904 mask_IO_APIC_irq(irq);
1907 static void unmask_IO_APIC_vector (unsigned int vector)
1909 int irq = vector_to_irq(vector);
1911 unmask_IO_APIC_irq(irq);
1914 static void set_ioapic_affinity_vector (unsigned int vector,
1917 int irq = vector_to_irq(vector);
1919 set_ioapic_affinity_irq(irq, cpu_mask);
1924 * Level and edge triggered IO-APIC interrupts need different handling,
1925 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1926 * handled with the level-triggered descriptor, but that one has slightly
1927 * more overhead. Level-triggered interrupts cannot be handled with the
1928 * edge-triggered handler, without risking IRQ storms and other ugly
1931 static struct hw_interrupt_type ioapic_edge_type = {
1932 .typename = "IO-APIC-edge",
1933 .startup = startup_edge_ioapic,
1934 .shutdown = shutdown_edge_ioapic,
1935 .enable = enable_edge_ioapic,
1936 .disable = disable_edge_ioapic,
1937 .ack = ack_edge_ioapic,
1938 .end = end_edge_ioapic,
1939 .set_affinity = set_ioapic_affinity,
1942 static struct hw_interrupt_type ioapic_level_type = {
1943 .typename = "IO-APIC-level",
1944 .startup = startup_level_ioapic,
1945 .shutdown = shutdown_level_ioapic,
1946 .enable = enable_level_ioapic,
1947 .disable = disable_level_ioapic,
1948 .ack = mask_and_ack_level_ioapic,
1949 .end = end_level_ioapic,
1950 .set_affinity = set_ioapic_affinity,
1953 static inline void init_IO_APIC_traps(void)
1958 * NOTE! The local APIC isn't very good at handling
1959 * multiple interrupts at the same interrupt level.
1960 * As the interrupt level is determined by taking the
1961 * vector number and shifting that right by 4, we
1962 * want to spread these out a bit so that they don't
1963 * all fall in the same interrupt level.
1965 * Also, we've got to be careful not to trash gate
1966 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1968 for (irq = 0; irq < NR_IRQS ; irq++) {
1970 if (use_pci_vector()) {
1971 if (!platform_legacy_irq(tmp))
1972 if ((tmp = vector_to_irq(tmp)) == -1)
1975 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
1977 * Hmm.. We don't have an entry for this,
1978 * so default to an old-fashioned 8259
1979 * interrupt if we can..
1982 make_8259A_irq(irq);
1984 /* Strange. Oh, well.. */
1985 irq_desc[irq].handler = &no_irq_type;
1990 static void enable_lapic_irq (unsigned int irq)
1994 v = apic_read(APIC_LVT0);
1995 apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
1998 static void disable_lapic_irq (unsigned int irq)
2002 v = apic_read(APIC_LVT0);
2003 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
2006 static void ack_lapic_irq (unsigned int irq)
2011 static void end_lapic_irq (unsigned int i) { /* nothing */ }
2013 static struct hw_interrupt_type lapic_irq_type = {
2014 .typename = "local-APIC-edge",
2015 .startup = NULL, /* startup_irq() not used for IRQ0 */
2016 .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
2017 .enable = enable_lapic_irq,
2018 .disable = disable_lapic_irq,
2019 .ack = ack_lapic_irq,
2020 .end = end_lapic_irq
2023 static void setup_nmi (void)
2026 * Dirty trick to enable the NMI watchdog ...
2027 * We put the 8259A master into AEOI mode and
2028 * unmask on all local APICs LVT0 as NMI.
2030 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2031 * is from Maciej W. Rozycki - so we do not have to EOI from
2032 * the NMI handler or the timer interrupt.
2034 printk(KERN_INFO "activating NMI Watchdog ...");
2036 on_each_cpu(enable_NMI_through_LVT0, NULL, 1, 1);
2042 * This looks a bit hackish but it's about the only one way of sending
2043 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2044 * not support the ExtINT mode, unfortunately. We need to send these
2045 * cycles as some i82489DX-based boards have glue logic that keeps the
2046 * 8259A interrupt line asserted until INTA. --macro
2048 static inline void unlock_ExtINT_logic(void)
2051 struct IO_APIC_route_entry entry0, entry1;
2052 unsigned char save_control, save_freq_select;
2053 unsigned long flags;
2055 pin = find_isa_irq_pin(8, mp_INT);
2059 spin_lock_irqsave(&ioapic_lock, flags);
2060 *(((int *)&entry0) + 1) = io_apic_read(0, 0x11 + 2 * pin);
2061 *(((int *)&entry0) + 0) = io_apic_read(0, 0x10 + 2 * pin);
2062 spin_unlock_irqrestore(&ioapic_lock, flags);
2063 clear_IO_APIC_pin(0, pin);
2065 memset(&entry1, 0, sizeof(entry1));
2067 entry1.dest_mode = 0; /* physical delivery */
2068 entry1.mask = 0; /* unmask IRQ now */
2069 entry1.dest.physical.physical_dest = hard_smp_processor_id();
2070 entry1.delivery_mode = dest_ExtINT;
2071 entry1.polarity = entry0.polarity;
2075 spin_lock_irqsave(&ioapic_lock, flags);
2076 io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
2077 io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
2078 spin_unlock_irqrestore(&ioapic_lock, flags);
2080 save_control = CMOS_READ(RTC_CONTROL);
2081 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2082 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2084 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2089 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2093 CMOS_WRITE(save_control, RTC_CONTROL);
2094 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2095 clear_IO_APIC_pin(0, pin);
2097 spin_lock_irqsave(&ioapic_lock, flags);
2098 io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
2099 io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
2100 spin_unlock_irqrestore(&ioapic_lock, flags);
2104 * This code may look a bit paranoid, but it's supposed to cooperate with
2105 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2106 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2107 * fanatically on his truly buggy board.
2109 static inline void check_timer(void)
2115 * get/set the timer IRQ vector:
2117 disable_8259A_irq(0);
2118 vector = assign_irq_vector(0);
2119 set_intr_gate(vector, interrupt[0]);
2122 * Subtle, code in do_timer_interrupt() expects an AEOI
2123 * mode for the 8259A whenever interrupts are routed
2124 * through I/O APICs. Also IRQ0 has to be enabled in
2125 * the 8259A which implies the virtual wire has to be
2126 * disabled in the local APIC.
2128 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2131 enable_8259A_irq(0);
2133 pin1 = find_isa_irq_pin(0, mp_INT);
2134 pin2 = find_isa_irq_pin(0, mp_ExtINT);
2136 printk(KERN_INFO "..TIMER: vector=0x%02X pin1=%d pin2=%d\n", vector, pin1, pin2);
2140 * Ok, does IRQ0 through the IOAPIC work?
2142 unmask_IO_APIC_irq(0);
2143 if (timer_irq_works()) {
2144 if (nmi_watchdog == NMI_IO_APIC) {
2145 disable_8259A_irq(0);
2147 enable_8259A_irq(0);
2148 check_nmi_watchdog();
2152 clear_IO_APIC_pin(0, pin1);
2153 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to IO-APIC\n");
2156 printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
2158 printk("\n..... (found pin %d) ...", pin2);
2160 * legacy devices should be connected to IO APIC #0
2162 setup_ExtINT_IRQ0_pin(pin2, vector);
2163 if (timer_irq_works()) {
2166 replace_pin_at_irq(0, 0, pin1, 0, pin2);
2168 add_pin_to_irq(0, 0, pin2);
2169 if (nmi_watchdog == NMI_IO_APIC) {
2171 check_nmi_watchdog();
2176 * Cleanup, just in case ...
2178 clear_IO_APIC_pin(0, pin2);
2180 printk(" failed.\n");
2182 if (nmi_watchdog == NMI_IO_APIC) {
2183 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2187 printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
2189 disable_8259A_irq(0);
2190 irq_desc[0].handler = &lapic_irq_type;
2191 apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
2192 enable_8259A_irq(0);
2194 if (timer_irq_works()) {
2195 printk(" works.\n");
2198 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
2199 printk(" failed.\n");
2201 printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
2206 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
2208 unlock_ExtINT_logic();
2210 if (timer_irq_works()) {
2211 printk(" works.\n");
2214 printk(" failed :(.\n");
2215 panic("IO-APIC + timer doesn't work! pester mingo@redhat.com");
2220 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2221 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2222 * Linux doesn't really care, as it's not actually used
2223 * for any interrupt handling anyway.
2225 #define PIC_IRQS (1 << PIC_CASCADE_IR)
2227 void __init setup_IO_APIC(void)
2232 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
2234 io_apic_irqs = ~PIC_IRQS;
2236 printk("ENABLING IO-APIC IRQs\n");
2239 * Set up IO-APIC IRQ routing.
2242 setup_ioapic_ids_from_mpc();
2244 setup_IO_APIC_irqs();
2245 init_IO_APIC_traps();
2252 * Called after all the initialization is done. If we didnt find any
2253 * APIC bugs then we can allow the modify fast path
2256 static int __init io_apic_bug_finalize(void)
2258 if(sis_apic_bug == -1)
2263 late_initcall(io_apic_bug_finalize);
2265 /* --------------------------------------------------------------------------
2266 ACPI-based IOAPIC Configuration
2267 -------------------------------------------------------------------------- */
2269 #ifdef CONFIG_ACPI_BOOT
2271 int __init io_apic_get_unique_id (int ioapic, int apic_id)
2273 union IO_APIC_reg_00 reg_00;
2274 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2276 unsigned long flags;
2280 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2281 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2282 * supports up to 16 on one shared APIC bus.
2284 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2285 * advantage of new APIC bus architecture.
2288 if (physids_empty(apic_id_map))
2289 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2291 spin_lock_irqsave(&ioapic_lock, flags);
2292 reg_00.raw = io_apic_read(ioapic, 0);
2293 spin_unlock_irqrestore(&ioapic_lock, flags);
2295 if (apic_id >= get_physical_broadcast()) {
2296 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2297 "%d\n", ioapic, apic_id, reg_00.bits.ID);
2298 apic_id = reg_00.bits.ID;
2302 * Every APIC in a system must have a unique ID or we get lots of nice
2303 * 'stuck on smp_invalidate_needed IPI wait' messages.
2305 if (check_apicid_used(apic_id_map, apic_id)) {
2307 for (i = 0; i < get_physical_broadcast(); i++) {
2308 if (!check_apicid_used(apic_id_map, i))
2312 if (i == get_physical_broadcast())
2313 panic("Max apic_id exceeded!\n");
2315 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2316 "trying %d\n", ioapic, apic_id, i);
2321 tmp = apicid_to_cpu_present(apic_id);
2322 physids_or(apic_id_map, apic_id_map, tmp);
2324 if (reg_00.bits.ID != apic_id) {
2325 reg_00.bits.ID = apic_id;
2327 spin_lock_irqsave(&ioapic_lock, flags);
2328 io_apic_write(ioapic, 0, reg_00.raw);
2329 reg_00.raw = io_apic_read(ioapic, 0);
2330 spin_unlock_irqrestore(&ioapic_lock, flags);
2333 if (reg_00.bits.ID != apic_id)
2334 panic("IOAPIC[%d]: Unable change apic_id!\n", ioapic);
2337 printk(KERN_INFO "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2343 int __init io_apic_get_version (int ioapic)
2345 union IO_APIC_reg_01 reg_01;
2346 unsigned long flags;
2348 spin_lock_irqsave(&ioapic_lock, flags);
2349 reg_01.raw = io_apic_read(ioapic, 1);
2350 spin_unlock_irqrestore(&ioapic_lock, flags);
2352 return reg_01.bits.version;
2356 int __init io_apic_get_redir_entries (int ioapic)
2358 union IO_APIC_reg_01 reg_01;
2359 unsigned long flags;
2361 spin_lock_irqsave(&ioapic_lock, flags);
2362 reg_01.raw = io_apic_read(ioapic, 1);
2363 spin_unlock_irqrestore(&ioapic_lock, flags);
2365 return reg_01.bits.entries;
2369 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
2371 struct IO_APIC_route_entry entry;
2372 unsigned long flags;
2374 if (!IO_APIC_IRQ(irq)) {
2375 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2381 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2382 * Note that we mask (disable) IRQs now -- these get enabled when the
2383 * corresponding device driver registers for this IRQ.
2386 memset(&entry,0,sizeof(entry));
2388 entry.delivery_mode = INT_DELIVERY_MODE;
2389 entry.dest_mode = INT_DEST_MODE;
2390 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2391 entry.trigger = edge_level;
2392 entry.polarity = active_high_low;
2396 * IRQs < 16 are already in the irq_2_pin[] map
2399 add_pin_to_irq(irq, ioapic, pin);
2401 entry.vector = assign_irq_vector(irq);
2403 Dprintk(KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> "
2404 "IRQ %d Mode:%i Active:%i)\n", ioapic,
2405 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq, edge_level, active_high_low);
2407 if (use_pci_vector() && !platform_legacy_irq(irq))
2408 irq = IO_APIC_VECTOR(irq);
2410 irq_desc[irq].handler = &ioapic_level_type;
2412 irq_desc[irq].handler = &ioapic_edge_type;
2415 set_intr_gate(entry.vector, interrupt[irq]);
2417 if (!ioapic && (irq < 16))
2418 disable_8259A_irq(irq);
2420 spin_lock_irqsave(&ioapic_lock, flags);
2421 io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
2422 io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
2423 spin_unlock_irqrestore(&ioapic_lock, flags);
2428 #endif /*CONFIG_ACPI_BOOT*/