2 * linux/arch/i386/traps.c
4 * Copyright (C) 1991, 1992 Linus Torvalds
6 * Pentium III FXSR, SSE support
7 * Gareth Hughes <gareth@valinux.com>, May 2000
11 * 'Traps.c' handles hardware traps and faults after we have saved some
14 #include <linux/config.h>
15 #include <linux/sched.h>
16 #include <linux/kernel.h>
17 #include <linux/string.h>
18 #include <linux/errno.h>
19 #include <linux/timer.h>
21 #include <linux/init.h>
22 #include <linux/delay.h>
23 #include <linux/spinlock.h>
24 #include <linux/interrupt.h>
25 #include <linux/highmem.h>
26 #include <linux/kallsyms.h>
27 #include <linux/ptrace.h>
28 #include <linux/version.h>
31 #include <linux/ioport.h>
32 #include <linux/eisa.h>
36 #include <linux/mca.h>
39 #include <asm/processor.h>
40 #include <asm/system.h>
41 #include <asm/uaccess.h>
43 #include <asm/atomic.h>
44 #include <asm/debugreg.h>
50 #include <asm/pgalloc.h>
51 #include <asm/arch_hooks.h>
53 #include <linux/irq.h>
54 #include <linux/module.h>
56 #include "mach_traps.h"
58 struct desc_struct default_ldt[] __attribute__((__section__(".data.default_ldt"))) = { { 0, 0 }, { 0, 0 }, { 0, 0 }, { 0, 0 }, { 0, 0 } };
59 struct page *default_ldt_page;
61 /* Do we ignore FPU interrupts ? */
62 char ignore_fpu_irq = 0;
65 * The IDT has to be page-aligned to simplify the Pentium
66 * F0 0F bug workaround.. We have a special link segment
69 struct desc_struct idt_table[256] __attribute__((__section__(".data.idt"))) = { {0, 0}, };
71 asmlinkage void divide_error(void);
72 asmlinkage void debug(void);
73 asmlinkage void nmi(void);
74 asmlinkage void int3(void);
75 asmlinkage void overflow(void);
76 asmlinkage void bounds(void);
77 asmlinkage void invalid_op(void);
78 asmlinkage void device_not_available(void);
79 asmlinkage void coprocessor_segment_overrun(void);
80 asmlinkage void invalid_TSS(void);
81 asmlinkage void segment_not_present(void);
82 asmlinkage void stack_segment(void);
83 asmlinkage void general_protection(void);
84 asmlinkage void page_fault(void);
85 asmlinkage void coprocessor_error(void);
86 asmlinkage void simd_coprocessor_error(void);
87 asmlinkage void alignment_check(void);
88 asmlinkage void spurious_interrupt_bug(void);
89 asmlinkage void machine_check(void);
91 static int kstack_depth_to_print = 24;
93 static int valid_stack_ptr(struct task_struct *task, void *p)
95 if (p <= (void *)task->thread_info)
102 #ifdef CONFIG_FRAME_POINTER
103 void print_context_stack(struct task_struct *task, unsigned long *stack,
108 while (valid_stack_ptr(task, (void *)ebp)) {
109 addr = *(unsigned long *)(ebp + 4);
110 printk(" [<%08lx>] ", addr);
111 print_symbol("%s", addr);
113 ebp = *(unsigned long *)ebp;
117 void print_context_stack(struct task_struct *task, unsigned long *stack,
122 while (!kstack_end(stack)) {
124 if (kernel_text_address(addr)) {
125 printk(" [<%08lx>] ", addr);
126 print_symbol("%s\n", addr);
132 void show_trace(struct task_struct *task, unsigned long * stack)
139 if (!valid_stack_ptr(task, stack)) {
140 printk("Stack pointer is garbage, not printing trace\n");
144 if (task == current) {
145 /* Grab ebp right from our regs */
146 asm ("movl %%ebp, %0" : "=r" (ebp) : );
148 /* ebp is the last reg pushed by switch_to */
149 ebp = *(unsigned long *) task->thread.esp;
153 struct thread_info *context;
154 context = (struct thread_info *)
155 ((unsigned long)stack & (~(THREAD_SIZE - 1)));
156 print_context_stack(task, stack, ebp);
157 stack = (unsigned long*)context->previous_esp;
160 printk(" =======================\n");
165 void show_stack(struct task_struct *task, unsigned long *esp)
167 unsigned long *stack;
172 esp = (unsigned long*)task->thread.esp;
174 esp = (unsigned long *)&esp;
178 for(i = 0; i < kstack_depth_to_print; i++) {
179 if (kstack_end(stack))
181 if (i && ((i % 8) == 0))
183 printk("%08lx ", *stack++);
185 printk("\nCall Trace:\n");
186 show_trace(task, esp);
190 * The architecture-independent dump_stack generator
192 void dump_stack(void)
196 show_trace(current, &stack);
199 EXPORT_SYMBOL(dump_stack);
201 void show_registers(struct pt_regs *regs)
208 esp = (unsigned long) (®s->esp);
213 ss = regs->xss & 0xffff;
216 printk("CPU: %d\nEIP: %04x:[<%08lx>] %s\nEFLAGS: %08lx"
218 smp_processor_id(), 0xffff & regs->xcs, regs->eip,
219 print_tainted(), regs->eflags, UTS_RELEASE);
220 print_symbol("EIP is at %s\n", regs->eip);
221 printk("eax: %08lx ebx: %08lx ecx: %08lx edx: %08lx\n",
222 regs->eax, regs->ebx, regs->ecx, regs->edx);
223 printk("esi: %08lx edi: %08lx ebp: %08lx esp: %08lx\n",
224 regs->esi, regs->edi, regs->ebp, esp);
225 printk("ds: %04x es: %04x ss: %04x\n",
226 regs->xds & 0xffff, regs->xes & 0xffff, ss);
227 printk("Process %s (pid: %d, threadinfo=%p task=%p)",
228 current->comm, current->pid, current_thread_info(), current);
230 * When in-kernel, we also print out the stack and code at the
231 * time of the fault..
236 show_stack(NULL, (unsigned long*)esp);
239 if(regs->eip < PAGE_OFFSET)
245 if ((user_mode(regs) && get_user(c, &((unsigned char*)regs->eip)[i])) ||
246 (!user_mode(regs) && __direct_get_user(c, &((unsigned char*)regs->eip)[i]))) {
249 printk(" Bad EIP value.");
258 static void handle_BUG(struct pt_regs *regs)
267 goto no_bug; /* Not in kernel */
271 if (__direct_get_user(ud2, (unsigned short *)eip))
275 if (__direct_get_user(line, (unsigned short *)(eip + 2)))
277 if (__direct_get_user(file, (char **)(eip + 4)) ||
278 __direct_get_user(c, file))
279 file = "<bad filename>";
281 printk("------------[ cut here ]------------\n");
282 printk("kernel BUG at %s:%d!\n", file, line);
287 /* Here we know it was a BUG but file-n-line is unavailable */
289 printk("Kernel BUG\n");
292 spinlock_t die_lock = SPIN_LOCK_UNLOCKED;
294 void die(const char * str, struct pt_regs * regs, long err)
296 static int die_counter;
300 spin_lock_irq(&die_lock);
303 printk("%s: %04lx [#%d]\n", str, err & 0xffff, ++die_counter);
304 #ifdef CONFIG_PREEMPT
312 #ifdef CONFIG_DEBUG_PAGEALLOC
313 printk("DEBUG_PAGEALLOC");
318 show_registers(regs);
320 spin_unlock_irq(&die_lock);
322 panic("Fatal exception in interrupt");
325 printk(KERN_EMERG "Fatal exception: panic in 5 seconds\n");
326 set_current_state(TASK_UNINTERRUPTIBLE);
327 schedule_timeout(5 * HZ);
328 panic("Fatal exception");
333 static inline void die_if_kernel(const char * str, struct pt_regs * regs, long err)
335 if (!(regs->eflags & VM_MASK) && !(3 & regs->xcs))
339 static inline unsigned long get_cr2(void)
341 unsigned long address;
343 /* get the address */
344 __asm__("movl %%cr2,%0":"=r" (address));
348 static inline void do_trap(int trapnr, int signr, char *str, int vm86,
349 struct pt_regs * regs, long error_code, siginfo_t *info)
351 if (regs->eflags & VM_MASK) {
357 if (!(regs->xcs & 3))
361 struct task_struct *tsk = current;
362 tsk->thread.error_code = error_code;
363 tsk->thread.trap_no = trapnr;
365 force_sig_info(signr, info, tsk);
367 force_sig(signr, tsk);
372 if (!fixup_exception(regs))
373 die(str, regs, error_code);
378 int ret = handle_vm86_trap((struct kernel_vm86_regs *) regs, error_code, trapnr);
379 if (ret) goto trap_signal;
384 #define DO_ERROR(trapnr, signr, str, name) \
385 asmlinkage void do_##name(struct pt_regs * regs, long error_code) \
387 do_trap(trapnr, signr, str, 0, regs, error_code, NULL); \
390 #define DO_ERROR_INFO(trapnr, signr, str, name, sicode, siaddr) \
391 asmlinkage void do_##name(struct pt_regs * regs, long error_code) \
394 info.si_signo = signr; \
396 info.si_code = sicode; \
397 info.si_addr = (void *)siaddr; \
398 do_trap(trapnr, signr, str, 0, regs, error_code, &info); \
401 #define DO_VM86_ERROR(trapnr, signr, str, name) \
402 asmlinkage void do_##name(struct pt_regs * regs, long error_code) \
404 do_trap(trapnr, signr, str, 1, regs, error_code, NULL); \
407 #define DO_VM86_ERROR_INFO(trapnr, signr, str, name, sicode, siaddr) \
408 asmlinkage void do_##name(struct pt_regs * regs, long error_code) \
411 info.si_signo = signr; \
413 info.si_code = sicode; \
414 info.si_addr = (void *)siaddr; \
415 do_trap(trapnr, signr, str, 1, regs, error_code, &info); \
418 DO_VM86_ERROR_INFO( 0, SIGFPE, "divide error", divide_error, FPE_INTDIV, regs->eip)
419 DO_VM86_ERROR( 3, SIGTRAP, "int3", int3)
420 DO_VM86_ERROR( 4, SIGSEGV, "overflow", overflow)
421 DO_VM86_ERROR( 5, SIGSEGV, "bounds", bounds)
422 DO_ERROR_INFO( 6, SIGILL, "invalid operand", invalid_op, ILL_ILLOPN, regs->eip)
423 DO_ERROR( 9, SIGFPE, "coprocessor segment overrun", coprocessor_segment_overrun)
424 DO_ERROR(10, SIGSEGV, "invalid TSS", invalid_TSS)
425 DO_ERROR(11, SIGBUS, "segment not present", segment_not_present)
426 DO_ERROR(12, SIGBUS, "stack segment", stack_segment)
427 DO_ERROR_INFO(17, SIGBUS, "alignment check", alignment_check, BUS_ADRALN, get_cr2())
430 * the original non-exec stack patch was written by
431 * Solar Designer <solar at openwall.com>. Thanks!
433 asmlinkage void do_general_protection(struct pt_regs * regs, long error_code)
435 if (regs->eflags & X86_EFLAGS_IF)
438 if (regs->eflags & VM_MASK)
441 if (!(regs->xcs & 3))
445 * lazy-check for CS validity on exec-shield binaries:
448 int cpu = smp_processor_id();
449 struct desc_struct *desc1, *desc2;
450 struct vm_area_struct *vma;
451 unsigned long limit = 0;
453 spin_lock(¤t->mm->page_table_lock);
454 for (vma = current->mm->mmap; vma; vma = vma->vm_next)
455 if ((vma->vm_flags & VM_EXEC) && (vma->vm_end > limit))
457 spin_unlock(¤t->mm->page_table_lock);
459 current->mm->context.exec_limit = limit;
460 set_user_cs(¤t->mm->context.user_cs, limit);
462 desc1 = ¤t->mm->context.user_cs;
463 desc2 = cpu_gdt_table[cpu] + GDT_ENTRY_DEFAULT_USER_CS;
466 * The CS was not in sync - reload it and retry the
467 * instruction. If the instruction still faults then
468 * we wont hit this branch next time around.
470 if (desc1->a != desc2->a || desc1->b != desc2->b) {
471 if (print_fatal_signals >= 2) {
472 printk("#GPF fixup (%ld[seg:%lx]) at %08lx, CPU#%d.\n", error_code, error_code/8, regs->eip, smp_processor_id());
473 printk(" exec_limit: %08lx, user_cs: %08lx/%08lx, CPU_cs: %08lx/%08lx.\n", current->mm->context.exec_limit, desc1->a, desc1->b, desc2->a, desc2->b);
475 load_user_cs_desc(cpu, current->mm);
479 if (print_fatal_signals) {
480 printk("#GPF(%ld[seg:%lx]) at %08lx, CPU#%d.\n", error_code, error_code/8, regs->eip, smp_processor_id());
481 printk(" exec_limit: %08lx, user_cs: %08lx/%08lx.\n", current->mm->context.exec_limit, current->mm->context.user_cs.a, current->mm->context.user_cs.b);
484 current->thread.error_code = error_code;
485 current->thread.trap_no = 13;
486 force_sig(SIGSEGV, current);
491 handle_vm86_fault((struct kernel_vm86_regs *) regs, error_code);
495 if (!fixup_exception(regs))
496 die("general protection fault", regs, error_code);
499 static void mem_parity_error(unsigned char reason, struct pt_regs * regs)
501 printk("Uhhuh. NMI received. Dazed and confused, but trying to continue\n");
502 printk("You probably have a hardware problem with your RAM chips\n");
504 /* Clear and disable the memory parity error line. */
505 clear_mem_error(reason);
508 static void io_check_error(unsigned char reason, struct pt_regs * regs)
512 printk("NMI: IOCK error (debug interrupt?)\n");
513 show_registers(regs);
515 /* Re-enable the IOCK line, wait for a few seconds */
516 reason = (reason & 0xf) | 8;
519 while (--i) udelay(1000);
524 static void unknown_nmi_error(unsigned char reason, struct pt_regs * regs)
527 /* Might actually be able to figure out what the guilty party
534 printk("Uhhuh. NMI received for unknown reason %02x on CPU %d.\n",
535 reason, smp_processor_id());
536 printk("Dazed and confused, but trying to continue\n");
537 printk("Do you have a strange power saving mode enabled?\n");
540 static void default_do_nmi(struct pt_regs * regs)
542 unsigned char reason = get_nmi_reason();
544 if (!(reason & 0xc0)) {
545 #ifdef CONFIG_X86_LOCAL_APIC
547 * Ok, so this is none of the documented NMI sources,
548 * so it must be the NMI watchdog.
551 nmi_watchdog_tick(regs);
555 unknown_nmi_error(reason, regs);
559 mem_parity_error(reason, regs);
561 io_check_error(reason, regs);
563 * Reassert NMI in case it became active meanwhile
564 * as it's edge-triggered.
569 static int dummy_nmi_callback(struct pt_regs * regs, int cpu)
574 static nmi_callback_t nmi_callback = dummy_nmi_callback;
576 asmlinkage void do_nmi(struct pt_regs * regs, long error_code)
582 cpu = smp_processor_id();
585 if (!nmi_callback(regs, cpu))
586 default_do_nmi(regs);
591 void set_nmi_callback(nmi_callback_t callback)
593 nmi_callback = callback;
596 void unset_nmi_callback(void)
598 nmi_callback = dummy_nmi_callback;
602 * Our handling of the processor debug registers is non-trivial.
603 * We do not clear them on entry and exit from the kernel. Therefore
604 * it is possible to get a watchpoint trap here from inside the kernel.
605 * However, the code in ./ptrace.c has ensured that the user can
606 * only set watchpoints on userspace addresses. Therefore the in-kernel
607 * watchpoint trap can only occur in code which is reading/writing
608 * from user space. Such code must not hold kernel locks (since it
609 * can equally take a page fault), therefore it is safe to call
610 * force_sig_info even though that claims and releases locks.
612 * Code in ./signal.c ensures that the debug control register
613 * is restored before we deliver any signal, and therefore that
614 * user code runs with the correct debug control register even though
617 * Being careful here means that we don't have to be as careful in a
618 * lot of more complicated places (task switching can be a bit lazy
619 * about restoring all the debug state, and ptrace doesn't have to
620 * find every occurrence of the TF bit that could be saved away even
623 asmlinkage void do_debug(struct pt_regs * regs, long error_code)
625 unsigned int condition;
626 struct task_struct *tsk = current;
629 __asm__ __volatile__("movl %%db6,%0" : "=r" (condition));
631 /* It's safe to allow irq's after DR6 has been saved */
632 if (regs->eflags & X86_EFLAGS_IF)
636 * Mask out spurious debug traps due to lazy DR7 setting or
637 * due to 4G/4G kernel mode:
639 if (condition & (DR_TRAP0|DR_TRAP1|DR_TRAP2|DR_TRAP3)) {
640 if (!tsk->thread.debugreg[7])
642 if (!user_mode(regs)) {
643 // restore upon return-to-userspace:
644 set_thread_flag(TIF_DB7);
649 if (regs->eflags & VM_MASK)
652 /* Save debug status register where ptrace can see it */
653 tsk->thread.debugreg[6] = condition;
655 /* Mask out spurious TF errors due to lazy TF clearing */
656 if (condition & DR_STEP) {
658 * The TF error should be masked out only if the current
659 * process is not traced and if the TRAP flag has been set
660 * previously by a tracing process (condition detected by
661 * the PT_DTRACE flag); remember that the i386 TRAP flag
662 * can be modified by the process itself in user mode,
663 * allowing programs to debug themselves without the ptrace()
666 if ((regs->xcs & 3) == 0)
667 goto clear_TF_reenable;
668 if ((tsk->ptrace & (PT_DTRACE|PT_PTRACED)) == PT_DTRACE)
672 /* Ok, finally something we can handle */
673 tsk->thread.trap_no = 1;
674 tsk->thread.error_code = error_code;
675 info.si_signo = SIGTRAP;
677 info.si_code = TRAP_BRKPT;
679 /* If this is a kernel mode trap, save the user PC on entry to
680 * the kernel, that's what the debugger can make sense of.
682 info.si_addr = ((regs->xcs & 3) == 0) ? (void *)tsk->thread.eip :
684 force_sig_info(SIGTRAP, &info, tsk);
686 /* Disable additional traps. They'll be re-enabled when
687 * the signal is delivered.
690 __asm__("movl %0,%%db7"
696 handle_vm86_trap((struct kernel_vm86_regs *) regs, error_code, 1);
700 set_tsk_thread_flag(tsk, TIF_SINGLESTEP);
702 regs->eflags &= ~TF_MASK;
707 * Note that we play around with the 'TS' bit in an attempt to get
708 * the correct behaviour even in the presence of the asynchronous
711 void math_error(void *eip)
713 struct task_struct * task;
715 unsigned short cwd, swd;
718 * Save the info for the exception handler and clear the error.
722 task->thread.trap_no = 16;
723 task->thread.error_code = 0;
724 info.si_signo = SIGFPE;
726 info.si_code = __SI_FAULT;
729 * (~cwd & swd) will mask out exceptions that are not set to unmasked
730 * status. 0x3f is the exception bits in these regs, 0x200 is the
731 * C1 reg you need in case of a stack fault, 0x040 is the stack
732 * fault bit. We should only be taking one exception at a time,
733 * so if this combination doesn't produce any single exception,
734 * then we have a bad program that isn't syncronizing its FPU usage
735 * and it will suffer the consequences since we won't be able to
736 * fully reproduce the context of the exception
738 cwd = get_fpu_cwd(task);
739 swd = get_fpu_swd(task);
740 switch (((~cwd) & swd & 0x3f) | (swd & 0x240)) {
744 case 0x001: /* Invalid Op */
745 case 0x041: /* Stack Fault */
746 case 0x241: /* Stack Fault | Direction */
747 info.si_code = FPE_FLTINV;
748 /* Should we clear the SF or let user space do it ???? */
750 case 0x002: /* Denormalize */
751 case 0x010: /* Underflow */
752 info.si_code = FPE_FLTUND;
754 case 0x004: /* Zero Divide */
755 info.si_code = FPE_FLTDIV;
757 case 0x008: /* Overflow */
758 info.si_code = FPE_FLTOVF;
760 case 0x020: /* Precision */
761 info.si_code = FPE_FLTRES;
764 force_sig_info(SIGFPE, &info, task);
767 asmlinkage void do_coprocessor_error(struct pt_regs * regs, long error_code)
770 math_error((void *)regs->eip);
773 void simd_math_error(void *eip)
775 struct task_struct * task;
777 unsigned short mxcsr;
780 * Save the info for the exception handler and clear the error.
784 task->thread.trap_no = 19;
785 task->thread.error_code = 0;
786 info.si_signo = SIGFPE;
788 info.si_code = __SI_FAULT;
791 * The SIMD FPU exceptions are handled a little differently, as there
792 * is only a single status/control register. Thus, to determine which
793 * unmasked exception was caught we must mask the exception mask bits
794 * at 0x1f80, and then use these to mask the exception bits at 0x3f.
796 mxcsr = get_fpu_mxcsr(task);
797 switch (~((mxcsr & 0x1f80) >> 7) & (mxcsr & 0x3f)) {
801 case 0x001: /* Invalid Op */
802 info.si_code = FPE_FLTINV;
804 case 0x002: /* Denormalize */
805 case 0x010: /* Underflow */
806 info.si_code = FPE_FLTUND;
808 case 0x004: /* Zero Divide */
809 info.si_code = FPE_FLTDIV;
811 case 0x008: /* Overflow */
812 info.si_code = FPE_FLTOVF;
814 case 0x020: /* Precision */
815 info.si_code = FPE_FLTRES;
818 force_sig_info(SIGFPE, &info, task);
821 asmlinkage void do_simd_coprocessor_error(struct pt_regs * regs,
825 /* Handle SIMD FPU exceptions on PIII+ processors. */
827 simd_math_error((void *)regs->eip);
830 * Handle strange cache flush from user space exception
831 * in all other cases. This is undocumented behaviour.
833 if (regs->eflags & VM_MASK) {
834 handle_vm86_fault((struct kernel_vm86_regs *)regs,
838 die_if_kernel("cache flush denied", regs, error_code);
839 current->thread.trap_no = 19;
840 current->thread.error_code = error_code;
841 force_sig(SIGSEGV, current);
845 asmlinkage void do_spurious_interrupt_bug(struct pt_regs * regs,
849 /* No need to warn about this any longer. */
850 printk("Ignoring P6 Local APIC Spurious Interrupt Bug...\n");
855 * 'math_state_restore()' saves the current math information in the
856 * old math state array, and gets the new ones from the current task
858 * Careful.. There are problems with IBM-designed IRQ13 behaviour.
859 * Don't touch unless you *really* know how it works.
861 * Must be called with kernel preemption disabled (in this case,
862 * local interrupts are disabled at the call-site in entry.S).
864 asmlinkage void math_state_restore(struct pt_regs regs)
866 struct thread_info *thread = current_thread_info();
867 struct task_struct *tsk = thread->task;
869 clts(); /* Allow maths ops (or we recurse) */
873 thread->status |= TS_USEDFPU; /* So we fnsave on switch_to() */
876 #ifndef CONFIG_MATH_EMULATION
878 asmlinkage void math_emulate(long arg)
880 printk("math-emulation not enabled and no coprocessor found.\n");
881 printk("killing %s.\n",current->comm);
882 force_sig(SIGFPE,current);
886 #endif /* CONFIG_MATH_EMULATION */
888 void __init trap_init_virtual_IDT(void)
891 * "idt" is magic - it overlaps the idt_descr
892 * variable so that updating idt will automatically
893 * update the idt descriptor..
895 __set_fixmap(FIX_IDT, __pa(&idt_table), PAGE_KERNEL_RO);
896 idt_descr.address = __fix_to_virt(FIX_IDT);
898 __asm__ __volatile__("lidt %0" : : "m" (idt_descr));
901 void __init trap_init_virtual_GDT(void)
903 int cpu = smp_processor_id();
904 struct Xgt_desc_struct *gdt_desc = cpu_gdt_descr + cpu;
905 struct Xgt_desc_struct tmp_desc = {0, 0};
906 struct tss_struct * t;
908 __asm__ __volatile__("sgdt %0": "=m" (tmp_desc): :"memory");
910 #ifdef CONFIG_X86_HIGH_ENTRY
912 __set_fixmap(FIX_GDT_0, __pa(cpu_gdt_table), PAGE_KERNEL);
913 __set_fixmap(FIX_GDT_1, __pa(cpu_gdt_table) + PAGE_SIZE, PAGE_KERNEL);
914 __set_fixmap(FIX_TSS_0, __pa(init_tss), PAGE_KERNEL);
915 __set_fixmap(FIX_TSS_1, __pa(init_tss) + 1*PAGE_SIZE, PAGE_KERNEL);
916 __set_fixmap(FIX_TSS_2, __pa(init_tss) + 2*PAGE_SIZE, PAGE_KERNEL);
917 __set_fixmap(FIX_TSS_3, __pa(init_tss) + 3*PAGE_SIZE, PAGE_KERNEL);
920 gdt_desc->address = __fix_to_virt(FIX_GDT_0) + sizeof(cpu_gdt_table[0]) * cpu;
922 gdt_desc->address = (unsigned long)cpu_gdt_table[cpu];
924 __asm__ __volatile__("lgdt %0": "=m" (*gdt_desc));
926 #ifdef CONFIG_X86_HIGH_ENTRY
927 t = (struct tss_struct *) __fix_to_virt(FIX_TSS_0) + cpu;
931 set_tss_desc(cpu, t);
932 cpu_gdt_table[cpu][GDT_ENTRY_TSS].b &= 0xfffffdff;
936 #define _set_gate(gate_addr,type,dpl,addr,seg) \
939 __asm__ __volatile__ ("movw %%dx,%%ax\n\t" \
941 "movl %%eax,%0\n\t" \
943 :"=m" (*((long *) (gate_addr))), \
944 "=m" (*(1+(long *) (gate_addr))), "=&a" (__d0), "=&d" (__d1) \
945 :"i" ((short) (0x8000+(dpl<<13)+(type<<8))), \
946 "3" ((char *) (addr)),"2" ((seg) << 16)); \
951 * This needs to use 'idt_table' rather than 'idt', and
952 * thus use the _nonmapped_ version of the IDT, as the
953 * Pentium F0 0F bugfix can have resulted in the mapped
954 * IDT being write-protected.
956 void set_intr_gate(unsigned int n, void *addr)
958 _set_gate(idt_table+n,14,0,addr,__KERNEL_CS);
961 void __init set_trap_gate(unsigned int n, void *addr)
963 _set_gate(idt_table+n,15,0,addr,__KERNEL_CS);
966 void __init set_system_gate(unsigned int n, void *addr)
968 _set_gate(idt_table+n,15,3,addr,__KERNEL_CS);
971 void __init set_call_gate(void *a, void *addr)
973 _set_gate(a,12,3,addr,__KERNEL_CS);
976 static void __init set_task_gate(unsigned int n, unsigned int gdt_entry)
978 _set_gate(idt_table+n,5,0,0,(gdt_entry<<3));
982 void __init trap_init(void)
985 if (isa_readl(0x0FFFD9) == 'E'+('I'<<8)+('S'<<16)+('A'<<24)) {
990 #ifdef CONFIG_X86_LOCAL_APIC
991 init_apic_mappings();
993 init_entry_mappings();
995 set_trap_gate(0,÷_error);
996 set_intr_gate(1,&debug);
997 set_intr_gate(2,&nmi);
998 set_system_gate(3,&int3); /* int3-5 can be called from all */
999 set_system_gate(4,&overflow);
1000 set_system_gate(5,&bounds);
1001 set_trap_gate(6,&invalid_op);
1002 set_trap_gate(7,&device_not_available);
1003 set_task_gate(8,GDT_ENTRY_DOUBLEFAULT_TSS);
1004 set_trap_gate(9,&coprocessor_segment_overrun);
1005 set_trap_gate(10,&invalid_TSS);
1006 set_trap_gate(11,&segment_not_present);
1007 set_trap_gate(12,&stack_segment);
1008 set_trap_gate(13,&general_protection);
1009 set_intr_gate(14,&page_fault);
1010 set_trap_gate(15,&spurious_interrupt_bug);
1011 set_trap_gate(16,&coprocessor_error);
1012 set_trap_gate(17,&alignment_check);
1013 #ifdef CONFIG_X86_MCE
1014 set_trap_gate(18,&machine_check);
1016 set_trap_gate(19,&simd_coprocessor_error);
1018 set_system_gate(SYSCALL_VECTOR,&system_call);
1021 * default LDT is a single-entry callgate to lcall7 for iBCS
1022 * and a callgate to lcall27 for Solaris/x86 binaries
1025 set_call_gate(&default_ldt[0],lcall7);
1026 set_call_gate(&default_ldt[4],lcall27);
1029 * Should be a barrier for any external CPU state.