2 ** IA64 System Bus Adapter (SBA) I/O MMU manager
4 ** (c) Copyright 2002-2004 Alex Williamson
5 ** (c) Copyright 2002-2003 Grant Grundler
6 ** (c) Copyright 2002-2004 Hewlett-Packard Company
8 ** Portions (c) 2000 Grant Grundler (from parisc I/O MMU code)
9 ** Portions (c) 1999 Dave S. Miller (from sparc64 I/O MMU code)
11 ** This program is free software; you can redistribute it and/or modify
12 ** it under the terms of the GNU General Public License as published by
13 ** the Free Software Foundation; either version 2 of the License, or
14 ** (at your option) any later version.
17 ** This module initializes the IOC (I/O Controller) found on HP
18 ** McKinley machines and their successors.
22 #include <linux/config.h>
23 #include <linux/types.h>
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/spinlock.h>
27 #include <linux/slab.h>
28 #include <linux/init.h>
30 #include <linux/string.h>
31 #include <linux/pci.h>
32 #include <linux/proc_fs.h>
33 #include <linux/seq_file.h>
34 #include <linux/acpi.h>
35 #include <linux/efi.h>
37 #include <asm/delay.h> /* ia64_get_itc() */
39 #include <asm/page.h> /* PAGE_OFFSET */
41 #include <asm/system.h> /* wmb() */
42 #include <asm/bitops.h> /* hweight64() */
44 #include <asm/acpi-ext.h>
49 ** Enabling timing search of the pdir resource map. Output in /proc.
50 ** Disabled by default to optimize performance.
52 #undef PDIR_SEARCH_TIMING
55 ** This option allows cards capable of 64bit DMA to bypass the IOMMU. If
56 ** not defined, all DMA will be 32bit and go through the TLB.
57 ** There's potentially a conflict in the bio merge code with us
58 ** advertising an iommu, but then bypassing it. Since I/O MMU bypassing
59 ** appears to give more performance than bio-level virtual merging, we'll
60 ** do the former for now. NOTE: BYPASS_SG also needs to be undef'd to
61 ** completely restrict DMA to the IOMMU.
63 #define ALLOW_IOV_BYPASS
66 ** This option specifically allows/disallows bypassing scatterlists with
67 ** multiple entries. Coalescing these entries can allow better DMA streaming
68 ** and in some cases shows better performance than entirely bypassing the
69 ** IOMMU. Performance increase on the order of 1-2% sequential output/input
70 ** using bonnie++ on a RAID0 MD device (sym2 & mpt).
72 #undef ALLOW_IOV_BYPASS_SG
75 ** If a device prefetches beyond the end of a valid pdir entry, it will cause
76 ** a hard failure, ie. MCA. Version 3.0 and later of the zx1 LBA should
77 ** disconnect on 4k boundaries and prevent such issues. If the device is
78 ** particularly agressive, this option will keep the entire pdir valid such
79 ** that prefetching will hit a valid address. This could severely impact
80 ** error containment, and is therefore off by default. The page that is
81 ** used for spill-over is poisoned, so that should help debugging somewhat.
83 #undef FULL_VALID_PDIR
85 #define ENABLE_MARK_CLEAN
88 ** The number of debug flags is a clue - this code is fragile. NOTE: since
89 ** tightening the use of res_lock the resource bitmap and actual pdir are no
90 ** longer guaranteed to stay in sync. The sanity checking code isn't going to
95 #undef DEBUG_SBA_RUN_SG
96 #undef DEBUG_SBA_RESOURCE
97 #undef ASSERT_PDIR_SANITY
98 #undef DEBUG_LARGE_SG_ENTRIES
101 #if defined(FULL_VALID_PDIR) && defined(ASSERT_PDIR_SANITY)
102 #error FULL_VALID_PDIR and ASSERT_PDIR_SANITY are mutually exclusive
105 #define SBA_INLINE __inline__
106 /* #define SBA_INLINE */
108 #ifdef DEBUG_SBA_INIT
109 #define DBG_INIT(x...) printk(x)
111 #define DBG_INIT(x...)
115 #define DBG_RUN(x...) printk(x)
117 #define DBG_RUN(x...)
120 #ifdef DEBUG_SBA_RUN_SG
121 #define DBG_RUN_SG(x...) printk(x)
123 #define DBG_RUN_SG(x...)
127 #ifdef DEBUG_SBA_RESOURCE
128 #define DBG_RES(x...) printk(x)
130 #define DBG_RES(x...)
134 #define DBG_BYPASS(x...) printk(x)
136 #define DBG_BYPASS(x...)
139 #ifdef ASSERT_PDIR_SANITY
140 #define ASSERT(expr) \
142 printk( "\n" __FILE__ ":%d: Assertion " #expr " failed!\n",__LINE__); \
150 ** The number of pdir entries to "free" before issuing
151 ** a read to PCOM register to flush out PCOM writes.
152 ** Interacts with allocation granularity (ie 4 or 8 entries
153 ** allocated and free'd/purged at a time might make this
154 ** less interesting).
156 #define DELAYED_RESOURCE_CNT 64
158 #define ZX1_IOC_ID ((PCI_DEVICE_ID_HP_ZX1_IOC << 16) | PCI_VENDOR_ID_HP)
159 #define REO_IOC_ID ((PCI_DEVICE_ID_HP_REO_IOC << 16) | PCI_VENDOR_ID_HP)
160 #define SX1000_IOC_ID ((PCI_DEVICE_ID_HP_SX1000_IOC << 16) | PCI_VENDOR_ID_HP)
162 #define ZX1_IOC_OFFSET 0x1000 /* ACPI reports SBA, we want IOC */
164 #define IOC_FUNC_ID 0x000
165 #define IOC_FCLASS 0x008 /* function class, bist, header, rev... */
166 #define IOC_IBASE 0x300 /* IO TLB */
167 #define IOC_IMASK 0x308
168 #define IOC_PCOM 0x310
169 #define IOC_TCNFG 0x318
170 #define IOC_PDIR_BASE 0x320
172 #define IOC_ROPE0_CFG 0x500
173 #define IOC_ROPE_AO 0x10 /* Allow "Relaxed Ordering" */
176 /* AGP GART driver looks for this */
177 #define ZX1_SBA_IOMMU_COOKIE 0x0000badbadc0ffeeUL
180 ** The zx1 IOC supports 4/8/16/64KB page sizes (see TCNFG register)
182 ** Some IOCs (sx1000) can run at the above pages sizes, but are
183 ** really only supported using the IOC at a 4k page size.
185 ** iovp_size could only be greater than PAGE_SIZE if we are
186 ** confident the drivers really only touch the next physical
187 ** page iff that driver instance owns it.
189 static unsigned long iovp_size;
190 static unsigned long iovp_shift;
191 static unsigned long iovp_mask;
194 void *ioc_hpa; /* I/O MMU base address */
195 char *res_map; /* resource map, bit == pdir entry */
196 u64 *pdir_base; /* physical base address */
197 unsigned long ibase; /* pdir IOV Space base */
198 unsigned long imask; /* pdir IOV Space mask */
200 unsigned long *res_hint; /* next avail IOVP - circular search */
201 unsigned long dma_mask;
202 spinlock_t res_lock; /* protects the resource bitmap, but must be held when */
203 /* clearing pdir to prevent races with allocations. */
204 unsigned int res_bitshift; /* from the RIGHT! */
205 unsigned int res_size; /* size of resource map in bytes */
206 #if DELAYED_RESOURCE_CNT > 0
207 spinlock_t saved_lock; /* may want to try to get this on a separate cacheline */
208 /* than res_lock for bigger systems. */
210 struct sba_dma_pair {
213 } saved[DELAYED_RESOURCE_CNT];
216 #ifdef PDIR_SEARCH_TIMING
217 #define SBA_SEARCH_SAMPLE 0x100
218 unsigned long avg_search[SBA_SEARCH_SAMPLE];
219 unsigned long avg_idx; /* current index into avg_search */
222 /* Stuff we don't need in performance path */
223 struct ioc *next; /* list of IOC's in system */
224 acpi_handle handle; /* for multiple IOC's */
226 unsigned int func_id;
227 unsigned int rev; /* HW revision of chip */
229 unsigned int pdir_size; /* in bytes, determined by IOV Space size */
230 struct pci_dev *sac_only_dev;
233 static struct ioc *ioc_list;
234 static int reserve_sba_gart = 1;
236 static SBA_INLINE void sba_mark_invalid(struct ioc *, dma_addr_t, size_t);
237 static SBA_INLINE void sba_free_range(struct ioc *, dma_addr_t, size_t);
239 #define sba_sg_address(sg) (page_address((sg)->page) + (sg)->offset)
241 #ifdef FULL_VALID_PDIR
242 static u64 prefetch_spill_page;
246 # define GET_IOC(dev) (((dev)->bus == &pci_bus_type) \
247 ? ((struct ioc *) PCI_CONTROLLER(to_pci_dev(dev))->iommu) : NULL)
249 # define GET_IOC(dev) NULL
253 ** DMA_CHUNK_SIZE is used by the SCSI mid-layer to break up
254 ** (or rather not merge) DMA's into managable chunks.
255 ** On parisc, this is more of the software/tuning constraint
256 ** rather than the HW. I/O MMU allocation alogorithms can be
257 ** faster with smaller size is (to some degree).
259 #define DMA_CHUNK_SIZE (BITS_PER_LONG*iovp_size)
261 #define ROUNDUP(x,y) ((x + ((y)-1)) & ~((y)-1))
263 /************************************
264 ** SBA register read and write support
266 ** BE WARNED: register writes are posted.
267 ** (ie follow writes which must reach HW with a read)
270 #define READ_REG(addr) __raw_readq(addr)
271 #define WRITE_REG(val, addr) __raw_writeq(val, addr)
273 #ifdef DEBUG_SBA_INIT
276 * sba_dump_tlb - debugging only - print IOMMU operating parameters
277 * @hpa: base address of the IOMMU
279 * Print the size/location of the IO MMU PDIR.
282 sba_dump_tlb(char *hpa)
284 DBG_INIT("IO TLB at 0x%p\n", (void *)hpa);
285 DBG_INIT("IOC_IBASE : %016lx\n", READ_REG(hpa+IOC_IBASE));
286 DBG_INIT("IOC_IMASK : %016lx\n", READ_REG(hpa+IOC_IMASK));
287 DBG_INIT("IOC_TCNFG : %016lx\n", READ_REG(hpa+IOC_TCNFG));
288 DBG_INIT("IOC_PDIR_BASE: %016lx\n", READ_REG(hpa+IOC_PDIR_BASE));
294 #ifdef ASSERT_PDIR_SANITY
297 * sba_dump_pdir_entry - debugging only - print one IOMMU PDIR entry
298 * @ioc: IO MMU structure which owns the pdir we are interested in.
299 * @msg: text to print ont the output line.
302 * Print one entry of the IO MMU PDIR in human readable form.
305 sba_dump_pdir_entry(struct ioc *ioc, char *msg, uint pide)
307 /* start printing from lowest pde in rval */
308 u64 *ptr = &ioc->pdir_base[pide & ~(BITS_PER_LONG - 1)];
309 unsigned long *rptr = (unsigned long *) &ioc->res_map[(pide >>3) & -sizeof(unsigned long)];
312 printk(KERN_DEBUG "SBA: %s rp %p bit %d rval 0x%lx\n",
313 msg, rptr, pide & (BITS_PER_LONG - 1), *rptr);
316 while (rcnt < BITS_PER_LONG) {
317 printk(KERN_DEBUG "%s %2d %p %016Lx\n",
318 (rcnt == (pide & (BITS_PER_LONG - 1)))
320 rcnt, ptr, (unsigned long long) *ptr );
324 printk(KERN_DEBUG "%s", msg);
329 * sba_check_pdir - debugging only - consistency checker
330 * @ioc: IO MMU structure which owns the pdir we are interested in.
331 * @msg: text to print ont the output line.
333 * Verify the resource map and pdir state is consistent
336 sba_check_pdir(struct ioc *ioc, char *msg)
338 u64 *rptr_end = (u64 *) &(ioc->res_map[ioc->res_size]);
339 u64 *rptr = (u64 *) ioc->res_map; /* resource map ptr */
340 u64 *pptr = ioc->pdir_base; /* pdir ptr */
343 while (rptr < rptr_end) {
345 int rcnt; /* number of bits we might check */
351 /* Get last byte and highest bit from that */
352 u32 pde = ((u32)((*pptr >> (63)) & 0x1));
353 if ((rval & 0x1) ^ pde)
356 ** BUMMER! -- res_map != pdir --
357 ** Dump rval and matching pdir entries
359 sba_dump_pdir_entry(ioc, msg, pide);
363 rval >>= 1; /* try the next bit */
367 rptr++; /* look at next word of res_map */
369 /* It'd be nice if we always got here :^) */
375 * sba_dump_sg - debugging only - print Scatter-Gather list
376 * @ioc: IO MMU structure which owns the pdir we are interested in.
377 * @startsg: head of the SG list
378 * @nents: number of entries in SG list
380 * print the SG list so we can verify it's correct by hand.
383 sba_dump_sg( struct ioc *ioc, struct scatterlist *startsg, int nents)
385 while (nents-- > 0) {
386 printk(KERN_DEBUG " %d : DMA %08lx/%05x CPU %p\n", nents,
387 startsg->dma_address, startsg->dma_length,
388 sba_sg_address(startsg));
394 sba_check_sg( struct ioc *ioc, struct scatterlist *startsg, int nents)
396 struct scatterlist *the_sg = startsg;
397 int the_nents = nents;
399 while (the_nents-- > 0) {
400 if (sba_sg_address(the_sg) == 0x0UL)
401 sba_dump_sg(NULL, startsg, nents);
406 #endif /* ASSERT_PDIR_SANITY */
411 /**************************************************************
413 * I/O Pdir Resource Management
415 * Bits set in the resource map are in use.
416 * Each bit can represent a number of pages.
417 * LSbs represent lower addresses (IOVA's).
419 ***************************************************************/
420 #define PAGES_PER_RANGE 1 /* could increase this to 4 or 8 if needed */
422 /* Convert from IOVP to IOVA and vice versa. */
423 #define SBA_IOVA(ioc,iovp,offset) ((ioc->ibase) | (iovp) | (offset))
424 #define SBA_IOVP(ioc,iova) ((iova) & ~(ioc->ibase))
426 #define PDIR_ENTRY_SIZE sizeof(u64)
428 #define PDIR_INDEX(iovp) ((iovp)>>iovp_shift)
430 #define RESMAP_MASK(n) ~(~0UL << (n))
431 #define RESMAP_IDX_MASK (sizeof(unsigned long) - 1)
435 * For most cases the normal get_order is sufficient, however it limits us
436 * to PAGE_SIZE being the minimum mapping alignment and TC flush granularity.
437 * It only incurs about 1 clock cycle to use this one with the static variable
438 * and makes the code more intuitive.
440 static SBA_INLINE int
441 get_iovp_order (unsigned long size)
443 long double d = size - 1;
446 order = ia64_getf_exp(d);
447 order = order - iovp_shift - 0xffff + 1;
454 * sba_search_bitmap - find free space in IO PDIR resource bitmap
455 * @ioc: IO MMU structure which owns the pdir we are interested in.
456 * @bits_wanted: number of entries we need.
458 * Find consecutive free bits in resource bitmap.
459 * Each bit represents one entry in the IO Pdir.
460 * Cool perf optimization: search for log2(size) bits at a time.
462 static SBA_INLINE unsigned long
463 sba_search_bitmap(struct ioc *ioc, unsigned long bits_wanted)
465 unsigned long *res_ptr = ioc->res_hint;
466 unsigned long *res_end = (unsigned long *) &(ioc->res_map[ioc->res_size]);
467 unsigned long pide = ~0UL;
469 ASSERT(((unsigned long) ioc->res_hint & (sizeof(unsigned long) - 1UL)) == 0);
470 ASSERT(res_ptr < res_end);
473 * N.B. REO/Grande defect AR2305 can cause TLB fetch timeouts
474 * if a TLB entry is purged while in use. sba_mark_invalid()
475 * purges IOTLB entries in power-of-two sizes, so we also
476 * allocate IOVA space in power-of-two sizes.
478 bits_wanted = 1UL << get_iovp_order(bits_wanted << PAGE_SHIFT);
480 if (likely(bits_wanted == 1)) {
481 unsigned int bitshiftcnt;
482 for(; res_ptr < res_end ; res_ptr++) {
483 if (likely(*res_ptr != ~0UL)) {
484 bitshiftcnt = ffz(*res_ptr);
485 *res_ptr |= (1UL << bitshiftcnt);
486 pide = ((unsigned long)res_ptr - (unsigned long)ioc->res_map);
487 pide <<= 3; /* convert to bit address */
489 ioc->res_bitshift = bitshiftcnt + bits_wanted;
497 if (likely(bits_wanted <= BITS_PER_LONG/2)) {
499 ** Search the resource bit map on well-aligned values.
500 ** "o" is the alignment.
501 ** We need the alignment to invalidate I/O TLB using
502 ** SBA HW features in the unmap path.
504 unsigned long o = 1 << get_iovp_order(bits_wanted << iovp_shift);
505 uint bitshiftcnt = ROUNDUP(ioc->res_bitshift, o);
506 unsigned long mask, base_mask;
508 base_mask = RESMAP_MASK(bits_wanted);
509 mask = base_mask << bitshiftcnt;
511 DBG_RES("%s() o %ld %p", __FUNCTION__, o, res_ptr);
512 for(; res_ptr < res_end ; res_ptr++)
514 DBG_RES(" %p %lx %lx\n", res_ptr, mask, *res_ptr);
516 for (; mask ; mask <<= o, bitshiftcnt += o) {
517 if(0 == ((*res_ptr) & mask)) {
518 *res_ptr |= mask; /* mark resources busy! */
519 pide = ((unsigned long)res_ptr - (unsigned long)ioc->res_map);
520 pide <<= 3; /* convert to bit address */
522 ioc->res_bitshift = bitshiftcnt + bits_wanted;
536 qwords = bits_wanted >> 6; /* /64 */
537 bits = bits_wanted - (qwords * BITS_PER_LONG);
539 end = res_end - qwords;
541 for (; res_ptr < end; res_ptr++) {
542 for (i = 0 ; i < qwords ; i++) {
546 if (bits && res_ptr[i] && (__ffs(res_ptr[i]) < bits))
549 /* Found it, mark it */
550 for (i = 0 ; i < qwords ; i++)
552 res_ptr[i] |= RESMAP_MASK(bits);
554 pide = ((unsigned long)res_ptr - (unsigned long)ioc->res_map);
555 pide <<= 3; /* convert to bit address */
557 ioc->res_bitshift = bits;
565 prefetch(ioc->res_map);
566 ioc->res_hint = (unsigned long *) ioc->res_map;
567 ioc->res_bitshift = 0;
571 ioc->res_hint = res_ptr;
577 * sba_alloc_range - find free bits and mark them in IO PDIR resource bitmap
578 * @ioc: IO MMU structure which owns the pdir we are interested in.
579 * @size: number of bytes to create a mapping for
581 * Given a size, find consecutive unmarked and then mark those bits in the
585 sba_alloc_range(struct ioc *ioc, size_t size)
587 unsigned int pages_needed = size >> iovp_shift;
588 #ifdef PDIR_SEARCH_TIMING
589 unsigned long itc_start;
594 ASSERT(pages_needed);
595 ASSERT(0 == (size & ~iovp_mask));
597 spin_lock_irqsave(&ioc->res_lock, flags);
599 #ifdef PDIR_SEARCH_TIMING
600 itc_start = ia64_get_itc();
603 ** "seek and ye shall find"...praying never hurts either...
605 pide = sba_search_bitmap(ioc, pages_needed);
606 if (unlikely(pide >= (ioc->res_size << 3))) {
607 pide = sba_search_bitmap(ioc, pages_needed);
608 if (unlikely(pide >= (ioc->res_size << 3))) {
609 #if DELAYED_RESOURCE_CNT > 0
611 ** With delayed resource freeing, we can give this one more shot. We're
612 ** getting close to being in trouble here, so do what we can to make this
615 spin_lock(&ioc->saved_lock);
616 if (ioc->saved_cnt > 0) {
617 struct sba_dma_pair *d;
618 int cnt = ioc->saved_cnt;
620 d = &(ioc->saved[ioc->saved_cnt]);
623 sba_mark_invalid(ioc, d->iova, d->size);
624 sba_free_range(ioc, d->iova, d->size);
628 READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */
630 spin_unlock(&ioc->saved_lock);
632 pide = sba_search_bitmap(ioc, pages_needed);
633 if (unlikely(pide >= (ioc->res_size << 3)))
634 panic(__FILE__ ": I/O MMU @ %p is out of mapping resources\n",
637 panic(__FILE__ ": I/O MMU @ %p is out of mapping resources\n",
643 #ifdef PDIR_SEARCH_TIMING
644 ioc->avg_search[ioc->avg_idx++] = (ia64_get_itc() - itc_start) / pages_needed;
645 ioc->avg_idx &= SBA_SEARCH_SAMPLE - 1;
648 prefetchw(&(ioc->pdir_base[pide]));
650 #ifdef ASSERT_PDIR_SANITY
651 /* verify the first enable bit is clear */
652 if(0x00 != ((u8 *) ioc->pdir_base)[pide*PDIR_ENTRY_SIZE + 7]) {
653 sba_dump_pdir_entry(ioc, "sba_search_bitmap() botched it?", pide);
657 DBG_RES("%s(%x) %d -> %lx hint %x/%x\n",
658 __FUNCTION__, size, pages_needed, pide,
659 (uint) ((unsigned long) ioc->res_hint - (unsigned long) ioc->res_map),
662 spin_unlock_irqrestore(&ioc->res_lock, flags);
669 * sba_free_range - unmark bits in IO PDIR resource bitmap
670 * @ioc: IO MMU structure which owns the pdir we are interested in.
671 * @iova: IO virtual address which was previously allocated.
672 * @size: number of bytes to create a mapping for
674 * clear bits in the ioc's resource map
676 static SBA_INLINE void
677 sba_free_range(struct ioc *ioc, dma_addr_t iova, size_t size)
679 unsigned long iovp = SBA_IOVP(ioc, iova);
680 unsigned int pide = PDIR_INDEX(iovp);
681 unsigned int ridx = pide >> 3; /* convert bit to byte address */
682 unsigned long *res_ptr = (unsigned long *) &((ioc)->res_map[ridx & ~RESMAP_IDX_MASK]);
683 int bits_not_wanted = size >> iovp_shift;
686 /* Round up to power-of-two size: see AR2305 note above */
687 bits_not_wanted = 1UL << get_iovp_order(bits_not_wanted << PAGE_SHIFT);
688 for (; bits_not_wanted > 0 ; res_ptr++) {
690 if (unlikely(bits_not_wanted > BITS_PER_LONG)) {
692 /* these mappings start 64bit aligned */
694 bits_not_wanted -= BITS_PER_LONG;
695 pide += BITS_PER_LONG;
699 /* 3-bits "bit" address plus 2 (or 3) bits for "byte" == bit in word */
700 m = RESMAP_MASK(bits_not_wanted) << (pide & (BITS_PER_LONG - 1));
703 DBG_RES("%s( ,%x,%x) %x/%lx %x %p %lx\n", __FUNCTION__, (uint) iova, size,
704 bits_not_wanted, m, pide, res_ptr, *res_ptr);
707 ASSERT(bits_not_wanted);
708 ASSERT((*res_ptr & m) == m); /* verify same bits are set */
715 /**************************************************************
717 * "Dynamic DMA Mapping" support (aka "Coherent I/O")
719 ***************************************************************/
722 * sba_io_pdir_entry - fill in one IO PDIR entry
723 * @pdir_ptr: pointer to IO PDIR entry
724 * @vba: Virtual CPU address of buffer to map
726 * SBA Mapping Routine
728 * Given a virtual address (vba, arg1) sba_io_pdir_entry()
729 * loads the I/O PDIR entry pointed to by pdir_ptr (arg0).
730 * Each IO Pdir entry consists of 8 bytes as shown below
734 * +-+---------------------+----------------------------------+----+--------+
735 * |V| U | PPN[39:12] | U | FF |
736 * +-+---------------------+----------------------------------+----+--------+
740 * PPN == Physical Page Number
742 * The physical address fields are filled with the results of virt_to_phys()
747 #define sba_io_pdir_entry(pdir_ptr, vba) *pdir_ptr = ((vba & ~0xE000000000000FFFULL) \
748 | 0x8000000000000000ULL)
751 sba_io_pdir_entry(u64 *pdir_ptr, unsigned long vba)
753 *pdir_ptr = ((vba & ~0xE000000000000FFFULL) | 0x80000000000000FFULL);
757 #ifdef ENABLE_MARK_CLEAN
759 * Since DMA is i-cache coherent, any (complete) pages that were written via
760 * DMA can be marked as "clean" so that update_mmu_cache() doesn't have to
761 * flush them when they get mapped into an executable vm-area.
764 mark_clean (void *addr, size_t size)
766 unsigned long pg_addr, end;
768 pg_addr = PAGE_ALIGN((unsigned long) addr);
769 end = (unsigned long) addr + size;
770 while (pg_addr + PAGE_SIZE <= end) {
771 struct page *page = virt_to_page((void *)pg_addr);
772 set_bit(PG_arch_1, &page->flags);
773 pg_addr += PAGE_SIZE;
779 * sba_mark_invalid - invalidate one or more IO PDIR entries
780 * @ioc: IO MMU structure which owns the pdir we are interested in.
781 * @iova: IO Virtual Address mapped earlier
782 * @byte_cnt: number of bytes this mapping covers.
784 * Marking the IO PDIR entry(ies) as Invalid and invalidate
785 * corresponding IO TLB entry. The PCOM (Purge Command Register)
786 * is to purge stale entries in the IO TLB when unmapping entries.
788 * The PCOM register supports purging of multiple pages, with a minium
789 * of 1 page and a maximum of 2GB. Hardware requires the address be
790 * aligned to the size of the range being purged. The size of the range
791 * must be a power of 2. The "Cool perf optimization" in the
792 * allocation routine helps keep that true.
794 static SBA_INLINE void
795 sba_mark_invalid(struct ioc *ioc, dma_addr_t iova, size_t byte_cnt)
797 u32 iovp = (u32) SBA_IOVP(ioc,iova);
799 int off = PDIR_INDEX(iovp);
801 /* Must be non-zero and rounded up */
802 ASSERT(byte_cnt > 0);
803 ASSERT(0 == (byte_cnt & ~iovp_mask));
805 #ifdef ASSERT_PDIR_SANITY
806 /* Assert first pdir entry is set */
807 if (!(ioc->pdir_base[off] >> 60)) {
808 sba_dump_pdir_entry(ioc,"sba_mark_invalid()", PDIR_INDEX(iovp));
812 if (byte_cnt <= iovp_size)
814 ASSERT(off < ioc->pdir_size);
816 iovp |= iovp_shift; /* set "size" field for PCOM */
818 #ifndef FULL_VALID_PDIR
820 ** clear I/O PDIR entry "valid" bit
821 ** Do NOT clear the rest - save it for debugging.
822 ** We should only clear bits that have previously
825 ioc->pdir_base[off] &= ~(0x80000000000000FFULL);
828 ** If we want to maintain the PDIR as valid, put in
829 ** the spill page so devices prefetching won't
830 ** cause a hard fail.
832 ioc->pdir_base[off] = (0x80000000000000FFULL | prefetch_spill_page);
835 u32 t = get_iovp_order(byte_cnt) + iovp_shift;
838 ASSERT(t <= 31); /* 2GB! Max value of "size" field */
841 /* verify this pdir entry is enabled */
842 ASSERT(ioc->pdir_base[off] >> 63);
843 #ifndef FULL_VALID_PDIR
844 /* clear I/O Pdir entry "valid" bit first */
845 ioc->pdir_base[off] &= ~(0x80000000000000FFULL);
847 ioc->pdir_base[off] = (0x80000000000000FFULL | prefetch_spill_page);
850 byte_cnt -= iovp_size;
851 } while (byte_cnt > 0);
854 WRITE_REG(iovp | ioc->ibase, ioc->ioc_hpa+IOC_PCOM);
858 * sba_map_single - map one buffer and return IOVA for DMA
859 * @dev: instance of PCI owned by the driver that's asking.
860 * @addr: driver buffer to map.
861 * @size: number of bytes to map in driver buffer.
864 * See Documentation/DMA-mapping.txt
867 sba_map_single(struct device *dev, void *addr, size_t size, int dir)
874 #ifdef ASSERT_PDIR_SANITY
877 #ifdef ALLOW_IOV_BYPASS
878 unsigned long pci_addr = virt_to_phys(addr);
881 #ifdef ALLOW_IOV_BYPASS
882 ASSERT(to_pci_dev(dev)->dma_mask);
884 ** Check if the PCI device can DMA to ptr... if so, just return ptr
886 if (likely((pci_addr & ~to_pci_dev(dev)->dma_mask) == 0)) {
888 ** Device is bit capable of DMA'ing to the buffer...
889 ** just return the PCI address of ptr
891 DBG_BYPASS("sba_map_single() bypass mask/addr: 0x%lx/0x%lx\n",
892 to_pci_dev(dev)->dma_mask, pci_addr);
899 prefetch(ioc->res_hint);
902 ASSERT(size <= DMA_CHUNK_SIZE);
904 /* save offset bits */
905 offset = ((dma_addr_t) (long) addr) & ~iovp_mask;
907 /* round up to nearest iovp_size */
908 size = (size + offset + ~iovp_mask) & iovp_mask;
910 #ifdef ASSERT_PDIR_SANITY
911 spin_lock_irqsave(&ioc->res_lock, flags);
912 if (sba_check_pdir(ioc,"Check before sba_map_single()"))
913 panic("Sanity check failed");
914 spin_unlock_irqrestore(&ioc->res_lock, flags);
917 pide = sba_alloc_range(ioc, size);
919 iovp = (dma_addr_t) pide << iovp_shift;
921 DBG_RUN("%s() 0x%p -> 0x%lx\n",
922 __FUNCTION__, addr, (long) iovp | offset);
924 pdir_start = &(ioc->pdir_base[pide]);
927 ASSERT(((u8 *)pdir_start)[7] == 0); /* verify availability */
928 sba_io_pdir_entry(pdir_start, (unsigned long) addr);
930 DBG_RUN(" pdir 0x%p %lx\n", pdir_start, *pdir_start);
936 /* force pdir update */
939 /* form complete address */
940 #ifdef ASSERT_PDIR_SANITY
941 spin_lock_irqsave(&ioc->res_lock, flags);
942 sba_check_pdir(ioc,"Check after sba_map_single()");
943 spin_unlock_irqrestore(&ioc->res_lock, flags);
945 return SBA_IOVA(ioc, iovp, offset);
949 * sba_unmap_single - unmap one IOVA and free resources
950 * @dev: instance of PCI owned by the driver that's asking.
951 * @iova: IOVA of driver buffer previously mapped.
952 * @size: number of bytes mapped in driver buffer.
955 * See Documentation/DMA-mapping.txt
957 void sba_unmap_single(struct device *dev, dma_addr_t iova, size_t size, int dir)
960 #if DELAYED_RESOURCE_CNT > 0
961 struct sba_dma_pair *d;
969 #ifdef ALLOW_IOV_BYPASS
970 if (likely((iova & ioc->imask) != ioc->ibase)) {
972 ** Address does not fall w/in IOVA, must be bypassing
974 DBG_BYPASS("sba_unmap_single() bypass addr: 0x%lx\n", iova);
976 #ifdef ENABLE_MARK_CLEAN
977 if (dir == DMA_FROM_DEVICE) {
978 mark_clean(phys_to_virt(iova), size);
984 offset = iova & ~iovp_mask;
986 DBG_RUN("%s() iovp 0x%lx/%x\n",
987 __FUNCTION__, (long) iova, size);
989 iova ^= offset; /* clear offset bits */
991 size = ROUNDUP(size, iovp_size);
994 #if DELAYED_RESOURCE_CNT > 0
995 spin_lock_irqsave(&ioc->saved_lock, flags);
996 d = &(ioc->saved[ioc->saved_cnt]);
999 if (unlikely(++(ioc->saved_cnt) >= DELAYED_RESOURCE_CNT)) {
1000 int cnt = ioc->saved_cnt;
1001 spin_lock(&ioc->res_lock);
1003 sba_mark_invalid(ioc, d->iova, d->size);
1004 sba_free_range(ioc, d->iova, d->size);
1008 READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */
1009 spin_unlock(&ioc->res_lock);
1011 spin_unlock_irqrestore(&ioc->saved_lock, flags);
1012 #else /* DELAYED_RESOURCE_CNT == 0 */
1013 spin_lock_irqsave(&ioc->res_lock, flags);
1014 sba_mark_invalid(ioc, iova, size);
1015 sba_free_range(ioc, iova, size);
1016 READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */
1017 spin_unlock_irqrestore(&ioc->res_lock, flags);
1018 #endif /* DELAYED_RESOURCE_CNT == 0 */
1019 #ifdef ENABLE_MARK_CLEAN
1020 if (dir == DMA_FROM_DEVICE) {
1021 u32 iovp = (u32) SBA_IOVP(ioc,iova);
1022 int off = PDIR_INDEX(iovp);
1025 if (size <= iovp_size) {
1026 addr = phys_to_virt(ioc->pdir_base[off] &
1027 ~0xE000000000000FFFULL);
1028 mark_clean(addr, size);
1030 size_t byte_cnt = size;
1033 addr = phys_to_virt(ioc->pdir_base[off] &
1034 ~0xE000000000000FFFULL);
1035 mark_clean(addr, min(byte_cnt, iovp_size));
1037 byte_cnt -= iovp_size;
1039 } while (byte_cnt > 0);
1047 * sba_alloc_coherent - allocate/map shared mem for DMA
1048 * @dev: instance of PCI owned by the driver that's asking.
1049 * @size: number of bytes mapped in driver buffer.
1050 * @dma_handle: IOVA of new buffer.
1052 * See Documentation/DMA-mapping.txt
1055 sba_alloc_coherent (struct device *dev, size_t size, dma_addr_t *dma_handle, int flags)
1060 addr = (void *) __get_free_pages(flags, get_order(size));
1061 if (unlikely(!addr))
1064 memset(addr, 0, size);
1065 *dma_handle = virt_to_phys(addr);
1067 #ifdef ALLOW_IOV_BYPASS
1068 ASSERT(dev->coherent_dma_mask);
1070 ** Check if the PCI device can DMA to ptr... if so, just return ptr
1072 if (likely((*dma_handle & ~dev->coherent_dma_mask) == 0)) {
1073 DBG_BYPASS("sba_alloc_coherent() bypass mask/addr: 0x%lx/0x%lx\n",
1074 dev->coherent_dma_mask, *dma_handle);
1081 * If device can't bypass or bypass is disabled, pass the 32bit fake
1082 * device to map single to get an iova mapping.
1086 *dma_handle = sba_map_single(&ioc->sac_only_dev->dev, addr, size, 0);
1093 * sba_free_coherent - free/unmap shared mem for DMA
1094 * @dev: instance of PCI owned by the driver that's asking.
1095 * @size: number of bytes mapped in driver buffer.
1096 * @vaddr: virtual address IOVA of "consistent" buffer.
1097 * @dma_handler: IO virtual address of "consistent" buffer.
1099 * See Documentation/DMA-mapping.txt
1101 void sba_free_coherent (struct device *dev, size_t size, void *vaddr, dma_addr_t dma_handle)
1103 sba_unmap_single(dev, dma_handle, size, 0);
1104 free_pages((unsigned long) vaddr, get_order(size));
1109 ** Since 0 is a valid pdir_base index value, can't use that
1110 ** to determine if a value is valid or not. Use a flag to indicate
1111 ** the SG list entry contains a valid pdir index.
1113 #define PIDE_FLAG 0x1UL
1115 #ifdef DEBUG_LARGE_SG_ENTRIES
1116 int dump_run_sg = 0;
1121 * sba_fill_pdir - write allocated SG entries into IO PDIR
1122 * @ioc: IO MMU structure which owns the pdir we are interested in.
1123 * @startsg: list of IOVA/size pairs
1124 * @nents: number of entries in startsg list
1126 * Take preprocessed SG list and write corresponding entries
1130 static SBA_INLINE int
1133 struct scatterlist *startsg,
1136 struct scatterlist *dma_sg = startsg; /* pointer to current DMA */
1139 unsigned long dma_offset = 0;
1142 while (nents-- > 0) {
1143 int cnt = startsg->dma_length;
1144 startsg->dma_length = 0;
1146 #ifdef DEBUG_LARGE_SG_ENTRIES
1148 printk(" %2d : %08lx/%05x %p\n",
1149 nents, startsg->dma_address, cnt,
1150 sba_sg_address(startsg));
1152 DBG_RUN_SG(" %d : %08lx/%05x %p\n",
1153 nents, startsg->dma_address, cnt,
1154 sba_sg_address(startsg));
1157 ** Look for the start of a new DMA stream
1159 if (startsg->dma_address & PIDE_FLAG) {
1160 u32 pide = startsg->dma_address & ~PIDE_FLAG;
1161 dma_offset = (unsigned long) pide & ~iovp_mask;
1162 startsg->dma_address = 0;
1164 dma_sg->dma_address = pide | ioc->ibase;
1165 pdirp = &(ioc->pdir_base[pide >> iovp_shift]);
1170 ** Look for a VCONTIG chunk
1173 unsigned long vaddr = (unsigned long) sba_sg_address(startsg);
1176 /* Since multiple Vcontig blocks could make up
1177 ** one DMA stream, *add* cnt to dma_len.
1179 dma_sg->dma_length += cnt;
1181 dma_offset=0; /* only want offset on first chunk */
1182 cnt = ROUNDUP(cnt, iovp_size);
1184 sba_io_pdir_entry(pdirp, vaddr);
1192 /* force pdir update */
1195 #ifdef DEBUG_LARGE_SG_ENTRIES
1203 ** Two address ranges are DMA contiguous *iff* "end of prev" and
1204 ** "start of next" are both on an IOV page boundary.
1206 ** (shift left is a quick trick to mask off upper bits)
1208 #define DMA_CONTIG(__X, __Y) \
1209 (((((unsigned long) __X) | ((unsigned long) __Y)) << (BITS_PER_LONG - iovp_shift)) == 0UL)
1213 * sba_coalesce_chunks - preprocess the SG list
1214 * @ioc: IO MMU structure which owns the pdir we are interested in.
1215 * @startsg: list of IOVA/size pairs
1216 * @nents: number of entries in startsg list
1218 * First pass is to walk the SG list and determine where the breaks are
1219 * in the DMA stream. Allocates PDIR entries but does not fill them.
1220 * Returns the number of DMA chunks.
1222 * Doing the fill separate from the coalescing/allocation keeps the
1223 * code simpler. Future enhancement could make one pass through
1224 * the sglist do both.
1226 static SBA_INLINE int
1227 sba_coalesce_chunks( struct ioc *ioc,
1228 struct scatterlist *startsg,
1231 struct scatterlist *vcontig_sg; /* VCONTIG chunk head */
1232 unsigned long vcontig_len; /* len of VCONTIG chunk */
1233 unsigned long vcontig_end;
1234 struct scatterlist *dma_sg; /* next DMA stream head */
1235 unsigned long dma_offset, dma_len; /* start/len of DMA stream */
1239 unsigned long vaddr = (unsigned long) sba_sg_address(startsg);
1242 ** Prepare for first/next DMA stream
1244 dma_sg = vcontig_sg = startsg;
1245 dma_len = vcontig_len = vcontig_end = startsg->length;
1246 vcontig_end += vaddr;
1247 dma_offset = vaddr & ~iovp_mask;
1249 /* PARANOID: clear entries */
1250 startsg->dma_address = startsg->dma_length = 0;
1253 ** This loop terminates one iteration "early" since
1254 ** it's always looking one "ahead".
1256 while (--nents > 0) {
1257 unsigned long vaddr; /* tmp */
1262 startsg->dma_address = startsg->dma_length = 0;
1264 /* catch brokenness in SCSI layer */
1265 ASSERT(startsg->length <= DMA_CHUNK_SIZE);
1268 ** First make sure current dma stream won't
1269 ** exceed DMA_CHUNK_SIZE if we coalesce the
1272 if (((dma_len + dma_offset + startsg->length + ~iovp_mask) & iovp_mask)
1277 ** Then look for virtually contiguous blocks.
1279 ** append the next transaction?
1281 vaddr = (unsigned long) sba_sg_address(startsg);
1282 if (vcontig_end == vaddr)
1284 vcontig_len += startsg->length;
1285 vcontig_end += startsg->length;
1286 dma_len += startsg->length;
1290 #ifdef DEBUG_LARGE_SG_ENTRIES
1291 dump_run_sg = (vcontig_len > iovp_size);
1295 ** Not virtually contigous.
1296 ** Terminate prev chunk.
1297 ** Start a new chunk.
1299 ** Once we start a new VCONTIG chunk, dma_offset
1300 ** can't change. And we need the offset from the first
1301 ** chunk - not the last one. Ergo Successive chunks
1302 ** must start on page boundaries and dove tail
1303 ** with it's predecessor.
1305 vcontig_sg->dma_length = vcontig_len;
1307 vcontig_sg = startsg;
1308 vcontig_len = startsg->length;
1311 ** 3) do the entries end/start on page boundaries?
1312 ** Don't update vcontig_end until we've checked.
1314 if (DMA_CONTIG(vcontig_end, vaddr))
1316 vcontig_end = vcontig_len + vaddr;
1317 dma_len += vcontig_len;
1325 ** End of DMA Stream
1326 ** Terminate last VCONTIG block.
1327 ** Allocate space for DMA stream.
1329 vcontig_sg->dma_length = vcontig_len;
1330 dma_len = (dma_len + dma_offset + ~iovp_mask) & iovp_mask;
1331 ASSERT(dma_len <= DMA_CHUNK_SIZE);
1332 dma_sg->dma_address = (dma_addr_t) (PIDE_FLAG
1333 | (sba_alloc_range(ioc, dma_len) << iovp_shift)
1343 * sba_map_sg - map Scatter/Gather list
1344 * @dev: instance of PCI owned by the driver that's asking.
1345 * @sglist: array of buffer/length pairs
1346 * @nents: number of entries in list
1347 * @dir: R/W or both.
1349 * See Documentation/DMA-mapping.txt
1351 int sba_map_sg(struct device *dev, struct scatterlist *sglist, int nents, int dir)
1354 int coalesced, filled = 0;
1355 #ifdef ASSERT_PDIR_SANITY
1356 unsigned long flags;
1358 #ifdef ALLOW_IOV_BYPASS_SG
1359 struct scatterlist *sg;
1362 DBG_RUN_SG("%s() START %d entries\n", __FUNCTION__, nents);
1366 #ifdef ALLOW_IOV_BYPASS_SG
1367 ASSERT(to_pci_dev(dev)->dma_mask);
1368 if (likely((ioc->dma_mask & ~to_pci_dev(dev)->dma_mask) == 0)) {
1369 for (sg = sglist ; filled < nents ; filled++, sg++){
1370 sg->dma_length = sg->length;
1371 sg->dma_address = virt_to_phys(sba_sg_address(sg));
1376 /* Fast path single entry scatterlists. */
1378 sglist->dma_length = sglist->length;
1379 sglist->dma_address = sba_map_single(dev, sba_sg_address(sglist), sglist->length, dir);
1383 #ifdef ASSERT_PDIR_SANITY
1384 spin_lock_irqsave(&ioc->res_lock, flags);
1385 if (sba_check_pdir(ioc,"Check before sba_map_sg()"))
1387 sba_dump_sg(ioc, sglist, nents);
1388 panic("Check before sba_map_sg()");
1390 spin_unlock_irqrestore(&ioc->res_lock, flags);
1393 prefetch(ioc->res_hint);
1396 ** First coalesce the chunks and allocate I/O pdir space
1398 ** If this is one DMA stream, we can properly map using the
1399 ** correct virtual address associated with each DMA page.
1400 ** w/o this association, we wouldn't have coherent DMA!
1401 ** Access to the virtual address is what forces a two pass algorithm.
1403 coalesced = sba_coalesce_chunks(ioc, sglist, nents);
1406 ** Program the I/O Pdir
1408 ** map the virtual addresses to the I/O Pdir
1409 ** o dma_address will contain the pdir index
1410 ** o dma_len will contain the number of bytes to map
1411 ** o address contains the virtual address.
1413 filled = sba_fill_pdir(ioc, sglist, nents);
1415 #ifdef ASSERT_PDIR_SANITY
1416 spin_lock_irqsave(&ioc->res_lock, flags);
1417 if (sba_check_pdir(ioc,"Check after sba_map_sg()"))
1419 sba_dump_sg(ioc, sglist, nents);
1420 panic("Check after sba_map_sg()\n");
1422 spin_unlock_irqrestore(&ioc->res_lock, flags);
1425 ASSERT(coalesced == filled);
1426 DBG_RUN_SG("%s() DONE %d mappings\n", __FUNCTION__, filled);
1433 * sba_unmap_sg - unmap Scatter/Gather list
1434 * @dev: instance of PCI owned by the driver that's asking.
1435 * @sglist: array of buffer/length pairs
1436 * @nents: number of entries in list
1437 * @dir: R/W or both.
1439 * See Documentation/DMA-mapping.txt
1441 void sba_unmap_sg (struct device *dev, struct scatterlist *sglist, int nents, int dir)
1443 #ifdef ASSERT_PDIR_SANITY
1445 unsigned long flags;
1448 DBG_RUN_SG("%s() START %d entries, %p,%x\n",
1449 __FUNCTION__, nents, sba_sg_address(sglist), sglist->length);
1451 #ifdef ASSERT_PDIR_SANITY
1455 spin_lock_irqsave(&ioc->res_lock, flags);
1456 sba_check_pdir(ioc,"Check before sba_unmap_sg()");
1457 spin_unlock_irqrestore(&ioc->res_lock, flags);
1460 while (nents && sglist->dma_length) {
1462 sba_unmap_single(dev, sglist->dma_address, sglist->dma_length, dir);
1467 DBG_RUN_SG("%s() DONE (nents %d)\n", __FUNCTION__, nents);
1469 #ifdef ASSERT_PDIR_SANITY
1470 spin_lock_irqsave(&ioc->res_lock, flags);
1471 sba_check_pdir(ioc,"Check after sba_unmap_sg()");
1472 spin_unlock_irqrestore(&ioc->res_lock, flags);
1477 /**************************************************************
1479 * Initialization and claim
1481 ***************************************************************/
1484 ioc_iova_init(struct ioc *ioc)
1488 struct pci_dev *device = NULL;
1489 #ifdef FULL_VALID_PDIR
1490 unsigned long index;
1494 ** Firmware programs the base and size of a "safe IOVA space"
1495 ** (one that doesn't overlap memory or LMMIO space) in the
1496 ** IBASE and IMASK registers.
1498 ioc->ibase = READ_REG(ioc->ioc_hpa + IOC_IBASE) & ~0x1UL;
1499 ioc->imask = READ_REG(ioc->ioc_hpa + IOC_IMASK) | 0xFFFFFFFF00000000UL;
1501 ioc->iov_size = ~ioc->imask + 1;
1503 DBG_INIT("%s() hpa %p IOV base 0x%lx mask 0x%lx (%dMB)\n",
1504 __FUNCTION__, ioc->ioc_hpa, ioc->ibase, ioc->imask,
1505 ioc->iov_size >> 20);
1507 switch (iovp_size) {
1508 case 4*1024: tcnfg = 0; break;
1509 case 8*1024: tcnfg = 1; break;
1510 case 16*1024: tcnfg = 2; break;
1511 case 64*1024: tcnfg = 3; break;
1513 panic(PFX "Unsupported IOTLB page size %ldK",
1517 WRITE_REG(tcnfg, ioc->ioc_hpa + IOC_TCNFG);
1519 ioc->pdir_size = (ioc->iov_size / iovp_size) * PDIR_ENTRY_SIZE;
1520 ioc->pdir_base = (void *) __get_free_pages(GFP_KERNEL,
1521 get_order(ioc->pdir_size));
1522 if (!ioc->pdir_base)
1523 panic(PFX "Couldn't allocate I/O Page Table\n");
1525 memset(ioc->pdir_base, 0, ioc->pdir_size);
1527 DBG_INIT("%s() IOV page size %ldK pdir %p size %x\n", __FUNCTION__,
1528 iovp_size >> 10, ioc->pdir_base, ioc->pdir_size);
1530 ASSERT(ALIGN((unsigned long) ioc->pdir_base, 4*1024) == (unsigned long) ioc->pdir_base);
1531 WRITE_REG(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE);
1534 ** If an AGP device is present, only use half of the IOV space
1535 ** for PCI DMA. Unfortunately we can't know ahead of time
1536 ** whether GART support will actually be used, for now we
1537 ** can just key on an AGP device found in the system.
1538 ** We program the next pdir index after we stop w/ a key for
1539 ** the GART code to handshake on.
1541 while ((device = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, device)) != NULL)
1542 agp_found |= pci_find_capability(device, PCI_CAP_ID_AGP);
1544 if (agp_found && reserve_sba_gart) {
1545 printk(KERN_INFO PFX "reserving %dMb of IOVA space at 0x%lx for agpgart\n",
1546 ioc->iov_size/2 >> 20, ioc->ibase + ioc->iov_size/2);
1547 ioc->pdir_size /= 2;
1548 ((u64 *)ioc->pdir_base)[PDIR_INDEX(ioc->iov_size/2)] = ZX1_SBA_IOMMU_COOKIE;
1550 #ifdef FULL_VALID_PDIR
1552 ** Check to see if the spill page has been allocated, we don't need more than
1553 ** one across multiple SBAs.
1555 if (!prefetch_spill_page) {
1556 char *spill_poison = "SBAIOMMU POISON";
1557 int poison_size = 16;
1558 void *poison_addr, *addr;
1560 addr = (void *)__get_free_pages(GFP_KERNEL, get_order(iovp_size));
1562 panic(PFX "Couldn't allocate PDIR spill page\n");
1565 for ( ; (u64) poison_addr < addr + iovp_size; poison_addr += poison_size)
1566 memcpy(poison_addr, spill_poison, poison_size);
1568 prefetch_spill_page = virt_to_phys(addr);
1570 DBG_INIT("%s() prefetch spill addr: 0x%lx\n", __FUNCTION__, prefetch_spill_page);
1573 ** Set all the PDIR entries valid w/ the spill page as the target
1575 for (index = 0 ; index < (ioc->pdir_size / PDIR_ENTRY_SIZE) ; index++)
1576 ((u64 *)ioc->pdir_base)[index] = (0x80000000000000FF | prefetch_spill_page);
1579 /* Clear I/O TLB of any possible entries */
1580 WRITE_REG(ioc->ibase | (get_iovp_order(ioc->iov_size) + iovp_shift), ioc->ioc_hpa + IOC_PCOM);
1581 READ_REG(ioc->ioc_hpa + IOC_PCOM);
1583 /* Enable IOVA translation */
1584 WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa + IOC_IBASE);
1585 READ_REG(ioc->ioc_hpa + IOC_IBASE);
1589 ioc_resource_init(struct ioc *ioc)
1591 spin_lock_init(&ioc->res_lock);
1592 #if DELAYED_RESOURCE_CNT > 0
1593 spin_lock_init(&ioc->saved_lock);
1596 /* resource map size dictated by pdir_size */
1597 ioc->res_size = ioc->pdir_size / PDIR_ENTRY_SIZE; /* entries */
1598 ioc->res_size >>= 3; /* convert bit count to byte count */
1599 DBG_INIT("%s() res_size 0x%x\n", __FUNCTION__, ioc->res_size);
1601 ioc->res_map = (char *) __get_free_pages(GFP_KERNEL,
1602 get_order(ioc->res_size));
1604 panic(PFX "Couldn't allocate resource map\n");
1606 memset(ioc->res_map, 0, ioc->res_size);
1607 /* next available IOVP - circular search */
1608 ioc->res_hint = (unsigned long *) ioc->res_map;
1610 #ifdef ASSERT_PDIR_SANITY
1611 /* Mark first bit busy - ie no IOVA 0 */
1612 ioc->res_map[0] = 0x1;
1613 ioc->pdir_base[0] = 0x8000000000000000ULL | ZX1_SBA_IOMMU_COOKIE;
1615 #ifdef FULL_VALID_PDIR
1616 /* Mark the last resource used so we don't prefetch beyond IOVA space */
1617 ioc->res_map[ioc->res_size - 1] |= 0x80UL; /* res_map is chars */
1618 ioc->pdir_base[(ioc->pdir_size / PDIR_ENTRY_SIZE) - 1] = (0x80000000000000FF
1619 | prefetch_spill_page);
1622 DBG_INIT("%s() res_map %x %p\n", __FUNCTION__,
1623 ioc->res_size, (void *) ioc->res_map);
1627 ioc_sac_init(struct ioc *ioc)
1629 struct pci_dev *sac = NULL;
1630 struct pci_controller *controller = NULL;
1633 * pci_alloc_coherent() must return a DMA address which is
1634 * SAC (single address cycle) addressable, so allocate a
1635 * pseudo-device to enforce that.
1637 sac = kmalloc(sizeof(*sac), GFP_KERNEL);
1639 panic(PFX "Couldn't allocate struct pci_dev");
1640 memset(sac, 0, sizeof(*sac));
1642 controller = kmalloc(sizeof(*controller), GFP_KERNEL);
1644 panic(PFX "Couldn't allocate struct pci_controller");
1645 memset(controller, 0, sizeof(*controller));
1647 controller->iommu = ioc;
1648 sac->sysdata = controller;
1649 sac->dma_mask = 0xFFFFFFFFUL;
1651 sac->dev.bus = &pci_bus_type;
1653 ioc->sac_only_dev = sac;
1657 ioc_zx1_init(struct ioc *ioc)
1659 unsigned long rope_config;
1662 if (ioc->rev < 0x20)
1663 panic(PFX "IOC 2.0 or later required for IOMMU support\n");
1665 /* 38 bit memory controller + extra bit for range displaced by MMIO */
1666 ioc->dma_mask = (0x1UL << 39) - 1;
1669 ** Clear ROPE(N)_CONFIG AO bit.
1670 ** Disables "NT Ordering" (~= !"Relaxed Ordering")
1671 ** Overrides bit 1 in DMA Hint Sets.
1672 ** Improves netperf UDP_STREAM by ~10% for tg3 on bcm5701.
1674 for (i=0; i<(8*8); i+=8) {
1675 rope_config = READ_REG(ioc->ioc_hpa + IOC_ROPE0_CFG + i);
1676 rope_config &= ~IOC_ROPE_AO;
1677 WRITE_REG(rope_config, ioc->ioc_hpa + IOC_ROPE0_CFG + i);
1681 typedef void (initfunc)(struct ioc *);
1689 static struct ioc_iommu ioc_iommu_info[] __initdata = {
1690 { ZX1_IOC_ID, "zx1", ioc_zx1_init },
1691 { SX1000_IOC_ID, "sx1000", NULL },
1694 static struct ioc * __init
1695 ioc_init(u64 hpa, void *handle)
1698 struct ioc_iommu *info;
1700 ioc = kmalloc(sizeof(*ioc), GFP_KERNEL);
1704 memset(ioc, 0, sizeof(*ioc));
1706 ioc->next = ioc_list;
1709 ioc->handle = handle;
1710 ioc->ioc_hpa = ioremap(hpa, 0x1000);
1712 ioc->func_id = READ_REG(ioc->ioc_hpa + IOC_FUNC_ID);
1713 ioc->rev = READ_REG(ioc->ioc_hpa + IOC_FCLASS) & 0xFFUL;
1714 ioc->dma_mask = 0xFFFFFFFFFFFFFFFFUL; /* conservative */
1716 for (info = ioc_iommu_info; info < ioc_iommu_info + ARRAY_SIZE(ioc_iommu_info); info++) {
1717 if (ioc->func_id == info->func_id) {
1718 ioc->name = info->name;
1724 iovp_size = (1 << iovp_shift);
1725 iovp_mask = ~(iovp_size - 1);
1727 DBG_INIT("%s: PAGE_SIZE %ldK, iovp_size %ldK\n", __FUNCTION__,
1728 PAGE_SIZE >> 10, iovp_size >> 10);
1731 ioc->name = kmalloc(24, GFP_KERNEL);
1733 sprintf((char *) ioc->name, "Unknown (%04x:%04x)",
1734 ioc->func_id & 0xFFFF, (ioc->func_id >> 16) & 0xFFFF);
1736 ioc->name = "Unknown";
1740 ioc_resource_init(ioc);
1743 if ((long) ~iovp_mask > (long) ia64_max_iommu_merge_mask)
1744 ia64_max_iommu_merge_mask = ~iovp_mask;
1746 printk(KERN_INFO PFX
1747 "%s %d.%d HPA 0x%lx IOVA space %dMb at 0x%lx\n",
1748 ioc->name, (ioc->rev >> 4) & 0xF, ioc->rev & 0xF,
1749 hpa, ioc->iov_size >> 20, ioc->ibase);
1756 /**************************************************************************
1758 ** SBA initialization code (HW and SW)
1760 ** o identify SBA chip itself
1761 ** o FIXME: initialize DMA hints for reasonable defaults
1763 **************************************************************************/
1765 #ifdef CONFIG_PROC_FS
1767 ioc_start(struct seq_file *s, loff_t *pos)
1772 for (ioc = ioc_list; ioc; ioc = ioc->next)
1780 ioc_next(struct seq_file *s, void *v, loff_t *pos)
1782 struct ioc *ioc = v;
1789 ioc_stop(struct seq_file *s, void *v)
1794 ioc_show(struct seq_file *s, void *v)
1796 struct ioc *ioc = v;
1797 unsigned long *res_ptr = (unsigned long *)ioc->res_map;
1800 seq_printf(s, "Hewlett Packard %s IOC rev %d.%d\n",
1801 ioc->name, ((ioc->rev >> 4) & 0xF), (ioc->rev & 0xF));
1802 seq_printf(s, "IOVA size : %ld MB\n", ((ioc->pdir_size >> 3) * iovp_size)/(1024*1024));
1803 seq_printf(s, "IOVA page size : %ld kb\n", iovp_size/1024);
1805 for (i = 0; i < (ioc->res_size / sizeof(unsigned long)); ++i, ++res_ptr)
1806 used += hweight64(*res_ptr);
1808 seq_printf(s, "PDIR size : %d entries\n", ioc->pdir_size >> 3);
1809 seq_printf(s, "PDIR used : %d entries\n", used);
1811 #ifdef PDIR_SEARCH_TIMING
1813 unsigned long i = 0, avg = 0, min, max;
1814 min = max = ioc->avg_search[0];
1815 for (i = 0; i < SBA_SEARCH_SAMPLE; i++) {
1816 avg += ioc->avg_search[i];
1817 if (ioc->avg_search[i] > max) max = ioc->avg_search[i];
1818 if (ioc->avg_search[i] < min) min = ioc->avg_search[i];
1820 avg /= SBA_SEARCH_SAMPLE;
1821 seq_printf(s, "Bitmap search : %ld/%ld/%ld (min/avg/max CPU Cycles/IOVA page)\n",
1825 #ifndef ALLOW_IOV_BYPASS
1826 seq_printf(s, "IOVA bypass disabled\n");
1831 static struct seq_operations ioc_seq_ops = {
1839 ioc_open(struct inode *inode, struct file *file)
1841 return seq_open(file, &ioc_seq_ops);
1844 static struct file_operations ioc_fops = {
1847 .llseek = seq_lseek,
1848 .release = seq_release
1854 struct proc_dir_entry *dir, *entry;
1856 dir = proc_mkdir("bus/mckinley", 0);
1860 entry = create_proc_entry(ioc_list->name, 0, dir);
1862 entry->proc_fops = &ioc_fops;
1867 sba_connect_bus(struct pci_bus *bus)
1869 acpi_handle handle, parent;
1873 if (!PCI_CONTROLLER(bus))
1874 panic(PFX "no sysdata on bus %d!\n", bus->number);
1876 if (PCI_CONTROLLER(bus)->iommu)
1879 handle = PCI_CONTROLLER(bus)->acpi_handle;
1884 * The IOC scope encloses PCI root bridges in the ACPI
1885 * namespace, so work our way out until we find an IOC we
1886 * claimed previously.
1889 for (ioc = ioc_list; ioc; ioc = ioc->next)
1890 if (ioc->handle == handle) {
1891 PCI_CONTROLLER(bus)->iommu = ioc;
1895 status = acpi_get_parent(handle, &parent);
1897 } while (ACPI_SUCCESS(status));
1899 printk(KERN_WARNING "No IOC for PCI Bus %04x:%02x in ACPI\n", pci_domain_nr(bus), bus->number);
1903 acpi_sba_ioc_add(struct acpi_device *device)
1908 struct acpi_buffer buffer;
1909 struct acpi_device_info *dev_info;
1911 status = hp_acpi_csr_space(device->handle, &hpa, &length);
1912 if (ACPI_FAILURE(status))
1915 buffer.length = ACPI_ALLOCATE_LOCAL_BUFFER;
1916 status = acpi_get_object_info(device->handle, &buffer);
1917 if (ACPI_FAILURE(status))
1919 dev_info = buffer.pointer;
1922 * For HWP0001, only SBA appears in ACPI namespace. It encloses the PCI
1923 * root bridges, and its CSR space includes the IOC function.
1925 if (strncmp("HWP0001", dev_info->hardware_id.value, 7) == 0) {
1926 hpa += ZX1_IOC_OFFSET;
1927 /* zx1 based systems default to kernel page size iommu pages */
1929 iovp_shift = min(PAGE_SHIFT, 16);
1931 ACPI_MEM_FREE(dev_info);
1934 * default anything not caught above or specified on cmdline to 4k
1940 ioc = ioc_init(hpa, device->handle);
1947 static struct acpi_driver acpi_sba_ioc_driver = {
1948 .name = "IOC IOMMU Driver",
1949 .ids = "HWP0001,HWP0004",
1951 .add = acpi_sba_ioc_add,
1958 acpi_bus_register_driver(&acpi_sba_ioc_driver);
1964 struct pci_bus *b = NULL;
1965 while ((b = pci_find_next_bus(b)) != NULL)
1970 #ifdef CONFIG_PROC_FS
1976 subsys_initcall(sba_init); /* must be initialized after ACPI etc., but before any drivers... */
1978 extern void dig_setup(char**);
1980 * MAX_DMA_ADDRESS needs to be setup prior to paging_init to do any good,
1981 * so we use the platform_setup hook to fix it up.
1984 sba_setup(char **cmdline_p)
1986 MAX_DMA_ADDRESS = ~0UL;
1987 dig_setup(cmdline_p);
1991 nosbagart(char *str)
1993 reserve_sba_gart = 0;
1998 sba_dma_supported (struct device *dev, u64 mask)
2000 /* make sure it's at least 32bit capable */
2001 return ((mask & 0xFFFFFFFFUL) == 0xFFFFFFFFUL);
2005 sba_dma_mapping_error (dma_addr_t dma_addr)
2010 __setup("nosbagart", nosbagart);
2013 sba_page_override(char *str)
2015 unsigned long page_size;
2017 page_size = memparse(str, &str);
2018 switch (page_size) {
2023 iovp_shift = ffs(page_size) - 1;
2026 printk("%s: unknown/unsupported iommu page size %ld\n",
2027 __FUNCTION__, page_size);
2033 __setup("sbapagesize=",sba_page_override);
2035 EXPORT_SYMBOL(sba_dma_mapping_error);
2036 EXPORT_SYMBOL(sba_map_single);
2037 EXPORT_SYMBOL(sba_unmap_single);
2038 EXPORT_SYMBOL(sba_map_sg);
2039 EXPORT_SYMBOL(sba_unmap_sg);
2040 EXPORT_SYMBOL(sba_dma_supported);
2041 EXPORT_SYMBOL(sba_alloc_coherent);
2042 EXPORT_SYMBOL(sba_free_coherent);