6 * Copyright (C) 1998-2003 Hewlett-Packard Co
7 * David Mosberger-Tang <davidm@hpl.hp.com>
8 * Copyright (C) 1999, 2002-2003
9 * Asit Mallick <Asit.K.Mallick@intel.com>
10 * Don Dugger <Don.Dugger@intel.com>
11 * Suresh Siddha <suresh.b.siddha@intel.com>
12 * Fenghua Yu <fenghua.yu@intel.com>
13 * Copyright (C) 1999 VA Linux Systems
14 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
17 * ia64_switch_to now places correct virtual mapping in in TR2 for
18 * kernel stack. This allows us to handle interrupts without changing
21 * Jonathan Nicklin <nicklin@missioncriticallinux.com>
22 * Patrick O'Rourke <orourke@missioncriticallinux.com>
26 * Global (preserved) predicate usage on syscall entry/exit path:
34 #include <linux/config.h>
36 #include <asm/asmmacro.h>
37 #include <asm/cache.h>
38 #include <asm/errno.h>
39 #include <asm/kregs.h>
40 #include <asm/offsets.h>
41 #include <asm/pgtable.h>
42 #include <asm/percpu.h>
43 #include <asm/processor.h>
44 #include <asm/thread_info.h>
45 #include <asm/unistd.h>
50 * execve() is special because in case of success, we need to
51 * setup a null register window frame.
54 .prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(3)
55 alloc loc1=ar.pfs,3,2,4,0
58 mov out0=in0 // filename
59 ;; // stop bit between alloc and call
62 add out3=16,sp // regs
63 br.call.sptk.many rp=sys_execve
65 #ifdef CONFIG_IA32_SUPPORT
67 * Check if we're returning to ia32 mode. If so, we need to restore ia32 registers
70 adds r16=PT(CR_IPSR)+16,sp
75 mov ar.pfs=loc1 // restore ar.pfs
76 sxt4 r8=r8 // return 64-bit result
79 (p6) cmp.ne pKStk,pUStk=r0,r0 // a successful execve() lands us in user-mode...
81 (p6) mov ar.pfs=r0 // clear ar.pfs on success
82 (p7) br.ret.sptk.many rp
85 * In theory, we'd have to zap this state only to prevent leaking of
86 * security sensitive state (e.g., if current->mm->dumpable is zero). However,
87 * this executes in less than 20 cycles even on Itanium, so it's not worth
90 mov ar.unat=0; mov ar.lc=0
91 mov r4=0; mov f2=f0; mov b1=r0
92 mov r5=0; mov f3=f0; mov b2=r0
93 mov r6=0; mov f4=f0; mov b3=r0
94 mov r7=0; mov f5=f0; mov b4=r0
95 ldf.fill f12=[sp]; mov f13=f0; mov b5=r0
96 ldf.fill f14=[sp]; ldf.fill f15=[sp]; mov f16=f0
97 ldf.fill f17=[sp]; ldf.fill f18=[sp]; mov f19=f0
98 ldf.fill f20=[sp]; ldf.fill f21=[sp]; mov f22=f0
99 ldf.fill f23=[sp]; ldf.fill f24=[sp]; mov f25=f0
100 ldf.fill f26=[sp]; ldf.fill f27=[sp]; mov f28=f0
101 ldf.fill f29=[sp]; ldf.fill f30=[sp]; mov f31=f0
102 #ifdef CONFIG_IA32_SUPPORT
103 tbit.nz p6,p0=r16, IA64_PSR_IS_BIT
104 movl loc0=ia64_ret_from_ia32_execve
112 * sys_clone2(u64 flags, u64 ustack_base, u64 ustack_size, u64 parent_tidptr, u64 child_tidptr,
115 GLOBAL_ENTRY(sys_clone2)
116 .prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(6)
117 alloc r16=ar.pfs,6,2,6,0
119 adds r2=PT(R16)+IA64_SWITCH_STACK_SIZE+16,sp
121 mov loc1=r16 // save ar.pfs across do_fork
125 tbit.nz p6,p0=in0,CLONE_SETTLS_BIT
126 mov out4=in3 // parent_tidptr: valid only w/CLONE_PARENT_SETTID
128 (p6) st8 [r2]=in5 // store TLS in r16 for copy_thread()
129 mov out5=in4 // child_tidptr: valid only w/CLONE_CHILD_SETTID or CLONE_CHILD_CLEARTID
130 adds out2=IA64_SWITCH_STACK_SIZE+16,sp // out2 = ®s
131 dep out0=0,in0,CLONE_IDLETASK_BIT,1 // out0 = clone_flags & ~CLONE_IDLETASK
132 br.call.sptk.many rp=do_fork
134 adds sp=IA64_SWITCH_STACK_SIZE,sp // pop the switch stack
141 * sys_clone(u64 flags, u64 ustack_base, u64 parent_tidptr, u64 child_tidptr, u64 tls)
142 * Deprecated. Use sys_clone2() instead.
144 GLOBAL_ENTRY(sys_clone)
145 .prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(5)
146 alloc r16=ar.pfs,5,2,6,0
148 adds r2=PT(R16)+IA64_SWITCH_STACK_SIZE+16,sp
150 mov loc1=r16 // save ar.pfs across do_fork
153 mov out3=16 // stacksize (compensates for 16-byte scratch area)
154 tbit.nz p6,p0=in0,CLONE_SETTLS_BIT
155 mov out4=in2 // parent_tidptr: valid only w/CLONE_PARENT_SETTID
157 (p6) st8 [r2]=in4 // store TLS in r13 (tp)
158 mov out5=in3 // child_tidptr: valid only w/CLONE_CHILD_SETTID or CLONE_CHILD_CLEARTID
159 adds out2=IA64_SWITCH_STACK_SIZE+16,sp // out2 = ®s
160 dep out0=0,in0,CLONE_IDLETASK_BIT,1 // out0 = clone_flags & ~CLONE_IDLETASK
161 br.call.sptk.many rp=do_fork
163 adds sp=IA64_SWITCH_STACK_SIZE,sp // pop the switch stack
170 * prev_task <- ia64_switch_to(struct task_struct *next)
171 * With Ingo's new scheduler, interrupts are disabled when this routine gets
172 * called. The code starting at .map relies on this. The rest of the code
173 * doesn't care about the interrupt masking status.
175 GLOBAL_ENTRY(ia64_switch_to)
177 alloc r16=ar.pfs,1,0,0,0
181 adds r22=IA64_TASK_THREAD_KSP_OFFSET,r13
182 mov r27=IA64_KR(CURRENT_STACK)
183 dep r20=0,in0,61,3 // physical address of "current"
185 st8 [r22]=sp // save kernel stack pointer of old task
186 shr.u r26=r20,IA64_GRANULE_SHIFT
187 adds r21=IA64_TASK_THREAD_KSP_OFFSET,in0
190 * If we've already mapped this task's page, we can skip doing it again.
193 (p6) br.cond.dpnt .map
196 (p6) ssm psr.ic // if we we had to map, renable the psr.ic bit FIRST!!!
199 ld8 sp=[r21] // load kernel stack pointer of new task
200 mov IA64_KR(CURRENT)=in0 // update "current" application register
201 mov r8=r13 // return pointer to previously running task
202 mov r13=in0 // set "current" pointer
207 sync.i // ensure "fc"s done by this CPU are visible on other CPUs
209 br.ret.sptk.many rp // boogie on out in new context
212 rsm psr.ic // interrupts (psr.i) are already disabled here
216 or r23=r25,r20 // construct PA | page properties
217 mov r25=IA64_GRANULE_SHIFT<<2
220 mov cr.ifa=in0 // VA of next task...
222 mov r25=IA64_TR_CURRENT_STACK
223 mov IA64_KR(CURRENT_STACK)=r26 // remember last page we mapped...
225 itr.d dtr[r25]=r23 // wire in new mapping...
230 * Note that interrupts are enabled during save_switch_stack and load_switch_stack. This
231 * means that we may get an interrupt with "sp" pointing to the new kernel stack while
232 * ar.bspstore is still pointing to the old kernel backing store area. Since ar.rsc,
233 * ar.rnat, ar.bsp, and ar.bspstore are all preserved by interrupts, this is not a
234 * problem. Also, we don't need to specify unwind information for preserved registers
235 * that are not modified in save_switch_stack as the right unwind information is already
236 * specified at the call-site of save_switch_stack.
242 * - b7 holds address to return to
243 * - rp (b0) holds return address to save
245 GLOBAL_ENTRY(save_switch_stack)
248 flushrs // flush dirty regs to backing store (must be first in insn group)
250 mov r17=ar.unat // preserve caller's
252 #ifdef CONFIG_ITANIUM
255 adds r14=SW(R4)+16,sp
257 st8.spill [r14]=r4,16 // spill r4
258 lfetch.fault.excl.nt1 [r3],128
260 lfetch.fault.excl.nt1 [r2],128
261 lfetch.fault.excl.nt1 [r3],128
263 lfetch.fault.excl [r2]
264 lfetch.fault.excl [r3]
265 adds r15=SW(R5)+16,sp
271 st8.spill [r14]=r4,SW(R6)-SW(R4) // spill r4 and prefetch offset 0x1c0
272 lfetch.fault.excl.nt1 [r3],128 // prefetch offset 0x010
274 lfetch.fault.excl.nt1 [r3],128 // prefetch offset 0x090
275 lfetch.fault.excl.nt1 [r2],128 // prefetch offset 0x190
277 lfetch.fault.excl.nt1 [r3] // prefetch offset 0x110
278 lfetch.fault.excl.nt1 [r2] // prefetch offset 0x210
279 adds r15=SW(R5)+16,sp
282 st8.spill [r15]=r5,SW(R7)-SW(R5) // spill r5
283 mov.m ar.rsc=0 // put RSE in mode: enforced lazy, little endian, pl 0
284 add r2=SW(F2)+16,sp // r2 = &sw->f2
286 st8.spill [r14]=r6,SW(B0)-SW(R6) // spill r6
287 mov.m r18=ar.fpsr // preserve fpsr
288 add r3=SW(F3)+16,sp // r3 = &sw->f3
295 st8.spill [r15]=r7,SW(B2)-SW(R7) // spill r7
298 // since we're done with the spills, read and save ar.unat:
300 mov.m r20=ar.bspstore
306 st8 [r14]=r21,SW(B1)-SW(B0) // save b0
307 st8 [r15]=r23,SW(B3)-SW(B2) // save b2
311 st8 [r14]=r22,SW(B4)-SW(B1) // save b1
312 st8 [r15]=r24,SW(AR_PFS)-SW(B3) // save b3
313 mov r21=ar.lc // I-unit
314 stf.spill [r2]=f12,32
315 stf.spill [r3]=f13,32
317 st8 [r14]=r25,SW(B5)-SW(B4) // save b4
318 st8 [r15]=r16,SW(AR_LC)-SW(AR_PFS) // save ar.pfs
319 stf.spill [r2]=f14,32
320 stf.spill [r3]=f15,32
322 st8 [r14]=r26 // save b5
323 st8 [r15]=r21 // save ar.lc
324 stf.spill [r2]=f16,32
325 stf.spill [r3]=f17,32
327 stf.spill [r2]=f18,32
328 stf.spill [r3]=f19,32
330 stf.spill [r2]=f20,32
331 stf.spill [r3]=f21,32
333 stf.spill [r2]=f22,32
334 stf.spill [r3]=f23,32
336 stf.spill [r2]=f24,32
337 stf.spill [r3]=f25,32
339 stf.spill [r2]=f26,32
340 stf.spill [r3]=f27,32
342 stf.spill [r2]=f28,32
343 stf.spill [r3]=f29,32
345 stf.spill [r2]=f30,SW(AR_UNAT)-SW(F30)
346 stf.spill [r3]=f31,SW(PR)-SW(F31)
347 add r14=SW(CALLER_UNAT)+16,sp
349 st8 [r2]=r29,SW(AR_RNAT)-SW(AR_UNAT) // save ar.unat
350 st8 [r14]=r17,SW(AR_FPSR)-SW(CALLER_UNAT) // save caller_unat
353 st8 [r2]=r19,SW(AR_BSPSTORE)-SW(AR_RNAT) // save ar.rnat
354 st8 [r3]=r21 // save predicate registers
356 st8 [r2]=r20 // save ar.bspstore
357 st8 [r14]=r18 // save fpsr
358 mov ar.rsc=3 // put RSE back into eager mode, pl 0
360 END(save_switch_stack)
364 * - "invala" MUST be done at call site (normally in DO_LOAD_SWITCH_STACK)
365 * - b7 holds address to return to
366 * - must not touch r8-r11
368 ENTRY(load_switch_stack)
373 lfetch.fault.nt1 [sp]
374 adds r2=SW(AR_BSPSTORE)+16,sp
375 adds r3=SW(AR_UNAT)+16,sp
376 mov ar.rsc=0 // put RSE into enforced lazy mode
377 adds r14=SW(CALLER_UNAT)+16,sp
378 adds r15=SW(AR_FPSR)+16,sp
380 ld8 r27=[r2],(SW(B0)-SW(AR_BSPSTORE)) // bspstore
381 ld8 r29=[r3],(SW(B1)-SW(AR_UNAT)) // unat
383 ld8 r21=[r2],16 // restore b0
384 ld8 r22=[r3],16 // restore b1
386 ld8 r23=[r2],16 // restore b2
387 ld8 r24=[r3],16 // restore b3
389 ld8 r25=[r2],16 // restore b4
390 ld8 r26=[r3],16 // restore b5
392 ld8 r16=[r2],(SW(PR)-SW(AR_PFS)) // ar.pfs
393 ld8 r17=[r3],(SW(AR_RNAT)-SW(AR_LC)) // ar.lc
395 ld8 r28=[r2] // restore pr
396 ld8 r30=[r3] // restore rnat
398 ld8 r18=[r14],16 // restore caller's unat
399 ld8 r19=[r15],24 // restore fpsr
407 ldf.fill f12=[r14],32
408 ldf.fill f13=[r15],32
410 ldf.fill f14=[r14],32
411 ldf.fill f15=[r15],32
413 ldf.fill f16=[r14],32
414 ldf.fill f17=[r15],32
416 ldf.fill f18=[r14],32
417 ldf.fill f19=[r15],32
420 ldf.fill f20=[r14],32
421 ldf.fill f21=[r15],32
424 ldf.fill f22=[r14],32
425 ldf.fill f23=[r15],32
429 mov ar.unat=r29 // establish unat holding the NaT bits for r4-r7
432 ldf.fill f24=[r14],32
433 ldf.fill f25=[r15],32
436 ldf.fill f26=[r14],32
437 ldf.fill f27=[r15],32
440 ldf.fill f28=[r14],32
441 ldf.fill f29=[r15],32
444 ldf.fill f30=[r14],32
445 ldf.fill f31=[r15],24
455 mov ar.unat=r18 // restore caller's unat
456 mov ar.rnat=r30 // must restore after bspstore but before rsc!
457 mov ar.fpsr=r19 // restore fpsr
458 mov ar.rsc=3 // put RSE back into eager mode, pl 0
460 END(load_switch_stack)
462 GLOBAL_ENTRY(__ia64_syscall)
464 mov r15=in5 // put syscall number in place
465 break __BREAK_SYSCALL
475 mov r15=__NR_execve // put syscall number in place
476 break __BREAK_SYSCALL
481 mov r15=__NR_clone // put syscall number in place
482 break __BREAK_SYSCALL
487 * Invoke a system call, but do some tracing before and after the call.
488 * We MUST preserve the current register frame throughout this routine
489 * because some system calls (such as ia64_execve) directly
492 GLOBAL_ENTRY(ia64_trace_syscall)
493 PT_REGS_UNWIND_INFO(0)
495 * We need to preserve the scratch registers f6-f11 in case the system
498 adds r16=PT(F6)+16,sp
499 adds r17=PT(F7)+16,sp
501 stf.spill [r16]=f6,32
502 stf.spill [r17]=f7,32
504 stf.spill [r16]=f8,32
505 stf.spill [r17]=f9,32
509 br.call.sptk.many rp=syscall_trace // give parent a chance to catch syscall args
510 adds r16=PT(F6)+16,sp
511 adds r17=PT(F7)+16,sp
521 // the syscall number may have changed, so re-load it and re-calculate the
522 // syscall entry-point:
523 adds r15=PT(R15)+16,sp // r15 = &pt_regs.r15 (syscall #)
526 mov r3=NR_syscalls - 1
529 movl r16=sys_call_table
531 shladd r20=r15,3,r16 // r20 = sys_call_table + 8*(syscall-1024)
534 (p6) ld8 r20=[r20] // load address of syscall entry point
535 (p7) movl r20=sys_ni_syscall
538 br.call.sptk.many rp=b6 // do the syscall
539 .strace_check_retval:
540 cmp.lt p6,p0=r8,r0 // syscall failed?
541 adds r2=PT(R8)+16,sp // r2 = &pt_regs.r8
542 adds r3=PT(R10)+16,sp // r3 = &pt_regs.r10
544 (p6) br.cond.sptk strace_error // syscall failed ->
545 ;; // avoid RAW on r10
547 .mem.offset 0,0; st8.spill [r2]=r8 // store return value in slot for r8
548 .mem.offset 8,0; st8.spill [r3]=r10 // clear error indication in slot for r10
549 br.call.sptk.many rp=syscall_trace // give parent a chance to catch return value
550 .ret3: br.cond.sptk ia64_leave_syscall
553 ld8 r3=[r2] // load pt_regs.r8
554 sub r9=0,r8 // negate return value to get errno value
556 cmp.ne p6,p0=r3,r0 // is pt_regs.r8!=0?
557 adds r3=16,r2 // r3=&pt_regs.r10
561 br.cond.sptk .strace_save_retval
562 END(ia64_trace_syscall)
565 * When traced and returning from sigreturn, we invoke syscall_trace but then
566 * go straight to ia64_leave_kernel rather than ia64_leave_syscall.
568 GLOBAL_ENTRY(ia64_strace_leave_kernel)
569 PT_REGS_UNWIND_INFO(0)
571 * Some versions of gas generate bad unwind info if the first instruction of a
572 * procedure doesn't go into the first slot of a bundle. This is a workaround.
576 br.call.sptk.many rp=syscall_trace // give parent a chance to catch return value
578 .ret4: br.cond.sptk ia64_leave_kernel
579 END(ia64_strace_leave_kernel)
581 GLOBAL_ENTRY(ia64_ret_from_clone)
582 PT_REGS_UNWIND_INFO(0)
584 * Some versions of gas generate bad unwind info if the first instruction of a
585 * procedure doesn't go into the first slot of a bundle. This is a workaround.
590 * We need to call schedule_tail() to complete the scheduling process.
591 * Called by ia64_switch_to() after do_fork()->copy_thread(). r8 contains the
592 * address of the previously executing task.
594 br.call.sptk.many rp=ia64_invoke_schedule_tail
597 adds r2=TI_FLAGS+IA64_TASK_SIZE,r13
602 tbit.nz p6,p0=r2,TIF_SYSCALL_TRACE
603 (p6) br.cond.spnt .strace_check_retval
604 ;; // added stop bits to prevent r8 dependency
605 END(ia64_ret_from_clone)
607 GLOBAL_ENTRY(ia64_ret_from_syscall)
608 PT_REGS_UNWIND_INFO(0)
609 cmp.ge p6,p7=r8,r0 // syscall executed successfully?
610 adds r2=PT(R8)+16,sp // r2 = &pt_regs.r8
611 adds r3=PT(R10)+16,sp // r3 = &pt_regs.r10
613 .mem.offset 0,0; (p6) st8.spill [r2]=r8 // store return value in slot for r8 and set unat bit
614 .mem.offset 8,0; (p6) st8.spill [r3]=r0 // clear error indication in slot for r10 and set unat bit
615 (p7) br.cond.spnt handle_syscall_error // handle potential syscall failure
616 END(ia64_ret_from_syscall)
619 * ia64_leave_syscall(): Same as ia64_leave_kernel, except that it doesn't
620 * need to switch to bank 0 and doesn't restore the scratch registers.
621 * To avoid leaking kernel bits, the scratch registers are set to
622 * the following known-to-be-safe values:
624 * r1: restored (global pointer)
626 * r3: 1 (when returning to user-level)
627 * r8-r11: restored (syscall return value(s))
628 * r12: restored (user-level stack pointer)
629 * r13: restored (user-level thread pointer)
631 * r15: restored (syscall #)
633 * r20: user-level ar.fpsr
636 * r23: user-level ar.bspstore
637 * r24: user-level ar.rnat
638 * r25: user-level ar.unat
639 * r26: user-level ar.pfs
640 * r27: user-level ar.rsc
642 * r29: user-level psr
643 * r30: user-level cfm
646 * pr: restored (user-level pr)
647 * b0: restored (user-level rp)
650 * ar.unat: restored (user-level ar.unat)
651 * ar.pfs: restored (user-level ar.pfs)
652 * ar.rsc: restored (user-level ar.rsc)
653 * ar.rnat: restored (user-level ar.rnat)
654 * ar.bspstore: restored (user-level ar.bspstore)
655 * ar.fpsr: restored (user-level ar.fpsr)
660 GLOBAL_ENTRY(ia64_leave_syscall)
661 PT_REGS_UNWIND_INFO(0)
663 * work.need_resched etc. mustn't get changed by this CPU before it returns to
664 * user- or fsys-mode, hence we disable interrupts early on:
666 #ifdef CONFIG_PREEMPT
667 rsm psr.i // disable interrupts
671 cmp.eq pLvSys,p0=r0,r0 // pLvSys=1: leave from syscall
672 (pUStk) cmp.eq.unc p6,p0=r0,r0 // p6 <- pUStk
673 .work_processed_syscall:
674 #ifdef CONFIG_PREEMPT
675 (pKStk) adds r20=TI_PRE_COUNT+IA64_TASK_SIZE,r13
677 .pred.rel.mutex pUStk,pKStk
678 (pKStk) ld4 r21=[r20] // r21 <- preempt_count
679 (pUStk) mov r21=0 // r21 <- 0
681 (p6) cmp.eq.unc p6,p0=r21,r0 // p6 <- p6 && (r21 == 0)
682 #endif /* CONFIG_PREEMPT */
683 adds r16=PT(LOADRS)+16,r12
684 adds r17=PT(AR_BSPSTORE)+16,r12
685 adds r18=TI_FLAGS+IA64_TASK_SIZE,r13
687 (p6) ld4 r31=[r18] // load current_thread_info()->flags
688 ld8 r19=[r16],PT(B6)-PT(LOADRS) // load ar.rsc value for "loadrs"
691 ld8 r23=[r17],PT(R9)-PT(AR_BSPSTORE) // load ar.bspstore (may be garbage)
692 ld8 r22=[r16],PT(R8)-PT(B6) // load b6
693 (p6) and r15=TIF_WORK_MASK,r31 // any work other than TIF_SYSCALL_TRACE?
696 mov.m ar.ccv=r0 // clear ar.ccv
697 (p6) cmp4.ne.unc p6,p0=r15, r0 // any special work pending?
698 (p6) br.cond.spnt .work_pending
700 // start restoring the state saved on the kernel stack (struct pt_regs):
703 mov f6=f0 // clear f6
705 ld8.fill r10=[r16],16
706 ld8.fill r11=[r17],16
707 mov f7=f0 // clear f7
709 ld8 r29=[r16],16 // load cr.ipsr
710 ld8 r28=[r17],16 // load cr.iip
711 mov f8=f0 // clear f8
713 ld8 r30=[r16],16 // load cr.ifs
714 ld8 r25=[r17],16 // load ar.unat
715 cmp.eq p9,p0=r0,r0 // set p9 to indicate that we should restore cr.ifs
717 rsm psr.i | psr.ic // initiate turning off of interrupt and interruption collection
718 invala // invalidate ALAT
719 mov f9=f0 // clear f9
721 mov.m ar.ssd=r0 // clear ar.ssd
722 mov.m ar.csd=r0 // clear ar.csd
723 mov f10=f0 // clear f10
725 ld8 r26=[r16],16 // load ar.pfs
726 ld8 r27=[r17],PT(PR)-PT(AR_RSC) // load ar.rsc
727 mov f11=f0 // clear f11
729 ld8 r24=[r16],PT(B0)-PT(AR_RNAT) // load ar.rnat (may be garbage)
730 ld8 r31=[r17],PT(R1)-PT(PR) // load predicates
731 (pUStk) add r14=IA64_TASK_THREAD_ON_USTACK_OFFSET,r13
733 ld8 r21=[r16],PT(R12)-PT(B0) // load b0
734 ld8.fill r1=[r17],16 // load r1
737 ld8.fill r12=[r16],16
738 ld8.fill r13=[r17],16
739 mov r2=r0 // clear r2
741 ld8 r20=[r16] // load ar.fpsr
742 ld8.fill r15=[r17] // load r15
743 mov b7=r0 // clear b7
746 addl r17=THIS_CPU(ia64_phys_stacked_size_p8),r0
748 mov r16=ar.bsp // get existing backing store pointer
749 srlz.i // ensure interruption collection is off
750 mov r14=r0 // clear r14
752 ld4 r17=[r17] // r17 = cpu_data->phys_stacked_size_p8
753 mov b6=r22 // restore b6
754 shr.u r18=r19,16 // get byte size of existing "dirty" partition
755 (pKStk) br.cond.dpnt.many skip_rbs_switch
756 (pNonSys) br.cond.dpnt.many dont_preserve_current_frame
757 br.cond.sptk.many rbs_switch
758 END(ia64_leave_syscall)
760 #ifdef CONFIG_IA32_SUPPORT
761 GLOBAL_ENTRY(ia64_ret_from_ia32_execve)
762 PT_REGS_UNWIND_INFO(0)
763 adds r2=PT(R8)+16,sp // r2 = &pt_regs.r8
764 adds r3=PT(R10)+16,sp // r3 = &pt_regs.r10
767 st8.spill [r2]=r8 // store return value in slot for r8 and set unat bit
769 st8.spill [r3]=r0 // clear error indication in slot for r10 and set unat bit
770 END(ia64_ret_from_ia32_execve_syscall)
772 #endif /* CONFIG_IA32_SUPPORT */
773 GLOBAL_ENTRY(ia64_leave_kernel)
774 PT_REGS_UNWIND_INFO(0)
776 * work.need_resched etc. mustn't get changed by this CPU before it returns to
777 * user- or fsys-mode, hence we disable interrupts early on:
779 #ifdef CONFIG_PREEMPT
780 rsm psr.i // disable interrupts
784 cmp.eq p0,pLvSys=r0,r0 // pLvSys=0: leave from kernel
785 (pUStk) cmp.eq.unc p6,p0=r0,r0 // p6 <- pUStk
787 .work_processed_kernel:
788 #ifdef CONFIG_PREEMPT
789 adds r20=TI_PRE_COUNT+IA64_TASK_SIZE,r13
791 .pred.rel.mutex pUStk,pKStk
792 (pKStk) ld4 r21=[r20] // r21 <- preempt_count
793 (pUStk) mov r21=0 // r21 <- 0
795 (p6) cmp.eq.unc p6,p0=r21,r0 // p6 <- p6 && (r21 == 0)
796 #endif /* CONFIG_PREEMPT */
797 adds r17=TI_FLAGS+IA64_TASK_SIZE,r13
799 (p6) ld4 r31=[r17] // load current_thread_info()->flags
800 adds r21=PT(PR)+16,r12
803 lfetch [r21],PT(CR_IPSR)-PT(PR)
804 adds r2=PT(B6)+16,r12
805 adds r3=PT(R16)+16,r12
808 ld8 r28=[r2],8 // load b6
809 adds r29=PT(R24)+16,r12
811 ld8.fill r16=[r3],PT(AR_CSD)-PT(R16)
812 adds r30=PT(AR_CCV)+16,r12
813 (p6) and r19=TIF_WORK_MASK,r31 // any work other than TIF_SYSCALL_TRACE?
816 ld8 r15=[r30] // load ar.ccv
817 (p6) cmp4.ne.unc p6,p0=r19, r0 // any special work pending?
819 ld8 r29=[r2],16 // load b7
820 ld8 r30=[r3],16 // load ar.csd
821 (p6) br.cond.spnt .work_pending
823 ld8 r31=[r2],16 // load ar.ssd
827 ld8.fill r10=[r3],PT(R17)-PT(R10)
829 ld8.fill r11=[r2],PT(R18)-PT(R11)
840 rsm psr.i | psr.ic // initiate turning off of interrupt and interruption collection
841 invala // invalidate ALAT
857 ld8.fill r31=[r2],PT(F9)-PT(R31)
858 adds r3=PT(F10)-PT(F6),r3
860 ldf.fill f9=[r2],PT(F6)-PT(F9)
861 ldf.fill f10=[r3],PT(F8)-PT(F10)
863 ldf.fill f6=[r2],PT(F7)-PT(F6)
865 ldf.fill f7=[r2],PT(F11)-PT(F7)
868 srlz.i // ensure interruption collection is off
871 bsw.0 // switch back to bank 0 (no stop bit required beforehand...)
874 (pUStk) mov r18=IA64_KR(CURRENT) // Itanium 2: 12 cycle read latency
875 adds r16=PT(CR_IPSR)+16,r12
876 adds r17=PT(CR_IIP)+16,r12
878 ld8 r29=[r16],16 // load cr.ipsr
879 ld8 r28=[r17],16 // load cr.iip
881 ld8 r30=[r16],16 // load cr.ifs
882 ld8 r25=[r17],16 // load ar.unat
884 ld8 r26=[r16],16 // load ar.pfs
885 ld8 r27=[r17],16 // load ar.rsc
886 cmp.eq p9,p0=r0,r0 // set p9 to indicate that we should restore cr.ifs
888 ld8 r24=[r16],16 // load ar.rnat (may be garbage)
889 ld8 r23=[r17],16// load ar.bspstore (may be garbage)
891 ld8 r31=[r16],16 // load predicates
892 ld8 r21=[r17],16 // load b0
894 ld8 r19=[r16],16 // load ar.rsc value for "loadrs"
895 ld8.fill r1=[r17],16 // load r1
897 ld8.fill r12=[r16],16
898 ld8.fill r13=[r17],16
899 (pUStk) adds r18=IA64_TASK_THREAD_ON_USTACK_OFFSET,r18
901 ld8 r20=[r16],16 // ar.fpsr
902 ld8.fill r15=[r17],16
904 ld8.fill r14=[r16],16
909 (pUStk) st1 [r18]=r17 // restore current->thread.on_ustack
910 shr.u r18=r19,16 // get byte size of existing "dirty" partition
912 mov r16=ar.bsp // get existing backing store pointer
913 addl r17=THIS_CPU(ia64_phys_stacked_size_p8),r0
915 ld4 r17=[r17] // r17 = cpu_data->phys_stacked_size_p8
916 (pKStk) br.cond.dpnt skip_rbs_switch
919 * Restore user backing store.
921 * NOTE: alloc, loadrs, and cover can't be predicated.
923 (pNonSys) br.cond.dpnt dont_preserve_current_frame
926 cover // add current frame into dirty partition and set cr.ifs
928 mov r19=ar.bsp // get new backing store pointer
929 sub r16=r16,r18 // krbs = old bsp - size of dirty partition
930 cmp.ne p9,p0=r0,r0 // clear p9 to skip restore of cr.ifs
932 sub r19=r19,r16 // calculate total byte size of dirty partition
933 add r18=64,r18 // don't force in0-in7 into memory...
935 shl r19=r19,16 // shift size of dirty partition into loadrs position
937 dont_preserve_current_frame:
939 * To prevent leaking bits between the kernel and user-space,
940 * we must clear the stacked registers in the "invalid" partition here.
941 * Not pretty, but at least it's fast (3.34 registers/cycle on Itanium,
942 * 5 registers/cycle on McKinley).
946 #ifdef CONFIG_ITANIUM
951 alloc loc0=ar.pfs,2,Nregs-2,2,0
952 shr.u loc1=r18,9 // RNaTslots <= floor(dirtySize / (64*8))
953 sub r17=r17,r18 // r17 = (physStackedSize + 8) - dirtySize
955 mov ar.rsc=r19 // load ar.rsc to be used for "loadrs"
956 shladd in0=loc1,3,r17
960 #ifdef CONFIG_ITANIUM
963 alloc loc0=ar.pfs,2,Nregs-2,2,0
964 cmp.lt pRecurse,p0=Nregs*8,in0 // if more than Nregs regs left to clear, (re)curse
965 add out0=-Nregs*8,in0
967 add out1=1,in1 // increment recursion count
969 nop.b 0 // can't do br.call here because of alloc (WAW on CFM)
978 (pRecurse) br.call.sptk.many b0=rse_clear_invalid
983 cmp.ne pReturn,p0=r0,in1 // if recursion count != 0, we need to do a br.ret
987 (pReturn) br.ret.sptk.many b0
989 #else /* !CONFIG_ITANIUM */
990 alloc loc0=ar.pfs,2,Nregs-2,2,0
991 cmp.lt pRecurse,p0=Nregs*8,in0 // if more than Nregs regs left to clear, (re)curse
992 add out0=-Nregs*8,in0
993 add out1=1,in1 // increment recursion count
1002 (pRecurse) br.call.sptk.few b0=rse_clear_invalid
1006 cmp.ne pReturn,p0=r0,in1 // if recursion count != 0, we need to do a br.ret
1009 (pReturn) br.ret.sptk.many b0
1010 #endif /* !CONFIG_ITANIUM */
1014 alloc r17=ar.pfs,0,0,0,0 // drop current register frame
1019 (pLvSys) mov r19=r0 // clear r19 for leave_syscall, no-op otherwise
1022 (pUStk) mov ar.bspstore=r23
1024 (pLvSys)mov r16=r0 // clear r16 for leave_syscall, no-op otherwise
1027 (pLvSys)mov r17=r0 // clear r17 for leave_syscall, no-op otherwise
1030 (pUStk) mov ar.rnat=r24 // must happen with RSE in lazy mode
1031 (pLvSys)mov r18=r0 // clear r18 for leave_syscall, no-op otherwise
1039 * r20 = ¤t->thread_info->pre_count (if CONFIG_PREEMPT)
1040 * r31 = current->thread_info->flags
1042 * p6 = TRUE if work-pending-check needs to be redone
1045 tbit.z p6,p0=r31,TIF_NEED_RESCHED // current_thread_info()->need_resched==0?
1046 (p6) br.cond.sptk.few .notify
1047 #ifdef CONFIG_PREEMPT
1048 (pKStk) dep r21=-1,r0,PREEMPT_ACTIVE_BIT,1
1050 (pKStk) st4 [r20]=r21
1051 ssm psr.i // enable interrupts
1053 br.call.spnt.many rp=schedule
1054 .ret9: cmp.eq p6,p0=r0,r0 // p6 <- 1
1055 rsm psr.i // disable interrupts
1057 #ifdef CONFIG_PREEMPT
1058 (pKStk) adds r20=TI_PRE_COUNT+IA64_TASK_SIZE,r13
1060 (pKStk) st4 [r20]=r0 // preempt_count() <- 0
1062 (pLvSys)br.cond.sptk.many .work_processed_syscall // re-check
1063 br.cond.sptk.many .work_processed_kernel // re-check
1066 br.call.spnt.many rp=notify_resume_user
1067 .ret10: cmp.ne p6,p0=r0,r0 // p6 <- 0
1068 (pLvSys)br.cond.sptk.many .work_processed_syscall // don't re-check
1069 br.cond.sptk.many .work_processed_kernel // don't re-check
1070 END(ia64_leave_kernel)
1072 ENTRY(handle_syscall_error)
1074 * Some system calls (e.g., ptrace, mmap) can return arbitrary values which could
1075 * lead us to mistake a negative return value as a failed syscall. Those syscall
1076 * must deposit a non-zero value in pt_regs.r8 to indicate an error. If
1077 * pt_regs.r8 is zero, we assume that the call completed successfully.
1079 PT_REGS_UNWIND_INFO(0)
1080 ld8 r3=[r2] // load pt_regs.r8
1081 sub r9=0,r8 // negate return value to get errno
1083 mov r10=-1 // return -1 in pt_regs.r10 to indicate error
1084 cmp.eq p6,p7=r3,r0 // is pt_regs.r8==0?
1085 adds r3=16,r2 // r3=&pt_regs.r10
1090 .mem.offset 0,0; st8.spill [r2]=r9 // store errno in pt_regs.r8 and set unat bit
1091 .mem.offset 8,0; st8.spill [r3]=r10 // store error indication in pt_regs.r10 and set unat bit
1092 br.cond.sptk ia64_leave_syscall
1093 END(handle_syscall_error)
1096 * Invoke schedule_tail(task) while preserving in0-in7, which may be needed
1097 * in case a system call gets restarted.
1099 GLOBAL_ENTRY(ia64_invoke_schedule_tail)
1100 .prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(8)
1101 alloc loc1=ar.pfs,8,2,1,0
1103 mov out0=r8 // Address of previous task
1105 br.call.sptk.many rp=schedule_tail
1106 .ret11: mov ar.pfs=loc1
1109 END(ia64_invoke_schedule_tail)
1112 * Setup stack and call do_notify_resume_user(). Note that pSys and pNonSys need to
1113 * be set up by the caller. We declare 8 input registers so the system call
1114 * args get preserved, in case we need to restart a system call.
1116 ENTRY(notify_resume_user)
1117 .prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(8)
1118 alloc loc1=ar.pfs,8,2,3,0 // preserve all eight input regs in case of syscall restart!
1120 mov loc0=rp // save return address
1121 mov out0=0 // there is no "oldset"
1122 adds out1=8,sp // out1=&sigscratch->ar_pfs
1123 (pSys) mov out2=1 // out2==1 => we're in a syscall
1125 (pNonSys) mov out2=0 // out2==0 => not a syscall
1127 .spillpsp ar.unat, 16 // (note that offset is relative to psp+0x10!)
1128 st8 [sp]=r9,-16 // allocate space for ar.unat and save it
1129 st8 [out1]=loc1,-8 // save ar.pfs, out1=&sigscratch
1131 br.call.sptk.many rp=do_notify_resume_user
1133 adds sp=16,sp // pop scratch stack space
1135 ld8 r9=[sp] // load new unat from sigscratch->scratch_unat
1141 END(notify_resume_user)
1143 GLOBAL_ENTRY(sys_rt_sigsuspend)
1144 .prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(8)
1145 alloc loc1=ar.pfs,8,2,3,0 // preserve all eight input regs in case of syscall restart!
1147 mov loc0=rp // save return address
1148 mov out0=in0 // mask
1149 mov out1=in1 // sigsetsize
1150 adds out2=8,sp // out2=&sigscratch->ar_pfs
1153 .spillpsp ar.unat, 16 // (note that offset is relative to psp+0x10!)
1154 st8 [sp]=r9,-16 // allocate space for ar.unat and save it
1155 st8 [out2]=loc1,-8 // save ar.pfs, out2=&sigscratch
1157 br.call.sptk.many rp=ia64_rt_sigsuspend
1159 adds sp=16,sp // pop scratch stack space
1161 ld8 r9=[sp] // load new unat from sw->caller_unat
1167 END(sys_rt_sigsuspend)
1169 ENTRY(sys_rt_sigreturn)
1170 PT_REGS_UNWIND_INFO(0)
1171 alloc r2=ar.pfs,0,0,1,0
1176 cmp.eq pNonSys,pSys=r0,r0 // sigreturn isn't a normal syscall...
1179 * leave_kernel() restores f6-f11 from pt_regs, but since the streamlined
1180 * syscall-entry path does not save them we save them here instead. Note: we
1181 * don't need to save any other registers that are not saved by the stream-lined
1182 * syscall path, because restore_sigcontext() restores them.
1184 adds r16=PT(F6)+32,sp
1185 adds r17=PT(F7)+32,sp
1187 stf.spill [r16]=f6,32
1188 stf.spill [r17]=f7,32
1190 stf.spill [r16]=f8,32
1191 stf.spill [r17]=f9,32
1195 adds out0=16,sp // out0 = &sigscratch
1196 br.call.sptk.many rp=ia64_rt_sigreturn
1197 .ret19: .restore sp 0
1200 ld8 r9=[sp] // load new ar.unat
1201 mov.sptk b7=r8,ia64_leave_kernel
1205 END(sys_rt_sigreturn)
1207 GLOBAL_ENTRY(ia64_prepare_handle_unaligned)
1210 * r16 = fake ar.pfs, we simply need to make sure privilege is still 0
1213 DO_SAVE_SWITCH_STACK
1214 br.call.sptk.many rp=ia64_handle_unaligned // stack frame setup in ivt
1216 DO_LOAD_SWITCH_STACK
1217 br.cond.sptk.many rp // goes to ia64_leave_kernel
1218 END(ia64_prepare_handle_unaligned)
1221 // unw_init_running(void (*callback)(info, arg), void *arg)
1223 # define EXTRA_FRAME_SIZE ((UNW_FRAME_INFO_SIZE+15)&~15)
1225 GLOBAL_ENTRY(unw_init_running)
1226 .prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(2)
1227 alloc loc1=ar.pfs,2,3,3,0
1232 DO_SAVE_SWITCH_STACK
1235 .prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(2)
1236 .fframe IA64_SWITCH_STACK_SIZE+EXTRA_FRAME_SIZE
1237 SWITCH_STACK_SAVES(EXTRA_FRAME_SIZE)
1238 adds sp=-EXTRA_FRAME_SIZE,sp
1241 adds out0=16,sp // &info
1242 mov out1=r13 // current
1243 adds out2=16+EXTRA_FRAME_SIZE,sp // &switch_stack
1244 br.call.sptk.many rp=unw_init_frame_info
1245 1: adds out0=16,sp // &info
1247 mov loc2=gp // save gp across indirect function call
1251 br.call.sptk.many rp=b6 // invoke the callback function
1252 1: mov gp=loc2 // restore gp
1254 // For now, we don't allow changing registers from within
1255 // unw_init_running; if we ever want to allow that, we'd
1256 // have to do a load_switch_stack here:
1258 adds sp=IA64_SWITCH_STACK_SIZE+EXTRA_FRAME_SIZE,sp
1263 END(unw_init_running)
1267 .globl sys_call_table
1269 data8 sys_ni_syscall // This must be sys_ni_syscall! See ivt.S.
1270 data8 sys_exit // 1025
1275 data8 sys_creat // 1030
1280 data8 sys_fchdir // 1035
1285 data8 sys_lseek // 1040
1290 data8 sys_setuid // 1045
1295 data8 sys_sync // 1050
1300 data8 sys_mkdir // 1055
1305 data8 ia64_brk // 1060
1310 data8 sys_ioctl // 1065
1315 data8 sys_dup2 // 1070
1320 data8 sys_getresgid // 1075
1325 data8 sys_setpgid // 1080
1328 data8 sys_sethostname
1330 data8 sys_getrlimit // 1085
1332 data8 sys_gettimeofday
1333 data8 sys_settimeofday
1335 data8 sys_poll // 1090
1340 data8 sys_swapoff // 1095
1345 data8 sys_fchown // 1100
1346 data8 ia64_getpriority
1347 data8 sys_setpriority
1350 data8 sys_gettid // 1105
1355 data8 sys_msgsnd // 1110
1360 data8 sys_shmdt // 1115
1365 data8 sys_ni_syscall // 1120 /* was: ia64_oldstat */
1366 data8 sys_ni_syscall /* was: ia64_oldlstat */
1367 data8 sys_ni_syscall /* was: ia64_oldfstat */
1370 data8 sys_remap_file_pages // 1125
1374 data8 sys_setdomainname
1375 data8 sys_newuname // 1130
1377 data8 sys_ni_syscall /* was: ia64_create_module */
1378 data8 sys_init_module
1379 data8 sys_delete_module
1380 data8 sys_ni_syscall // 1135 /* was: sys_get_kernel_syms */
1381 data8 sys_ni_syscall /* was: sys_query_module */
1385 data8 sys_personality // 1140
1386 data8 sys_ni_syscall // sys_afs_syscall
1390 data8 sys_flock // 1145
1395 data8 sys_sysctl // 1150
1400 data8 sys_mprotect // 1155
1404 data8 sys_munlockall
1405 data8 sys_sched_getparam // 1160
1406 data8 sys_sched_setparam
1407 data8 sys_sched_getscheduler
1408 data8 sys_sched_setscheduler
1409 data8 sys_sched_yield
1410 data8 sys_sched_get_priority_max // 1165
1411 data8 sys_sched_get_priority_min
1412 data8 sys_sched_rr_get_interval
1414 data8 sys_nfsservctl
1415 data8 sys_prctl // 1170
1416 data8 sys_getpagesize
1418 data8 sys_pciconfig_read
1419 data8 sys_pciconfig_write
1420 data8 sys_perfmonctl // 1175
1421 data8 sys_sigaltstack
1422 data8 sys_rt_sigaction
1423 data8 sys_rt_sigpending
1424 data8 sys_rt_sigprocmask
1425 data8 sys_rt_sigqueueinfo // 1180
1426 data8 sys_rt_sigreturn
1427 data8 sys_rt_sigsuspend
1428 data8 sys_rt_sigtimedwait
1430 data8 sys_capget // 1185
1432 data8 sys_sendfile64
1433 data8 sys_ni_syscall // sys_getpmsg (STREAMS)
1434 data8 sys_ni_syscall // sys_putpmsg (STREAMS)
1435 data8 sys_socket // 1190
1440 data8 sys_getsockname // 1195
1441 data8 sys_getpeername
1442 data8 sys_socketpair
1445 data8 sys_recv // 1200
1448 data8 sys_setsockopt
1449 data8 sys_getsockopt
1450 data8 sys_sendmsg // 1205
1452 data8 sys_pivot_root
1455 data8 sys_newstat // 1210
1459 data8 sys_getdents64
1460 data8 sys_getunwind // 1215
1465 data8 sys_getxattr // 1220
1469 data8 sys_llistxattr
1470 data8 sys_flistxattr // 1225
1471 data8 sys_removexattr
1472 data8 sys_lremovexattr
1473 data8 sys_fremovexattr
1475 data8 sys_futex // 1230
1476 data8 sys_sched_setaffinity
1477 data8 sys_sched_getaffinity
1478 data8 sys_set_tid_address
1479 data8 sys_fadvise64_64
1480 data8 sys_tgkill // 1235
1481 data8 sys_exit_group
1482 data8 sys_lookup_dcookie
1484 data8 sys_io_destroy
1485 data8 sys_io_getevents // 1240
1488 data8 sys_epoll_create
1490 data8 sys_epoll_wait // 1245
1491 data8 sys_restart_syscall
1492 data8 sys_semtimedop
1493 data8 sys_timer_create
1494 data8 sys_timer_settime
1495 data8 sys_timer_gettime // 1250
1496 data8 sys_timer_getoverrun
1497 data8 sys_timer_delete
1498 data8 sys_clock_settime
1499 data8 sys_clock_gettime
1500 data8 sys_clock_getres // 1255
1501 data8 sys_clock_nanosleep
1505 data8 sys_get_mempolicy // 1260
1506 data8 sys_set_mempolicy
1509 data8 sys_mq_timedsend
1510 data8 sys_mq_timedreceive // 1265
1512 data8 sys_mq_getsetattr
1513 data8 sys_ni_syscall // reserved for kexec_load
1515 data8 sys_ni_syscall // 1270
1516 data8 sys_ni_syscall
1517 data8 sys_ni_syscall
1518 data8 sys_ni_syscall
1519 data8 sys_ni_syscall
1520 data8 sys_ni_syscall // 1275
1521 data8 sys_ni_syscall
1522 data8 sys_ni_syscall
1523 data8 sys_ni_syscall
1524 data8 sys_ni_syscall
1526 .org sys_call_table + 8*NR_syscalls // guard against failures to increase NR_syscalls