4 * Copyright (C) 1999 Intel Corp.
5 * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
6 * Copyright (C) 2000-2002 J.I. Lee <jung-ik.lee@intel.com>
7 * Copyright (C) 1999-2000, 2002-2003 Hewlett-Packard Co.
8 * David Mosberger-Tang <davidm@hpl.hp.com>
9 * Copyright (C) 1999 VA Linux Systems
10 * Copyright (C) 1999,2000 Walt Drummond <drummond@valinux.com>
12 * 00/04/19 D. Mosberger Rewritten to mirror more closely the x86 I/O APIC code.
13 * In particular, we now have separate handlers for edge
14 * and level triggered interrupts.
15 * 00/10/27 Asit Mallick, Goutham Rao <goutham.rao@intel.com> IRQ vector allocation
16 * PCI to vector mapping, shared PCI interrupts.
17 * 00/10/27 D. Mosberger Document things a bit more to make them more understandable.
18 * Clean up much of the old IOSAPIC cruft.
19 * 01/07/27 J.I. Lee PCI irq routing, Platform/Legacy interrupts and fixes for
20 * ACPI S5(SoftOff) support.
21 * 02/01/23 J.I. Lee iosapic pgm fixes for PCI irq routing from _PRT
22 * 02/01/07 E. Focht <efocht@ess.nec.de> Redirectable interrupt vectors in
23 * iosapic_set_affinity(), initializations for
24 * /proc/irq/#/smp_affinity
25 * 02/04/02 P. Diefenbaugh Cleaned up ACPI PCI IRQ routing.
26 * 02/04/18 J.I. Lee bug fix in iosapic_init_pci_irq
27 * 02/04/30 J.I. Lee bug fix in find_iosapic to fix ACPI PCI IRQ to IOSAPIC mapping
29 * 02/07/29 T. Kochi Allocate interrupt vectors dynamically
30 * 02/08/04 T. Kochi Cleaned up terminology (irq, global system interrupt, vector, etc.)
31 * 02/09/20 D. Mosberger Simplified by taking advantage of ACPI's pci_irq code.
32 * 03/02/19 B. Helgaas Make pcat_compat system-wide, not per-IOSAPIC.
33 * Remove iosapic_address & gsi_base from external interfaces.
34 * Rationalize __init/__devinit attributes.
35 * 04/12/04 Ashok Raj <ashok.raj@intel.com> Intel Corporation 2004
36 * Updated to work with irq migration necessary for CPU Hotplug
39 * Here is what the interrupt logic between a PCI device and the kernel looks like:
41 * (1) A PCI device raises one of the four interrupt pins (INTA, INTB, INTC, INTD). The
42 * device is uniquely identified by its bus--, and slot-number (the function
43 * number does not matter here because all functions share the same interrupt
46 * (2) The motherboard routes the interrupt line to a pin on a IOSAPIC controller.
47 * Multiple interrupt lines may have to share the same IOSAPIC pin (if they're level
48 * triggered and use the same polarity). Each interrupt line has a unique Global
49 * System Interrupt (GSI) number which can be calculated as the sum of the controller's
50 * base GSI number and the IOSAPIC pin number to which the line connects.
52 * (3) The IOSAPIC uses an internal routing table entries (RTEs) to map the IOSAPIC pin
53 * into the IA-64 interrupt vector. This interrupt vector is then sent to the CPU.
55 * (4) The kernel recognizes an interrupt as an IRQ. The IRQ interface is used as
56 * architecture-independent interrupt handling mechanism in Linux. As an
57 * IRQ is a number, we have to have IA-64 interrupt vector number <-> IRQ number
58 * mapping. On smaller systems, we use one-to-one mapping between IA-64 vector and
59 * IRQ. A platform can implement platform_irq_to_vector(irq) and
60 * platform_local_vector_to_irq(vector) APIs to differentiate the mapping.
61 * Please see also include/asm-ia64/hw_irq.h for those APIs.
63 * To sum up, there are three levels of mappings involved:
65 * PCI pin -> global system interrupt (GSI) -> IA-64 vector <-> IRQ
67 * Note: The term "IRQ" is loosely used everywhere in Linux kernel to describe interrupts.
68 * Now we use "IRQ" only for Linux IRQ's. ISA IRQ (isa_irq) is the only exception in this
71 #include <linux/config.h>
73 #include <linux/acpi.h>
74 #include <linux/init.h>
75 #include <linux/irq.h>
76 #include <linux/kernel.h>
77 #include <linux/list.h>
78 #include <linux/pci.h>
79 #include <linux/smp.h>
80 #include <linux/smp_lock.h>
81 #include <linux/string.h>
83 #include <asm/delay.h>
84 #include <asm/hw_irq.h>
86 #include <asm/iosapic.h>
87 #include <asm/machvec.h>
88 #include <asm/processor.h>
89 #include <asm/ptrace.h>
90 #include <asm/system.h>
93 #undef DEBUG_INTERRUPT_ROUTING
96 #ifdef DEBUG_INTERRUPT_ROUTING
97 #define DBG(fmt...) printk(fmt)
102 static spinlock_t iosapic_lock = SPIN_LOCK_UNLOCKED;
104 /* These tables map IA-64 vectors to the IOSAPIC pin that generates this vector. */
106 static struct iosapic_intr_info {
107 char __iomem *addr; /* base address of IOSAPIC */
108 u32 low32; /* current value of low word of Redirection table entry */
109 unsigned int gsi_base; /* first GSI assigned to this IOSAPIC */
110 char rte_index; /* IOSAPIC RTE index (-1 => not an IOSAPIC interrupt) */
111 unsigned char dmode : 3; /* delivery mode (see iosapic.h) */
112 unsigned char polarity: 1; /* interrupt polarity (see iosapic.h) */
113 unsigned char trigger : 1; /* trigger mode (see iosapic.h) */
114 } iosapic_intr_info[IA64_NUM_VECTORS];
116 static struct iosapic {
117 char __iomem *addr; /* base address of IOSAPIC */
118 unsigned int gsi_base; /* first GSI assigned to this IOSAPIC */
119 unsigned short num_rte; /* number of RTE in this IOSAPIC */
121 unsigned short node; /* numa node association via pxm */
123 } iosapic_lists[NR_IOSAPICS];
125 static int num_iosapic;
127 static unsigned char pcat_compat __initdata; /* 8259 compatibility flag */
131 * Find an IOSAPIC associated with a GSI
134 find_iosapic (unsigned int gsi)
138 for (i = 0; i < num_iosapic; i++) {
139 if ((unsigned) (gsi - iosapic_lists[i].gsi_base) < iosapic_lists[i].num_rte)
147 _gsi_to_vector (unsigned int gsi)
149 struct iosapic_intr_info *info;
151 for (info = iosapic_intr_info; info < iosapic_intr_info + IA64_NUM_VECTORS; ++info)
152 if (info->gsi_base + info->rte_index == gsi)
153 return info - iosapic_intr_info;
158 * Translate GSI number to the corresponding IA-64 interrupt vector. If no
159 * entry exists, return -1.
162 gsi_to_vector (unsigned int gsi)
164 return _gsi_to_vector(gsi);
168 gsi_to_irq (unsigned int gsi)
171 * XXX fix me: this assumes an identity mapping vetween IA-64 vector and Linux irq
174 return _gsi_to_vector(gsi);
178 set_rte (unsigned int vector, unsigned int dest, int mask)
180 unsigned long pol, trigger, dmode, flags;
186 DBG(KERN_DEBUG"IOSAPIC: routing vector %d to 0x%x\n", vector, dest);
188 rte_index = iosapic_intr_info[vector].rte_index;
190 return; /* not an IOSAPIC interrupt */
192 addr = iosapic_intr_info[vector].addr;
193 pol = iosapic_intr_info[vector].polarity;
194 trigger = iosapic_intr_info[vector].trigger;
195 dmode = iosapic_intr_info[vector].dmode;
196 vector &= (~IA64_IRQ_REDIRECTED);
198 redir = (dmode == IOSAPIC_LOWEST_PRIORITY) ? 1 : 0;
204 for (irq = 0; irq < NR_IRQS; ++irq)
205 if (irq_to_vector(irq) == vector) {
206 set_irq_affinity_info(irq, (int)(dest & 0xffff), redir);
212 low32 = ((pol << IOSAPIC_POLARITY_SHIFT) |
213 (trigger << IOSAPIC_TRIGGER_SHIFT) |
214 (dmode << IOSAPIC_DELIVERY_SHIFT) |
215 ((mask ? 1 : 0) << IOSAPIC_MASK_SHIFT) |
218 /* dest contains both id and eid */
219 high32 = (dest << IOSAPIC_DEST_SHIFT);
221 spin_lock_irqsave(&iosapic_lock, flags);
223 iosapic_write(addr, IOSAPIC_RTE_HIGH(rte_index), high32);
224 iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32);
225 iosapic_intr_info[vector].low32 = low32;
227 spin_unlock_irqrestore(&iosapic_lock, flags);
231 nop (unsigned int vector)
237 mask_irq (unsigned int irq)
243 ia64_vector vec = irq_to_vector(irq);
245 addr = iosapic_intr_info[vec].addr;
246 rte_index = iosapic_intr_info[vec].rte_index;
249 return; /* not an IOSAPIC interrupt! */
251 spin_lock_irqsave(&iosapic_lock, flags);
253 /* set only the mask bit */
254 low32 = iosapic_intr_info[vec].low32 |= IOSAPIC_MASK;
255 iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32);
257 spin_unlock_irqrestore(&iosapic_lock, flags);
261 unmask_irq (unsigned int irq)
267 ia64_vector vec = irq_to_vector(irq);
269 addr = iosapic_intr_info[vec].addr;
270 rte_index = iosapic_intr_info[vec].rte_index;
272 return; /* not an IOSAPIC interrupt! */
274 spin_lock_irqsave(&iosapic_lock, flags);
276 low32 = iosapic_intr_info[vec].low32 &= ~IOSAPIC_MASK;
277 iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32);
279 spin_unlock_irqrestore(&iosapic_lock, flags);
284 iosapic_set_affinity (unsigned int irq, cpumask_t mask)
291 int redir = (irq & IA64_IRQ_REDIRECTED) ? 1 : 0;
294 irq &= (~IA64_IRQ_REDIRECTED);
295 vec = irq_to_vector(irq);
297 if (cpus_empty(mask))
300 dest = cpu_physical_id(first_cpu(mask));
302 rte_index = iosapic_intr_info[vec].rte_index;
303 addr = iosapic_intr_info[vec].addr;
306 return; /* not an IOSAPIC interrupt */
308 set_irq_affinity_info(irq, dest, redir);
310 /* dest contains both id and eid */
311 high32 = dest << IOSAPIC_DEST_SHIFT;
313 spin_lock_irqsave(&iosapic_lock, flags);
315 low32 = iosapic_intr_info[vec].low32 & ~(7 << IOSAPIC_DELIVERY_SHIFT);
318 /* change delivery mode to lowest priority */
319 low32 |= (IOSAPIC_LOWEST_PRIORITY << IOSAPIC_DELIVERY_SHIFT);
321 /* change delivery mode to fixed */
322 low32 |= (IOSAPIC_FIXED << IOSAPIC_DELIVERY_SHIFT);
324 iosapic_intr_info[vec].low32 = low32;
325 iosapic_write(addr, IOSAPIC_RTE_HIGH(rte_index), high32);
326 iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32);
328 spin_unlock_irqrestore(&iosapic_lock, flags);
333 * Handlers for level-triggered interrupts.
337 iosapic_startup_level_irq (unsigned int irq)
344 iosapic_end_level_irq (unsigned int irq)
346 ia64_vector vec = irq_to_vector(irq);
349 iosapic_eoi(iosapic_intr_info[vec].addr, vec);
352 #define iosapic_shutdown_level_irq mask_irq
353 #define iosapic_enable_level_irq unmask_irq
354 #define iosapic_disable_level_irq mask_irq
355 #define iosapic_ack_level_irq nop
357 struct hw_interrupt_type irq_type_iosapic_level = {
358 .typename = "IO-SAPIC-level",
359 .startup = iosapic_startup_level_irq,
360 .shutdown = iosapic_shutdown_level_irq,
361 .enable = iosapic_enable_level_irq,
362 .disable = iosapic_disable_level_irq,
363 .ack = iosapic_ack_level_irq,
364 .end = iosapic_end_level_irq,
365 .set_affinity = iosapic_set_affinity
369 * Handlers for edge-triggered interrupts.
373 iosapic_startup_edge_irq (unsigned int irq)
377 * IOSAPIC simply drops interrupts pended while the
378 * corresponding pin was masked, so we can't know if an
379 * interrupt is pending already. Let's hope not...
385 iosapic_ack_edge_irq (unsigned int irq)
387 irq_desc_t *idesc = irq_descp(irq);
391 * Once we have recorded IRQ_PENDING already, we can mask the
392 * interrupt for real. This prevents IRQ storms from unhandled
395 if ((idesc->status & (IRQ_PENDING|IRQ_DISABLED)) == (IRQ_PENDING|IRQ_DISABLED))
399 #define iosapic_enable_edge_irq unmask_irq
400 #define iosapic_disable_edge_irq nop
401 #define iosapic_end_edge_irq nop
403 struct hw_interrupt_type irq_type_iosapic_edge = {
404 .typename = "IO-SAPIC-edge",
405 .startup = iosapic_startup_edge_irq,
406 .shutdown = iosapic_disable_edge_irq,
407 .enable = iosapic_enable_edge_irq,
408 .disable = iosapic_disable_edge_irq,
409 .ack = iosapic_ack_edge_irq,
410 .end = iosapic_end_edge_irq,
411 .set_affinity = iosapic_set_affinity
415 iosapic_version (char __iomem *addr)
418 * IOSAPIC Version Register return 32 bit structure like:
420 * unsigned int version : 8;
421 * unsigned int reserved1 : 8;
422 * unsigned int max_redir : 8;
423 * unsigned int reserved2 : 8;
426 return iosapic_read(addr, IOSAPIC_VERSION);
430 * if the given vector is already owned by other,
431 * assign a new vector for the other and make the vector available
434 iosapic_reassign_vector (int vector)
438 if (iosapic_intr_info[vector].rte_index >= 0 || iosapic_intr_info[vector].addr
439 || iosapic_intr_info[vector].gsi_base || iosapic_intr_info[vector].dmode
440 || iosapic_intr_info[vector].polarity || iosapic_intr_info[vector].trigger)
442 new_vector = assign_irq_vector(AUTO_ASSIGN);
443 printk(KERN_INFO "Reassigning vector %d to %d\n", vector, new_vector);
444 memcpy(&iosapic_intr_info[new_vector], &iosapic_intr_info[vector],
445 sizeof(struct iosapic_intr_info));
446 memset(&iosapic_intr_info[vector], 0, sizeof(struct iosapic_intr_info));
447 iosapic_intr_info[vector].rte_index = -1;
452 register_intr (unsigned int gsi, int vector, unsigned char delivery,
453 unsigned long polarity, unsigned long trigger)
456 struct hw_interrupt_type *irq_type;
459 unsigned long gsi_base;
460 void __iomem *iosapic_address;
462 index = find_iosapic(gsi);
464 printk(KERN_WARNING "%s: No IOSAPIC for GSI %u\n", __FUNCTION__, gsi);
468 iosapic_address = iosapic_lists[index].addr;
469 gsi_base = iosapic_lists[index].gsi_base;
471 rte_index = gsi - gsi_base;
472 iosapic_intr_info[vector].rte_index = rte_index;
473 iosapic_intr_info[vector].polarity = polarity;
474 iosapic_intr_info[vector].dmode = delivery;
475 iosapic_intr_info[vector].addr = iosapic_address;
476 iosapic_intr_info[vector].gsi_base = gsi_base;
477 iosapic_intr_info[vector].trigger = trigger;
479 if (trigger == IOSAPIC_EDGE)
480 irq_type = &irq_type_iosapic_edge;
482 irq_type = &irq_type_iosapic_level;
484 idesc = irq_descp(vector);
485 if (idesc->handler != irq_type) {
486 if (idesc->handler != &no_irq_type)
487 printk(KERN_WARNING "%s: changing vector %d from %s to %s\n",
488 __FUNCTION__, vector, idesc->handler->typename, irq_type->typename);
489 idesc->handler = irq_type;
494 get_target_cpu (unsigned int gsi, int vector)
500 * If the platform supports redirection via XTP, let it
501 * distribute interrupts.
503 if (smp_int_redirect & SMP_IRQ_REDIRECTION)
504 return hard_smp_processor_id();
507 * Some interrupts (ACPI SCI, for instance) are registered
508 * before the BSP is marked as online.
510 if (!cpu_online(smp_processor_id()))
511 return hard_smp_processor_id();
515 int num_cpus, cpu_index, iosapic_index, numa_cpu, i = 0;
518 iosapic_index = find_iosapic(gsi);
519 if (iosapic_index < 0 ||
520 iosapic_lists[iosapic_index].node == MAX_NUMNODES)
521 goto skip_numa_setup;
523 cpu_mask = node_to_cpumask(iosapic_lists[iosapic_index].node);
525 for_each_cpu_mask(numa_cpu, cpu_mask) {
526 if (!cpu_online(numa_cpu))
527 cpu_clear(numa_cpu, cpu_mask);
530 num_cpus = cpus_weight(cpu_mask);
533 goto skip_numa_setup;
535 /* Use vector assigment to distribute across cpus in node */
536 cpu_index = vector % num_cpus;
538 for (numa_cpu = first_cpu(cpu_mask) ; i < cpu_index ; i++)
539 numa_cpu = next_cpu(numa_cpu, cpu_mask);
541 if (numa_cpu != NR_CPUS)
542 return cpu_physical_id(numa_cpu);
547 * Otherwise, round-robin interrupt vectors across all the
548 * processors. (It'd be nice if we could be smarter in the
552 if (++cpu >= NR_CPUS)
554 } while (!cpu_online(cpu));
556 return cpu_physical_id(cpu);
558 return hard_smp_processor_id();
563 * ACPI can describe IOSAPIC interrupts via static tables and namespace
564 * methods. This provides an interface to register those interrupts and
565 * program the IOSAPIC RTE.
568 iosapic_register_intr (unsigned int gsi,
569 unsigned long polarity, unsigned long trigger)
576 * If this GSI has already been registered (i.e., it's a
577 * shared interrupt, or we lost a race to register it),
578 * don't touch the RTE.
580 spin_lock_irqsave(&iosapic_lock, flags);
582 vector = gsi_to_vector(gsi);
584 spin_unlock_irqrestore(&iosapic_lock, flags);
588 vector = assign_irq_vector(AUTO_ASSIGN);
589 dest = get_target_cpu(gsi, vector);
590 register_intr(gsi, vector, IOSAPIC_LOWEST_PRIORITY,
593 spin_unlock_irqrestore(&iosapic_lock, flags);
595 printk(KERN_INFO "GSI %u (%s, %s) -> CPU %d (0x%04x) vector %d\n",
596 gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"),
597 (polarity == IOSAPIC_POL_HIGH ? "high" : "low"),
598 cpu_logical_id(dest), dest, vector);
600 set_rte(vector, dest, 1);
605 * ACPI calls this when it finds an entry for a platform interrupt.
606 * Note that the irq_base and IOSAPIC address must be set in iosapic_init().
609 iosapic_register_platform_intr (u32 int_type, unsigned int gsi,
610 int iosapic_vector, u16 eid, u16 id,
611 unsigned long polarity, unsigned long trigger)
613 static const char * const name[] = {"unknown", "PMI", "INIT", "CPEI"};
614 unsigned char delivery;
615 int vector, mask = 0;
616 unsigned int dest = ((id << 8) | eid) & 0xffff;
619 case ACPI_INTERRUPT_PMI:
620 vector = iosapic_vector;
622 * since PMI vector is alloc'd by FW(ACPI) not by kernel,
623 * we need to make sure the vector is available
625 iosapic_reassign_vector(vector);
626 delivery = IOSAPIC_PMI;
628 case ACPI_INTERRUPT_INIT:
629 vector = assign_irq_vector(AUTO_ASSIGN);
630 delivery = IOSAPIC_INIT;
632 case ACPI_INTERRUPT_CPEI:
633 vector = IA64_CPE_VECTOR;
634 delivery = IOSAPIC_LOWEST_PRIORITY;
638 printk(KERN_ERR "iosapic_register_platform_irq(): invalid int type 0x%x\n", int_type);
642 register_intr(gsi, vector, delivery, polarity, trigger);
644 printk(KERN_INFO "PLATFORM int %s (0x%x): GSI %u (%s, %s) -> CPU %d (0x%04x) vector %d\n",
645 int_type < ARRAY_SIZE(name) ? name[int_type] : "unknown",
646 int_type, gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"),
647 (polarity == IOSAPIC_POL_HIGH ? "high" : "low"),
648 cpu_logical_id(dest), dest, vector);
650 set_rte(vector, dest, mask);
656 * ACPI calls this when it finds an entry for a legacy ISA IRQ override.
657 * Note that the gsi_base and IOSAPIC address must be set in iosapic_init().
660 iosapic_override_isa_irq (unsigned int isa_irq, unsigned int gsi,
661 unsigned long polarity,
662 unsigned long trigger)
665 unsigned int dest = hard_smp_processor_id();
667 vector = isa_irq_to_vector(isa_irq);
669 register_intr(gsi, vector, IOSAPIC_LOWEST_PRIORITY, polarity, trigger);
671 DBG("ISA: IRQ %u -> GSI %u (%s,%s) -> CPU %d (0x%04x) vector %d\n",
672 isa_irq, gsi, trigger == IOSAPIC_EDGE ? "edge" : "level",
673 polarity == IOSAPIC_POL_HIGH ? "high" : "low",
674 cpu_logical_id(dest), dest, vector);
676 set_rte(vector, dest, 1);
680 iosapic_system_init (int system_pcat_compat)
684 for (vector = 0; vector < IA64_NUM_VECTORS; ++vector)
685 iosapic_intr_info[vector].rte_index = -1; /* mark as unused */
687 pcat_compat = system_pcat_compat;
690 * Disable the compatibility mode interrupts (8259 style), needs IN/OUT support
693 printk(KERN_INFO "%s: Disabling PC-AT compatible 8259 interrupts\n", __FUNCTION__);
700 iosapic_init (unsigned long phys_addr, unsigned int gsi_base)
703 unsigned int isa_irq, ver;
706 addr = ioremap(phys_addr, 0);
707 ver = iosapic_version(addr);
710 * The MAX_REDIR register holds the highest input pin
711 * number (starting from 0).
712 * We add 1 so that we can use it for number of pins (= RTEs)
714 num_rte = ((ver >> 16) & 0xff) + 1;
716 iosapic_lists[num_iosapic].addr = addr;
717 iosapic_lists[num_iosapic].gsi_base = gsi_base;
718 iosapic_lists[num_iosapic].num_rte = num_rte;
720 iosapic_lists[num_iosapic].node = MAX_NUMNODES;
724 if ((gsi_base == 0) && pcat_compat) {
726 * Map the legacy ISA devices into the IOSAPIC data. Some of these may
727 * get reprogrammed later on with data from the ACPI Interrupt Source
730 for (isa_irq = 0; isa_irq < 16; ++isa_irq)
731 iosapic_override_isa_irq(isa_irq, isa_irq, IOSAPIC_POL_HIGH, IOSAPIC_EDGE);
737 map_iosapic_to_node(unsigned int gsi_base, int node)
741 index = find_iosapic(gsi_base);
743 printk(KERN_WARNING "%s: No IOSAPIC for GSI %u\n",
744 __FUNCTION__, gsi_base);
747 iosapic_lists[index].node = node;