arch/ia64/kernel/mca.c

   1 /*
   2  * File:        mca.c
   3  * Purpose:     Generic MCA handling layer
   4  *
   5  * Updated for latest kernel
   6  * Copyright (C) 2003 Hewlett-Packard Co
   7  *      David Mosberger-Tang <davidm@hpl.hp.com>
   8  *
   9  * Copyright (C) 2002 Dell Inc.
  10  * Copyright (C) Matt Domsch (Matt_Domsch@dell.com)
  11  *
  12  * Copyright (C) 2002 Intel
  13  * Copyright (C) Jenna Hall (jenna.s.hall@intel.com)
  14  *
  15  * Copyright (C) 2001 Intel
  16  * Copyright (C) Fred Lewis (frederick.v.lewis@intel.com)
  17  *
  18  * Copyright (C) 2000 Intel
  19  * Copyright (C) Chuck Fleckenstein (cfleck@co.intel.com)
  20  *
  21  * Copyright (C) 1999, 2004 Silicon Graphics, Inc.
  22  * Copyright (C) Vijay Chander(vijay@engr.sgi.com)
  23  *
  24  * 03/04/15 D. Mosberger Added INIT backtrace support.
  25  * 02/03/25 M. Domsch   GUID cleanups
  26  *
  27  * 02/01/04 J. Hall     Aligned MCA stack to 16 bytes, added platform vs. CPU
  28  *                      error flag, set SAL default return values, changed
  29  *                      error record structure to linked list, added init call
  30  *                      to sal_get_state_info_size().
  31  *
  32  * 01/01/03 F. Lewis    Added setup of CMCI and CPEI IRQs, logging of corrected
  33  *                      platform errors, completed code for logging of
  34  *                      corrected & uncorrected machine check errors, and
  35  *                      updated for conformance with Nov. 2000 revision of the
  36  *                      SAL 3.0 spec.
  37  * 00/03/29 C. Fleckenstein  Fixed PAL/SAL update issues, began MCA bug fixes, logging issues,
  38  *                           added min save state dump, added INIT handler.
  39  *
  40  * 2003-12-08 Keith Owens <kaos@sgi.com>
  41  *            smp_call_function() must not be called from interrupt context (can
  42  *            deadlock on tasklist_lock).  Use keventd to call smp_call_function().
  43  *
  44  * 2004-02-01 Keith Owens <kaos@sgi.com>
  45  *            Avoid deadlock when using printk() for MCA and INIT records.
  46  *            Delete all record printing code, moved to salinfo_decode in user space.
  47  *            Mark variables and functions static where possible.
  48  *            Delete dead variables and functions.
  49  *            Reorder to remove the need for forward declarations and to consolidate
  50  *            related code.
  51  */
  52 #include <linux/config.h>
  53 #include <linux/types.h>
  54 #include <linux/init.h>
  55 #include <linux/sched.h>
  56 #include <linux/interrupt.h>
  57 #include <linux/irq.h>
  58 #include <linux/kallsyms.h>
  59 #include <linux/smp_lock.h>
  60 #include <linux/bootmem.h>
  61 #include <linux/acpi.h>
  62 #include <linux/timer.h>
  63 #include <linux/module.h>
  64 #include <linux/kernel.h>
  65 #include <linux/smp.h>
  66 #include <linux/workqueue.h>
  67
  68 #include <asm/delay.h>
  69 #include <asm/machvec.h>
  70 #include <asm/page.h>
  71 #include <asm/ptrace.h>
  72 #include <asm/system.h>
  73 #include <asm/sal.h>
  74 #include <asm/mca.h>
  75
  76 #include <asm/irq.h>
  77 #include <asm/hw_irq.h>
  78
  79 #if defined(IA64_MCA_DEBUG_INFO)
  80 # define IA64_MCA_DEBUG(fmt...) printk(fmt)
  81 #else
  82 # define IA64_MCA_DEBUG(fmt...)
  83 #endif
  84
  85 typedef struct ia64_fptr {
  86         unsigned long fp;
  87         unsigned long gp;
  88 } ia64_fptr_t;
  89
  90 /* Used by mca_asm.S */
  91 ia64_mca_sal_to_os_state_t      ia64_sal_to_os_handoff_state;
  92 ia64_mca_os_to_sal_state_t      ia64_os_to_sal_handoff_state;
  93 u64                             ia64_mca_proc_state_dump[512];
  94 u64                             ia64_mca_stack[1024] __attribute__((aligned(16)));
  95 u64                             ia64_mca_stackframe[32];
  96 u64                             ia64_mca_bspstore[1024];
  97 u64                             ia64_init_stack[KERNEL_STACK_SIZE/8] __attribute__((aligned(16)));
  98 u64                             ia64_mca_serialize;
  99
 100 /* In mca_asm.S */
 101 extern void                     ia64_monarch_init_handler (void);
 102 extern void                     ia64_slave_init_handler (void);
 103
 104 static ia64_mc_info_t           ia64_mc_info;
 105
 106 struct ia64_mca_tlb_info ia64_mca_tlb_list[NR_CPUS];
 107
 108 #define MAX_CPE_POLL_INTERVAL (15*60*HZ) /* 15 minutes */
 109 #define MIN_CPE_POLL_INTERVAL (2*60*HZ)  /* 2 minutes */
 110 #define CMC_POLL_INTERVAL     (1*60*HZ)  /* 1 minute */
 111 #define CPE_HISTORY_LENGTH    5
 112 #define CMC_HISTORY_LENGTH    5
 113
 114 static struct timer_list cpe_poll_timer;
 115 static struct timer_list cmc_poll_timer;
 116 /*
 117  * This variable tells whether we are currently in polling mode.
 118  * Start with this in the wrong state so we won't play w/ timers
 119  * before the system is ready.
 120  */
 121 static int cmc_polling_enabled = 1;
 122
 123 /*
 124  * Clearing this variable prevents CPE polling from getting activated
 125  * in mca_late_init.  Use it if your system doesn't provide a CPEI,
 126  * but encounters problems retrieving CPE logs.  This should only be
 127  * necessary for debugging.
 128  */
 129 static int cpe_poll_enabled = 1;
 130
 131 static int cpe_vector = -1;
 132
 133 extern void salinfo_log_wakeup(int type, u8 *buffer, u64 size, int irqsafe);
 134
 135 /*
 136  * IA64_MCA log support
 137  */
 138 #define IA64_MAX_LOGS           2       /* Double-buffering for nested MCAs */
 139 #define IA64_MAX_LOG_TYPES      4   /* MCA, INIT, CMC, CPE */
 140
 141 typedef struct ia64_state_log_s
 142 {
 143         spinlock_t      isl_lock;
 144         int             isl_index;
 145         unsigned long   isl_count;
 146         ia64_err_rec_t  *isl_log[IA64_MAX_LOGS]; /* need space to store header + error log */
 147 } ia64_state_log_t;
 148
 149 static ia64_state_log_t ia64_state_log[IA64_MAX_LOG_TYPES];
 150
 151 #define IA64_LOG_ALLOCATE(it, size) \
 152         {ia64_state_log[it].isl_log[IA64_LOG_CURR_INDEX(it)] = \
 153                 (ia64_err_rec_t *)alloc_bootmem(size); \
 154         ia64_state_log[it].isl_log[IA64_LOG_NEXT_INDEX(it)] = \
 155                 (ia64_err_rec_t *)alloc_bootmem(size);}
 156 #define IA64_LOG_LOCK_INIT(it) spin_lock_init(&ia64_state_log[it].isl_lock)
 157 #define IA64_LOG_LOCK(it)      spin_lock_irqsave(&ia64_state_log[it].isl_lock, s)
 158 #define IA64_LOG_UNLOCK(it)    spin_unlock_irqrestore(&ia64_state_log[it].isl_lock,s)
 159 #define IA64_LOG_NEXT_INDEX(it)    ia64_state_log[it].isl_index
 160 #define IA64_LOG_CURR_INDEX(it)    1 - ia64_state_log[it].isl_index
 161 #define IA64_LOG_INDEX_INC(it) \
 162     {ia64_state_log[it].isl_index = 1 - ia64_state_log[it].isl_index; \
 163     ia64_state_log[it].isl_count++;}
 164 #define IA64_LOG_INDEX_DEC(it) \
 165     ia64_state_log[it].isl_index = 1 - ia64_state_log[it].isl_index
 166 #define IA64_LOG_NEXT_BUFFER(it)   (void *)((ia64_state_log[it].isl_log[IA64_LOG_NEXT_INDEX(it)]))
 167 #define IA64_LOG_CURR_BUFFER(it)   (void *)((ia64_state_log[it].isl_log[IA64_LOG_CURR_INDEX(it)]))
 168 #define IA64_LOG_COUNT(it)         ia64_state_log[it].isl_count
 169
 170 /*
 171  * ia64_log_init
 172  *      Reset the OS ia64 log buffer
 173  * Inputs   :   info_type   (SAL_INFO_TYPE_{MCA,INIT,CMC,CPE})
 174  * Outputs      :       None
 175  */
 176 static void
 177 ia64_log_init(int sal_info_type)
 178 {
 179         u64     max_size = 0;
 180
 181         IA64_LOG_NEXT_INDEX(sal_info_type) = 0;
 182         IA64_LOG_LOCK_INIT(sal_info_type);
 183
 184         // SAL will tell us the maximum size of any error record of this type
 185         max_size = ia64_sal_get_state_info_size(sal_info_type);
 186         if (!max_size)
 187                 /* alloc_bootmem() doesn't like zero-sized allocations! */
 188                 return;
 189
 190         // set up OS data structures to hold error info
 191         IA64_LOG_ALLOCATE(sal_info_type, max_size);
 192         memset(IA64_LOG_CURR_BUFFER(sal_info_type), 0, max_size);
 193         memset(IA64_LOG_NEXT_BUFFER(sal_info_type), 0, max_size);
 194 }
 195
 196 /*
 197  * ia64_log_get
 198  *
 199  *      Get the current MCA log from SAL and copy it into the OS log buffer.
 200  *
 201  *  Inputs  :   info_type   (SAL_INFO_TYPE_{MCA,INIT,CMC,CPE})
 202  *              irq_safe    whether you can use printk at this point
 203  *  Outputs :   size        (total record length)
 204  *              *buffer     (ptr to error record)
 205  *
 206  */
 207 static u64
 208 ia64_log_get(int sal_info_type, u8 **buffer, int irq_safe)
 209 {
 210         sal_log_record_header_t     *log_buffer;
 211         u64                         total_len = 0;
 212         int                         s;
 213
 214         IA64_LOG_LOCK(sal_info_type);
 215
 216         /* Get the process state information */
 217         log_buffer = IA64_LOG_NEXT_BUFFER(sal_info_type);
 218
 219         total_len = ia64_sal_get_state_info(sal_info_type, (u64 *)log_buffer);
 220
 221         if (total_len) {
 222                 IA64_LOG_INDEX_INC(sal_info_type);
 223                 IA64_LOG_UNLOCK(sal_info_type);
 224                 if (irq_safe) {
 225                         IA64_MCA_DEBUG("%s: SAL error record type %d retrieved. "
 226                                        "Record length = %ld\n", __FUNCTION__, sal_info_type, total_len);
 227                 }
 228                 *buffer = (u8 *) log_buffer;
 229                 return total_len;
 230         } else {
 231                 IA64_LOG_UNLOCK(sal_info_type);
 232                 return 0;
 233         }
 234 }
 235
 236 /*
 237  *  ia64_mca_log_sal_error_record
 238  *
 239  *  This function retrieves a specified error record type from SAL
 240  *  and wakes up any processes waiting for error records.
 241  *
 242  *  Inputs  :   sal_info_type   (Type of error record MCA/CMC/CPE/INIT)
 243  */
 244 static void
 245 ia64_mca_log_sal_error_record(int sal_info_type)
 246 {
 247         u8 *buffer;
 248         u64 size;
 249         int irq_safe = sal_info_type != SAL_INFO_TYPE_MCA && sal_info_type != SAL_INFO_TYPE_INIT;
 250 #ifdef IA64_MCA_DEBUG_INFO
 251         static const char * const rec_name[] = { "MCA", "INIT", "CMC", "CPE" };
 252 #endif
 253
 254         size = ia64_log_get(sal_info_type, &buffer, irq_safe);
 255         if (!size)
 256                 return;
 257
 258         salinfo_log_wakeup(sal_info_type, buffer, size, irq_safe);
 259
 260         if (irq_safe)
 261                 IA64_MCA_DEBUG("CPU %d: SAL log contains %s error record\n",
 262                         smp_processor_id(),
 263                         sal_info_type < ARRAY_SIZE(rec_name) ? rec_name[sal_info_type] : "UNKNOWN");
 264
 265         /* Clear logs from corrected errors in case there's no user-level logger */
 266         if (sal_info_type == SAL_INFO_TYPE_CPE || sal_info_type == SAL_INFO_TYPE_CMC)
 267                 ia64_sal_clear_state_info(sal_info_type);
 268 }
 269
 270 /*
 271  * platform dependent error handling
 272  */
 273 #ifndef PLATFORM_MCA_HANDLERS
 274
 275 #ifdef CONFIG_ACPI
 276
 277 static irqreturn_t
 278 ia64_mca_cpe_int_handler (int cpe_irq, void *arg, struct pt_regs *ptregs)
 279 {
 280         static unsigned long    cpe_history[CPE_HISTORY_LENGTH];
 281         static int              index;
 282         static spinlock_t       cpe_history_lock = SPIN_LOCK_UNLOCKED;
 283
 284         IA64_MCA_DEBUG("%s: received interrupt vector = %#x on CPU %d\n",
 285                        __FUNCTION__, cpe_irq, smp_processor_id());
 286
 287         /* SAL spec states this should run w/ interrupts enabled */
 288         local_irq_enable();
 289
 290         /* Get the CPE error record and log it */
 291         ia64_mca_log_sal_error_record(SAL_INFO_TYPE_CPE);
 292
 293         spin_lock(&cpe_history_lock);
 294         if (!cpe_poll_enabled && cpe_vector >= 0) {
 295
 296                 int i, count = 1; /* we know 1 happened now */
 297                 unsigned long now = jiffies;
 298
 299                 for (i = 0; i < CPE_HISTORY_LENGTH; i++) {
 300                         if (now - cpe_history[i] <= HZ)
 301                                 count++;
 302                 }
 303
 304                 IA64_MCA_DEBUG(KERN_INFO "CPE threshold %d/%d\n", count, CPE_HISTORY_LENGTH);
 305                 if (count >= CPE_HISTORY_LENGTH) {
 306
 307                         cpe_poll_enabled = 1;
 308                         spin_unlock(&cpe_history_lock);
 309                         disable_irq_nosync(local_vector_to_irq(IA64_CPE_VECTOR));
 310
 311                         /*
 312                          * Corrected errors will still be corrected, but
 313                          * make sure there's a log somewhere that indicates
 314                          * something is generating more than we can handle.
 315                          */
 316                         printk(KERN_WARNING "WARNING: Switching to polling CPE handler; error records may be lost\n");
 317
 318                         mod_timer(&cpe_poll_timer, jiffies + MIN_CPE_POLL_INTERVAL);
 319
 320                         /* lock already released, get out now */
 321                         return IRQ_HANDLED;
 322                 } else {
 323                         cpe_history[index++] = now;
 324                         if (index == CPE_HISTORY_LENGTH)
 325                                 index = 0;
 326                 }
 327         }
 328         spin_unlock(&cpe_history_lock);
 329         return IRQ_HANDLED;
 330 }
 331
 332 #endif /* CONFIG_ACPI */
 333
 334 static void
 335 show_min_state (pal_min_state_area_t *minstate)
 336 {
 337         u64 iip = minstate->pmsa_iip + ((struct ia64_psr *)(&minstate->pmsa_ipsr))->ri;
 338         u64 xip = minstate->pmsa_xip + ((struct ia64_psr *)(&minstate->pmsa_xpsr))->ri;
 339
 340         printk("NaT bits\t%016lx\n", minstate->pmsa_nat_bits);
 341         printk("pr\t\t%016lx\n", minstate->pmsa_pr);
 342         printk("b0\t\t%016lx ", minstate->pmsa_br0); print_symbol("%s\n", minstate->pmsa_br0);
 343         printk("ar.rsc\t\t%016lx\n", minstate->pmsa_rsc);
 344         printk("cr.iip\t\t%016lx ", iip); print_symbol("%s\n", iip);
 345         printk("cr.ipsr\t\t%016lx\n", minstate->pmsa_ipsr);
 346         printk("cr.ifs\t\t%016lx\n", minstate->pmsa_ifs);
 347         printk("xip\t\t%016lx ", xip); print_symbol("%s\n", xip);
 348         printk("xpsr\t\t%016lx\n", minstate->pmsa_xpsr);
 349         printk("xfs\t\t%016lx\n", minstate->pmsa_xfs);
 350         printk("b1\t\t%016lx ", minstate->pmsa_br1);
 351         print_symbol("%s\n", minstate->pmsa_br1);
 352
 353         printk("\nstatic registers r0-r15:\n");
 354         printk(" r0- 3 %016lx %016lx %016lx %016lx\n",
 355                0UL, minstate->pmsa_gr[0], minstate->pmsa_gr[1], minstate->pmsa_gr[2]);
 356         printk(" r4- 7 %016lx %016lx %016lx %016lx\n",
 357                minstate->pmsa_gr[3], minstate->pmsa_gr[4],
 358                minstate->pmsa_gr[5], minstate->pmsa_gr[6]);
 359         printk(" r8-11 %016lx %016lx %016lx %016lx\n",
 360                minstate->pmsa_gr[7], minstate->pmsa_gr[8],
 361                minstate->pmsa_gr[9], minstate->pmsa_gr[10]);
 362         printk("r12-15 %016lx %016lx %016lx %016lx\n",
 363                minstate->pmsa_gr[11], minstate->pmsa_gr[12],
 364                minstate->pmsa_gr[13], minstate->pmsa_gr[14]);
 365
 366         printk("\nbank 0:\n");
 367         printk("r16-19 %016lx %016lx %016lx %016lx\n",
 368                minstate->pmsa_bank0_gr[0], minstate->pmsa_bank0_gr[1],
 369                minstate->pmsa_bank0_gr[2], minstate->pmsa_bank0_gr[3]);
 370         printk("r20-23 %016lx %016lx %016lx %016lx\n",
 371                minstate->pmsa_bank0_gr[4], minstate->pmsa_bank0_gr[5],
 372                minstate->pmsa_bank0_gr[6], minstate->pmsa_bank0_gr[7]);
 373         printk("r24-27 %016lx %016lx %016lx %016lx\n",
 374                minstate->pmsa_bank0_gr[8], minstate->pmsa_bank0_gr[9],
 375                minstate->pmsa_bank0_gr[10], minstate->pmsa_bank0_gr[11]);
 376         printk("r28-31 %016lx %016lx %016lx %016lx\n",
 377                minstate->pmsa_bank0_gr[12], minstate->pmsa_bank0_gr[13],
 378                minstate->pmsa_bank0_gr[14], minstate->pmsa_bank0_gr[15]);
 379
 380         printk("\nbank 1:\n");
 381         printk("r16-19 %016lx %016lx %016lx %016lx\n",
 382                minstate->pmsa_bank1_gr[0], minstate->pmsa_bank1_gr[1],
 383                minstate->pmsa_bank1_gr[2], minstate->pmsa_bank1_gr[3]);
 384         printk("r20-23 %016lx %016lx %016lx %016lx\n",
 385                minstate->pmsa_bank1_gr[4], minstate->pmsa_bank1_gr[5],
 386                minstate->pmsa_bank1_gr[6], minstate->pmsa_bank1_gr[7]);
 387         printk("r24-27 %016lx %016lx %016lx %016lx\n",
 388                minstate->pmsa_bank1_gr[8], minstate->pmsa_bank1_gr[9],
 389                minstate->pmsa_bank1_gr[10], minstate->pmsa_bank1_gr[11]);
 390         printk("r28-31 %016lx %016lx %016lx %016lx\n",
 391                minstate->pmsa_bank1_gr[12], minstate->pmsa_bank1_gr[13],
 392                minstate->pmsa_bank1_gr[14], minstate->pmsa_bank1_gr[15]);
 393 }
 394
 395 static void
 396 fetch_min_state (pal_min_state_area_t *ms, struct pt_regs *pt, struct switch_stack *sw)
 397 {
 398         u64 *dst_banked, *src_banked, bit, shift, nat_bits;
 399         int i;
 400
 401         /*
 402          * First, update the pt-regs and switch-stack structures with the contents stored
 403          * in the min-state area:
 404          */
 405         if (((struct ia64_psr *) &ms->pmsa_ipsr)->ic == 0) {
 406                 pt->cr_ipsr = ms->pmsa_xpsr;
 407                 pt->cr_iip = ms->pmsa_xip;
 408                 pt->cr_ifs = ms->pmsa_xfs;
 409         } else {
 410                 pt->cr_ipsr = ms->pmsa_ipsr;
 411                 pt->cr_iip = ms->pmsa_iip;
 412                 pt->cr_ifs = ms->pmsa_ifs;
 413         }
 414         pt->ar_rsc = ms->pmsa_rsc;
 415         pt->pr = ms->pmsa_pr;
 416         pt->r1 = ms->pmsa_gr[0];
 417         pt->r2 = ms->pmsa_gr[1];
 418         pt->r3 = ms->pmsa_gr[2];
 419         sw->r4 = ms->pmsa_gr[3];
 420         sw->r5 = ms->pmsa_gr[4];
 421         sw->r6 = ms->pmsa_gr[5];
 422         sw->r7 = ms->pmsa_gr[6];
 423         pt->r8 = ms->pmsa_gr[7];
 424         pt->r9 = ms->pmsa_gr[8];
 425         pt->r10 = ms->pmsa_gr[9];
 426         pt->r11 = ms->pmsa_gr[10];
 427         pt->r12 = ms->pmsa_gr[11];
 428         pt->r13 = ms->pmsa_gr[12];
 429         pt->r14 = ms->pmsa_gr[13];
 430         pt->r15 = ms->pmsa_gr[14];
 431         dst_banked = &pt->r16;          /* r16-r31 are contiguous in struct pt_regs */
 432         src_banked = ms->pmsa_bank1_gr;
 433         for (i = 0; i < 16; ++i)
 434                 dst_banked[i] = src_banked[i];
 435         pt->b0 = ms->pmsa_br0;
 436         sw->b1 = ms->pmsa_br1;
 437
 438         /* construct the NaT bits for the pt-regs structure: */
 439 #       define PUT_NAT_BIT(dst, addr)                                   \
 440         do {                                                            \
 441                 bit = nat_bits & 1; nat_bits >>= 1;                     \
 442                 shift = ((unsigned long) addr >> 3) & 0x3f;             \
 443                 dst = ((dst) & ~(1UL << shift)) | (bit << shift);       \
 444         } while (0)
 445
 446         /* Rotate the saved NaT bits such that bit 0 corresponds to pmsa_gr[0]: */
 447         shift = ((unsigned long) &ms->pmsa_gr[0] >> 3) & 0x3f;
 448         nat_bits = (ms->pmsa_nat_bits >> shift) | (ms->pmsa_nat_bits << (64 - shift));
 449
 450         PUT_NAT_BIT(sw->caller_unat, &pt->r1);
 451         PUT_NAT_BIT(sw->caller_unat, &pt->r2);
 452         PUT_NAT_BIT(sw->caller_unat, &pt->r3);
 453         PUT_NAT_BIT(sw->ar_unat, &sw->r4);
 454         PUT_NAT_BIT(sw->ar_unat, &sw->r5);
 455         PUT_NAT_BIT(sw->ar_unat, &sw->r6);
 456         PUT_NAT_BIT(sw->ar_unat, &sw->r7);
 457         PUT_NAT_BIT(sw->caller_unat, &pt->r8);  PUT_NAT_BIT(sw->caller_unat, &pt->r9);
 458         PUT_NAT_BIT(sw->caller_unat, &pt->r10); PUT_NAT_BIT(sw->caller_unat, &pt->r11);
 459         PUT_NAT_BIT(sw->caller_unat, &pt->r12); PUT_NAT_BIT(sw->caller_unat, &pt->r13);
 460         PUT_NAT_BIT(sw->caller_unat, &pt->r14); PUT_NAT_BIT(sw->caller_unat, &pt->r15);
 461         nat_bits >>= 16;        /* skip over bank0 NaT bits */
 462         PUT_NAT_BIT(sw->caller_unat, &pt->r16); PUT_NAT_BIT(sw->caller_unat, &pt->r17);
 463         PUT_NAT_BIT(sw->caller_unat, &pt->r18); PUT_NAT_BIT(sw->caller_unat, &pt->r19);
 464         PUT_NAT_BIT(sw->caller_unat, &pt->r20); PUT_NAT_BIT(sw->caller_unat, &pt->r21);
 465         PUT_NAT_BIT(sw->caller_unat, &pt->r22); PUT_NAT_BIT(sw->caller_unat, &pt->r23);
 466         PUT_NAT_BIT(sw->caller_unat, &pt->r24); PUT_NAT_BIT(sw->caller_unat, &pt->r25);
 467         PUT_NAT_BIT(sw->caller_unat, &pt->r26); PUT_NAT_BIT(sw->caller_unat, &pt->r27);
 468         PUT_NAT_BIT(sw->caller_unat, &pt->r28); PUT_NAT_BIT(sw->caller_unat, &pt->r29);
 469         PUT_NAT_BIT(sw->caller_unat, &pt->r30); PUT_NAT_BIT(sw->caller_unat, &pt->r31);
 470 }
 471
 472 static void
 473 init_handler_platform (pal_min_state_area_t *ms,
 474                        struct pt_regs *pt, struct switch_stack *sw)
 475 {
 476         struct unw_frame_info info;
 477
 478         /* if a kernel debugger is available call it here else just dump the registers */
 479
 480         /*
 481          * Wait for a bit.  On some machines (e.g., HP's zx2000 and zx6000, INIT can be
 482          * generated via the BMC's command-line interface, but since the console is on the
 483          * same serial line, the user will need some time to switch out of the BMC before
 484          * the dump begins.
 485          */
 486         printk("Delaying for 5 seconds...\n");
 487         udelay(5*1000000);
 488         show_min_state(ms);
 489
 490         printk("Backtrace of current task (pid %d, %s)\n", current->pid, current->comm);
 491         fetch_min_state(ms, pt, sw);
 492         unw_init_from_interruption(&info, current, pt, sw);
 493         ia64_do_show_stack(&info, NULL);
 494
 495 #ifdef CONFIG_SMP
 496         /* read_trylock() would be handy... */
 497         if (!tasklist_lock.write_lock)
 498                 read_lock(&tasklist_lock);
 499 #endif
 500         {
 501                 struct task_struct *g, *t;
 502                 do_each_thread (g, t) {
 503                         if (t == current)
 504                                 continue;
 505
 506                         printk("\nBacktrace of pid %d (%s)\n", t->pid, t->comm);
 507                         show_stack(t, NULL);
 508                 } while_each_thread (g, t);
 509         }
 510 #ifdef CONFIG_SMP
 511         if (!tasklist_lock.write_lock)
 512                 read_unlock(&tasklist_lock);
 513 #endif
 514
 515         printk("\nINIT dump complete.  Please reboot now.\n");
 516         while (1);                      /* hang city if no debugger */
 517 }
 518
 519 #ifdef CONFIG_ACPI
 520 /*
 521  * ia64_mca_register_cpev
 522  *
 523  *  Register the corrected platform error vector with SAL.
 524  *
 525  *  Inputs
 526  *      cpev        Corrected Platform Error Vector number
 527  *
 528  *  Outputs
 529  *      None
 530  */
 531 static void
 532 ia64_mca_register_cpev (int cpev)
 533 {
 534         /* Register the CPE interrupt vector with SAL */
 535         struct ia64_sal_retval isrv;
 536
 537         isrv = ia64_sal_mc_set_params(SAL_MC_PARAM_CPE_INT, SAL_MC_PARAM_MECHANISM_INT, cpev, 0, 0);
 538         if (isrv.status) {
 539                 printk(KERN_ERR "Failed to register Corrected Platform "
 540                        "Error interrupt vector with SAL (status %ld)\n", isrv.status);
 541                 return;
 542         }
 543
 544         IA64_MCA_DEBUG("%s: corrected platform error "
 545                        "vector %#x setup and enabled\n", __FUNCTION__, cpev);
 546 }
 547 #endif /* CONFIG_ACPI */
 548
 549 #endif /* PLATFORM_MCA_HANDLERS */
 550
 551 /*
 552  * ia64_mca_cmc_vector_setup
 553  *
 554  *  Setup the corrected machine check vector register in the processor and
 555  *  unmask interrupt.  This function is invoked on a per-processor basis.
 556  *
 557  * Inputs
 558  *      None
 559  *
 560  * Outputs
 561  *      None
 562  */
 563 void
 564 ia64_mca_cmc_vector_setup (void)
 565 {
 566         cmcv_reg_t      cmcv;
 567
 568         cmcv.cmcv_regval        = 0;
 569         cmcv.cmcv_mask          = 0;        /* Unmask/enable interrupt */
 570         cmcv.cmcv_vector        = IA64_CMC_VECTOR;
 571         ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval);
 572
 573         IA64_MCA_DEBUG("%s: CPU %d corrected "
 574                        "machine check vector %#x setup and enabled.\n",
 575                        __FUNCTION__, smp_processor_id(), IA64_CMC_VECTOR);
 576
 577         IA64_MCA_DEBUG("%s: CPU %d CMCV = %#016lx\n",
 578                        __FUNCTION__, smp_processor_id(), ia64_getreg(_IA64_REG_CR_CMCV));
 579 }
 580
 581 /*
 582  * ia64_mca_cmc_vector_disable
 583  *
 584  *  Mask the corrected machine check vector register in the processor.
 585  *  This function is invoked on a per-processor basis.
 586  *
 587  * Inputs
 588  *      dummy(unused)
 589  *
 590  * Outputs
 591  *      None
 592  */
 593 static void
 594 ia64_mca_cmc_vector_disable (void *dummy)
 595 {
 596         cmcv_reg_t      cmcv;
 597
 598         cmcv = (cmcv_reg_t)ia64_getreg(_IA64_REG_CR_CMCV);
 599
 600         cmcv.cmcv_mask = 1; /* Mask/disable interrupt */
 601         ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval);
 602
 603         IA64_MCA_DEBUG("%s: CPU %d corrected "
 604                        "machine check vector %#x disabled.\n",
 605                        __FUNCTION__, smp_processor_id(), cmcv.cmcv_vector);
 606 }
 607
 608 /*
 609  * ia64_mca_cmc_vector_enable
 610  *
 611  *  Unmask the corrected machine check vector register in the processor.
 612  *  This function is invoked on a per-processor basis.
 613  *
 614  * Inputs
 615  *      dummy(unused)
 616  *
 617  * Outputs
 618  *      None
 619  */
 620 static void
 621 ia64_mca_cmc_vector_enable (void *dummy)
 622 {
 623         cmcv_reg_t      cmcv;
 624
 625         cmcv = (cmcv_reg_t)ia64_getreg(_IA64_REG_CR_CMCV);
 626
 627         cmcv.cmcv_mask = 0; /* Unmask/enable interrupt */
 628         ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval);
 629
 630         IA64_MCA_DEBUG("%s: CPU %d corrected "
 631                        "machine check vector %#x enabled.\n",
 632                        __FUNCTION__, smp_processor_id(), cmcv.cmcv_vector);
 633 }
 634
 635 /*
 636  * ia64_mca_cmc_vector_disable_keventd
 637  *
 638  * Called via keventd (smp_call_function() is not safe in interrupt context) to
 639  * disable the cmc interrupt vector.
 640  */
 641 static void
 642 ia64_mca_cmc_vector_disable_keventd(void *unused)
 643 {
 644         on_each_cpu(ia64_mca_cmc_vector_disable, NULL, 1, 0);
 645 }
 646
 647 /*
 648  * ia64_mca_cmc_vector_enable_keventd
 649  *
 650  * Called via keventd (smp_call_function() is not safe in interrupt context) to
 651  * enable the cmc interrupt vector.
 652  */
 653 static void
 654 ia64_mca_cmc_vector_enable_keventd(void *unused)
 655 {
 656         on_each_cpu(ia64_mca_cmc_vector_enable, NULL, 1, 0);
 657 }
 658
 659 /*
 660  * ia64_mca_wakeup_ipi_wait
 661  *
 662  *      Wait for the inter-cpu interrupt to be sent by the
 663  *      monarch processor once it is done with handling the
 664  *      MCA.
 665  *
 666  *  Inputs  :   None
 667  *  Outputs :   None
 668  */
 669 static void
 670 ia64_mca_wakeup_ipi_wait(void)
 671 {
 672         int     irr_num = (IA64_MCA_WAKEUP_VECTOR >> 6);
 673         int     irr_bit = (IA64_MCA_WAKEUP_VECTOR & 0x3f);
 674         u64     irr = 0;
 675
 676         do {
 677                 switch(irr_num) {
 678                       case 0:
 679                         irr = ia64_getreg(_IA64_REG_CR_IRR0);
 680                         break;
 681                       case 1:
 682                         irr = ia64_getreg(_IA64_REG_CR_IRR1);
 683                         break;
 684                       case 2:
 685                         irr = ia64_getreg(_IA64_REG_CR_IRR2);
 686                         break;
 687                       case 3:
 688                         irr = ia64_getreg(_IA64_REG_CR_IRR3);
 689                         break;
 690                 }
 691         } while (!(irr & (1UL << irr_bit))) ;
 692 }
 693
 694 /*
 695  * ia64_mca_wakeup
 696  *
 697  *      Send an inter-cpu interrupt to wake-up a particular cpu
 698  *      and mark that cpu to be out of rendez.
 699  *
 700  *  Inputs  :   cpuid
 701  *  Outputs :   None
 702  */
 703 static void
 704 ia64_mca_wakeup(int cpu)
 705 {
 706         platform_send_ipi(cpu, IA64_MCA_WAKEUP_VECTOR, IA64_IPI_DM_INT, 0);
 707         ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
 708
 709 }
 710
 711 /*
 712  * ia64_mca_wakeup_all
 713  *
 714  *      Wakeup all the cpus which have rendez'ed previously.
 715  *
 716  *  Inputs  :   None
 717  *  Outputs :   None
 718  */
 719 static void
 720 ia64_mca_wakeup_all(void)
 721 {
 722         int cpu;
 723
 724         /* Clear the Rendez checkin flag for all cpus */
 725         for(cpu = 0; cpu < NR_CPUS; cpu++) {
 726                 if (!cpu_online(cpu))
 727                         continue;
 728                 if (ia64_mc_info.imi_rendez_checkin[cpu] == IA64_MCA_RENDEZ_CHECKIN_DONE)
 729                         ia64_mca_wakeup(cpu);
 730         }
 731
 732 }
 733
 734 /*
 735  * ia64_mca_rendez_interrupt_handler
 736  *
 737  *      This is handler used to put slave processors into spinloop
 738  *      while the monarch processor does the mca handling and later
 739  *      wake each slave up once the monarch is done.
 740  *
 741  *  Inputs  :   None
 742  *  Outputs :   None
 743  */
 744 static irqreturn_t
 745 ia64_mca_rendez_int_handler(int rendez_irq, void *arg, struct pt_regs *ptregs)
 746 {
 747         unsigned long flags;
 748         int cpu = smp_processor_id();
 749
 750         /* Mask all interrupts */
 751         local_irq_save(flags);
 752
 753         ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_DONE;
 754         /* Register with the SAL monarch that the slave has
 755          * reached SAL
 756          */
 757         ia64_sal_mc_rendez();
 758
 759         /* Wait for the wakeup IPI from the monarch
 760          * This waiting is done by polling on the wakeup-interrupt
 761          * vector bit in the processor's IRRs
 762          */
 763         ia64_mca_wakeup_ipi_wait();
 764
 765         /* Enable all interrupts */
 766         local_irq_restore(flags);
 767         return IRQ_HANDLED;
 768 }
 769
 770 /*
 771  * ia64_mca_wakeup_int_handler
 772  *
 773  *      The interrupt handler for processing the inter-cpu interrupt to the
 774  *      slave cpu which was spinning in the rendez loop.
 775  *      Since this spinning is done by turning off the interrupts and
 776  *      polling on the wakeup-interrupt bit in the IRR, there is
 777  *      nothing useful to be done in the handler.
 778  *
 779  *  Inputs  :   wakeup_irq  (Wakeup-interrupt bit)
 780  *      arg             (Interrupt handler specific argument)
 781  *      ptregs          (Exception frame at the time of the interrupt)
 782  *  Outputs :   None
 783  *
 784  */
 785 static irqreturn_t
 786 ia64_mca_wakeup_int_handler(int wakeup_irq, void *arg, struct pt_regs *ptregs)
 787 {
 788         return IRQ_HANDLED;
 789 }
 790
 791 /*
 792  * ia64_return_to_sal_check
 793  *
 794  *      This is function called before going back from the OS_MCA handler
 795  *      to the OS_MCA dispatch code which finally takes the control back
 796  *      to the SAL.
 797  *      The main purpose of this routine is to setup the OS_MCA to SAL
 798  *      return state which can be used by the OS_MCA dispatch code
 799  *      just before going back to SAL.
 800  *
 801  *  Inputs  :   None
 802  *  Outputs :   None
 803  */
 804
 805 static void
 806 ia64_return_to_sal_check(int recover)
 807 {
 808
 809         /* Copy over some relevant stuff from the sal_to_os_mca_handoff
 810          * so that it can be used at the time of os_mca_to_sal_handoff
 811          */
 812         ia64_os_to_sal_handoff_state.imots_sal_gp =
 813                 ia64_sal_to_os_handoff_state.imsto_sal_gp;
 814
 815         ia64_os_to_sal_handoff_state.imots_sal_check_ra =
 816                 ia64_sal_to_os_handoff_state.imsto_sal_check_ra;
 817
 818         if (recover)
 819                 ia64_os_to_sal_handoff_state.imots_os_status = IA64_MCA_CORRECTED;
 820         else
 821                 ia64_os_to_sal_handoff_state.imots_os_status = IA64_MCA_COLD_BOOT;
 822
 823         /* Default = tell SAL to return to same context */
 824         ia64_os_to_sal_handoff_state.imots_context = IA64_MCA_SAME_CONTEXT;
 825
 826         ia64_os_to_sal_handoff_state.imots_new_min_state =
 827                 (u64 *)ia64_sal_to_os_handoff_state.pal_min_state;
 828
 829 }
 830
 831 /*
 832  * ia64_mca_ucmc_handler
 833  *
 834  *      This is uncorrectable machine check handler called from OS_MCA
 835  *      dispatch code which is in turn called from SAL_CHECK().
 836  *      This is the place where the core of OS MCA handling is done.
 837  *      Right now the logs are extracted and displayed in a well-defined
 838  *      format. This handler code is supposed to be run only on the
 839  *      monarch processor. Once the monarch is done with MCA handling
 840  *      further MCA logging is enabled by clearing logs.
 841  *      Monarch also has the duty of sending wakeup-IPIs to pull the
 842  *      slave processors out of rendezvous spinloop.
 843  *
 844  *  Inputs  :   None
 845  *  Outputs :   None
 846  */
 847 void
 848 ia64_mca_ucmc_handler(void)
 849 {
 850         pal_processor_state_info_t *psp = (pal_processor_state_info_t *)
 851                 &ia64_sal_to_os_handoff_state.proc_state_param;
 852         int recover = psp->tc && !(psp->cc || psp->bc || psp->rc || psp->uc);
 853
 854         /* Get the MCA error record and log it */
 855         ia64_mca_log_sal_error_record(SAL_INFO_TYPE_MCA);
 856
 857         /*
 858          *  Wakeup all the processors which are spinning in the rendezvous
 859          *  loop.
 860          */
 861         ia64_mca_wakeup_all();
 862
 863         /* Return to SAL */
 864         ia64_return_to_sal_check(recover);
 865 }
 866
 867 static DECLARE_WORK(cmc_disable_work, ia64_mca_cmc_vector_disable_keventd, NULL);
 868 static DECLARE_WORK(cmc_enable_work, ia64_mca_cmc_vector_enable_keventd, NULL);
 869
 870 /*
 871  * ia64_mca_cmc_int_handler
 872  *
 873  *  This is corrected machine check interrupt handler.
 874  *      Right now the logs are extracted and displayed in a well-defined
 875  *      format.
 876  *
 877  * Inputs
 878  *      interrupt number
 879  *      client data arg ptr
 880  *      saved registers ptr
 881  *
 882  * Outputs
 883  *      None
 884  */
 885 static irqreturn_t
 886 ia64_mca_cmc_int_handler(int cmc_irq, void *arg, struct pt_regs *ptregs)
 887 {
 888         static unsigned long    cmc_history[CMC_HISTORY_LENGTH];
 889         static int              index;
 890         static spinlock_t       cmc_history_lock = SPIN_LOCK_UNLOCKED;
 891
 892         IA64_MCA_DEBUG("%s: received interrupt vector = %#x on CPU %d\n",
 893                        __FUNCTION__, cmc_irq, smp_processor_id());
 894
 895         /* SAL spec states this should run w/ interrupts enabled */
 896         local_irq_enable();
 897
 898         /* Get the CMC error record and log it */
 899         ia64_mca_log_sal_error_record(SAL_INFO_TYPE_CMC);
 900
 901         spin_lock(&cmc_history_lock);
 902         if (!cmc_polling_enabled) {
 903                 int i, count = 1; /* we know 1 happened now */
 904                 unsigned long now = jiffies;
 905
 906                 for (i = 0; i < CMC_HISTORY_LENGTH; i++) {
 907                         if (now - cmc_history[i] <= HZ)
 908                                 count++;
 909                 }
 910
 911                 IA64_MCA_DEBUG(KERN_INFO "CMC threshold %d/%d\n", count, CMC_HISTORY_LENGTH);
 912                 if (count >= CMC_HISTORY_LENGTH) {
 913
 914                         cmc_polling_enabled = 1;
 915                         spin_unlock(&cmc_history_lock);
 916                         schedule_work(&cmc_disable_work);
 917
 918                         /*
 919                          * Corrected errors will still be corrected, but
 920                          * make sure there's a log somewhere that indicates
 921                          * something is generating more than we can handle.
 922                          */
 923                         printk(KERN_WARNING "WARNING: Switching to polling CMC handler; error records may be lost\n");
 924
 925                         mod_timer(&cmc_poll_timer, jiffies + CMC_POLL_INTERVAL);
 926
 927                         /* lock already released, get out now */
 928                         return IRQ_HANDLED;
 929                 } else {
 930                         cmc_history[index++] = now;
 931                         if (index == CMC_HISTORY_LENGTH)
 932                                 index = 0;
 933                 }
 934         }
 935         spin_unlock(&cmc_history_lock);
 936         return IRQ_HANDLED;
 937 }
 938
 939 /*
 940  *  ia64_mca_cmc_int_caller
 941  *
 942  *      Triggered by sw interrupt from CMC polling routine.  Calls
 943  *      real interrupt handler and either triggers a sw interrupt
 944  *      on the next cpu or does cleanup at the end.
 945  *
 946  * Inputs
 947  *      interrupt number
 948  *      client data arg ptr
 949  *      saved registers ptr
 950  * Outputs
 951  *      handled
 952  */
 953 static irqreturn_t
 954 ia64_mca_cmc_int_caller(int cmc_irq, void *arg, struct pt_regs *ptregs)
 955 {
 956         static int start_count = -1;
 957         unsigned int cpuid;
 958
 959         cpuid = smp_processor_id();
 960
 961         /* If first cpu, update count */
 962         if (start_count == -1)
 963                 start_count = IA64_LOG_COUNT(SAL_INFO_TYPE_CMC);
 964
 965         ia64_mca_cmc_int_handler(cmc_irq, arg, ptregs);
 966
 967         for (++cpuid ; cpuid < NR_CPUS && !cpu_online(cpuid) ; cpuid++);
 968
 969         if (cpuid < NR_CPUS) {
 970                 platform_send_ipi(cpuid, IA64_CMCP_VECTOR, IA64_IPI_DM_INT, 0);
 971         } else {
 972                 /* If no log record, switch out of polling mode */
 973                 if (start_count == IA64_LOG_COUNT(SAL_INFO_TYPE_CMC)) {
 974
 975                         printk(KERN_WARNING "Returning to interrupt driven CMC handler\n");
 976                         schedule_work(&cmc_enable_work);
 977                         cmc_polling_enabled = 0;
 978
 979                 } else {
 980
 981                         mod_timer(&cmc_poll_timer, jiffies + CMC_POLL_INTERVAL);
 982                 }
 983
 984                 start_count = -1;
 985         }
 986
 987         return IRQ_HANDLED;
 988 }
 989
 990 /*
 991  *  ia64_mca_cmc_poll
 992  *
 993  *      Poll for Corrected Machine Checks (CMCs)
 994  *
 995  * Inputs   :   dummy(unused)
 996  * Outputs  :   None
 997  *
 998  */
 999 static void
1000 ia64_mca_cmc_poll (unsigned long dummy)
1001 {
1002         /* Trigger a CMC interrupt cascade  */
1003         platform_send_ipi(first_cpu(cpu_online_map), IA64_CMCP_VECTOR, IA64_IPI_DM_INT, 0);
1004 }
1005
1006 /*
1007  *  ia64_mca_cpe_int_caller
1008  *
1009  *      Triggered by sw interrupt from CPE polling routine.  Calls
1010  *      real interrupt handler and either triggers a sw interrupt
1011  *      on the next cpu or does cleanup at the end.
1012  *
1013  * Inputs
1014  *      interrupt number
1015  *      client data arg ptr
1016  *      saved registers ptr
1017  * Outputs
1018  *      handled
1019  */
1020 #ifdef CONFIG_ACPI
1021
1022 static irqreturn_t
1023 ia64_mca_cpe_int_caller(int cpe_irq, void *arg, struct pt_regs *ptregs)
1024 {
1025         static int start_count = -1;
1026         static int poll_time = MIN_CPE_POLL_INTERVAL;
1027         unsigned int cpuid;
1028
1029         cpuid = smp_processor_id();
1030
1031         /* If first cpu, update count */
1032         if (start_count == -1)
1033                 start_count = IA64_LOG_COUNT(SAL_INFO_TYPE_CPE);
1034
1035         ia64_mca_cpe_int_handler(cpe_irq, arg, ptregs);
1036
1037         for (++cpuid ; cpuid < NR_CPUS && !cpu_online(cpuid) ; cpuid++);
1038
1039         if (cpuid < NR_CPUS) {
1040                 platform_send_ipi(cpuid, IA64_CPEP_VECTOR, IA64_IPI_DM_INT, 0);
1041         } else {
1042                 /*
1043                  * If a log was recorded, increase our polling frequency,
1044                  * otherwise, backoff or return to interrupt mode.
1045                  */
1046                 if (start_count != IA64_LOG_COUNT(SAL_INFO_TYPE_CPE)) {
1047                         poll_time = max(MIN_CPE_POLL_INTERVAL, poll_time / 2);
1048                 } else if (cpe_vector < 0) {
1049                         poll_time = min(MAX_CPE_POLL_INTERVAL, poll_time * 2);
1050                 } else {
1051                         poll_time = MIN_CPE_POLL_INTERVAL;
1052
1053                         printk(KERN_WARNING "Returning to interrupt driven CPE handler\n");
1054                         enable_irq(local_vector_to_irq(IA64_CPE_VECTOR));
1055                         cpe_poll_enabled = 0;
1056                 }
1057
1058                 if (cpe_poll_enabled)
1059                         mod_timer(&cpe_poll_timer, jiffies + poll_time);
1060                 start_count = -1;
1061         }
1062
1063         return IRQ_HANDLED;
1064 }
1065
1066 #endif /* CONFIG_ACPI */
1067
1068 /*
1069  *  ia64_mca_cpe_poll
1070  *
1071  *      Poll for Corrected Platform Errors (CPEs), trigger interrupt
1072  *      on first cpu, from there it will trickle through all the cpus.
1073  *
1074  * Inputs   :   dummy(unused)
1075  * Outputs  :   None
1076  *
1077  */
1078 static void
1079 ia64_mca_cpe_poll (unsigned long dummy)
1080 {
1081         /* Trigger a CPE interrupt cascade  */
1082         platform_send_ipi(first_cpu(cpu_online_map), IA64_CPEP_VECTOR, IA64_IPI_DM_INT, 0);
1083 }
1084
1085 /*
1086  * C portion of the OS INIT handler
1087  *
1088  * Called from ia64_monarch_init_handler
1089  *
1090  * Inputs: pointer to pt_regs where processor info was saved.
1091  *
1092  * Returns:
1093  *   0 if SAL must warm boot the System
1094  *   1 if SAL must return to interrupted context using PAL_MC_RESUME
1095  *
1096  */
1097 void
1098 ia64_init_handler (struct pt_regs *pt, struct switch_stack *sw)
1099 {
1100         pal_min_state_area_t *ms;
1101
1102         oops_in_progress = 1;   /* avoid deadlock in printk, but it makes recovery dodgy */
1103
1104         printk(KERN_INFO "Entered OS INIT handler. PSP=%lx\n",
1105                 ia64_sal_to_os_handoff_state.proc_state_param);
1106
1107         /*
1108          * Address of minstate area provided by PAL is physical,
1109          * uncacheable (bit 63 set). Convert to Linux virtual
1110          * address in region 6.
1111          */
1112         ms = (pal_min_state_area_t *)(ia64_sal_to_os_handoff_state.pal_min_state | (6ul<<61));
1113
1114         init_handler_platform(ms, pt, sw);      /* call platform specific routines */
1115 }
1116
1117 static int __init
1118 ia64_mca_disable_cpe_polling(char *str)
1119 {
1120         cpe_poll_enabled = 0;
1121         return 1;
1122 }
1123
1124 __setup("disable_cpe_poll", ia64_mca_disable_cpe_polling);
1125
1126 static struct irqaction cmci_irqaction = {
1127         .handler =      ia64_mca_cmc_int_handler,
1128         .flags =        SA_INTERRUPT,
1129         .name =         "cmc_hndlr"
1130 };
1131
1132 static struct irqaction cmcp_irqaction = {
1133         .handler =      ia64_mca_cmc_int_caller,
1134         .flags =        SA_INTERRUPT,
1135         .name =         "cmc_poll"
1136 };
1137
1138 static struct irqaction mca_rdzv_irqaction = {
1139         .handler =      ia64_mca_rendez_int_handler,
1140         .flags =        SA_INTERRUPT,
1141         .name =         "mca_rdzv"
1142 };
1143
1144 static struct irqaction mca_wkup_irqaction = {
1145         .handler =      ia64_mca_wakeup_int_handler,
1146         .flags =        SA_INTERRUPT,
1147         .name =         "mca_wkup"
1148 };
1149
1150 #ifdef CONFIG_ACPI
1151 static struct irqaction mca_cpe_irqaction = {
1152         .handler =      ia64_mca_cpe_int_handler,
1153         .flags =        SA_INTERRUPT,
1154         .name =         "cpe_hndlr"
1155 };
1156
1157 static struct irqaction mca_cpep_irqaction = {
1158         .handler =      ia64_mca_cpe_int_caller,
1159         .flags =        SA_INTERRUPT,
1160         .name =         "cpe_poll"
1161 };
1162 #endif /* CONFIG_ACPI */
1163
1164 /*
1165  * ia64_mca_init
1166  *
1167  *  Do all the system level mca specific initialization.
1168  *
1169  *      1. Register spinloop and wakeup request interrupt vectors
1170  *
1171  *      2. Register OS_MCA handler entry point
1172  *
1173  *      3. Register OS_INIT handler entry point
1174  *
1175  *  4. Initialize MCA/CMC/INIT related log buffers maintained by the OS.
1176  *
1177  *  Note that this initialization is done very early before some kernel
1178  *  services are available.
1179  *
1180  *  Inputs  :   None
1181  *
1182  *  Outputs :   None
1183  */
1184 void __init
1185 ia64_mca_init(void)
1186 {
1187         ia64_fptr_t *mon_init_ptr = (ia64_fptr_t *)ia64_monarch_init_handler;
1188         ia64_fptr_t *slave_init_ptr = (ia64_fptr_t *)ia64_slave_init_handler;
1189         ia64_fptr_t *mca_hldlr_ptr = (ia64_fptr_t *)ia64_os_mca_dispatch;
1190         int i;
1191         s64 rc;
1192         struct ia64_sal_retval isrv;
1193         u64 timeout = IA64_MCA_RENDEZ_TIMEOUT;  /* platform specific */
1194
1195         IA64_MCA_DEBUG("%s: begin\n", __FUNCTION__);
1196
1197         /* Clear the Rendez checkin flag for all cpus */
1198         for(i = 0 ; i < NR_CPUS; i++)
1199                 ia64_mc_info.imi_rendez_checkin[i] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
1200
1201         /*
1202          * Register the rendezvous spinloop and wakeup mechanism with SAL
1203          */
1204
1205         /* Register the rendezvous interrupt vector with SAL */
1206         while (1) {
1207                 isrv = ia64_sal_mc_set_params(SAL_MC_PARAM_RENDEZ_INT,
1208                                               SAL_MC_PARAM_MECHANISM_INT,
1209                                               IA64_MCA_RENDEZ_VECTOR,
1210                                               timeout,
1211                                               SAL_MC_PARAM_RZ_ALWAYS);
1212                 rc = isrv.status;
1213                 if (rc == 0)
1214                         break;
1215                 if (rc == -2) {
1216                         printk(KERN_INFO "Increasing MCA rendezvous timeout from "
1217                                 "%ld to %ld milliseconds\n", timeout, isrv.v0);
1218                         timeout = isrv.v0;
1219                         continue;
1220                 }
1221                 printk(KERN_ERR "Failed to register rendezvous interrupt "
1222                        "with SAL (status %ld)\n", rc);
1223                 return;
1224         }
1225
1226         /* Register the wakeup interrupt vector with SAL */
1227         isrv = ia64_sal_mc_set_params(SAL_MC_PARAM_RENDEZ_WAKEUP,
1228                                       SAL_MC_PARAM_MECHANISM_INT,
1229                                       IA64_MCA_WAKEUP_VECTOR,
1230                                       0, 0);
1231         rc = isrv.status;
1232         if (rc) {
1233                 printk(KERN_ERR "Failed to register wakeup interrupt with SAL "
1234                        "(status %ld)\n", rc);
1235                 return;
1236         }
1237
1238         IA64_MCA_DEBUG("%s: registered MCA rendezvous spinloop and wakeup mech.\n", __FUNCTION__);
1239
1240         ia64_mc_info.imi_mca_handler        = ia64_tpa(mca_hldlr_ptr->fp);
1241         /*
1242          * XXX - disable SAL checksum by setting size to 0; should be
1243          *      ia64_tpa(ia64_os_mca_dispatch_end) - ia64_tpa(ia64_os_mca_dispatch);
1244          */
1245         ia64_mc_info.imi_mca_handler_size       = 0;
1246
1247         /* Register the os mca handler with SAL */
1248         if ((rc = ia64_sal_set_vectors(SAL_VECTOR_OS_MCA,
1249                                        ia64_mc_info.imi_mca_handler,
1250                                        ia64_tpa(mca_hldlr_ptr->gp),
1251                                        ia64_mc_info.imi_mca_handler_size,
1252                                        0, 0, 0)))
1253         {
1254                 printk(KERN_ERR "Failed to register OS MCA handler with SAL "
1255                        "(status %ld)\n", rc);
1256                 return;
1257         }
1258
1259         IA64_MCA_DEBUG("%s: registered OS MCA handler with SAL at 0x%lx, gp = 0x%lx\n", __FUNCTION__,
1260                        ia64_mc_info.imi_mca_handler, ia64_tpa(mca_hldlr_ptr->gp));
1261
1262         /*
1263          * XXX - disable SAL checksum by setting size to 0, should be
1264          * size of the actual init handler in mca_asm.S.
1265          */
1266         ia64_mc_info.imi_monarch_init_handler           = ia64_tpa(mon_init_ptr->fp);
1267         ia64_mc_info.imi_monarch_init_handler_size      = 0;
1268         ia64_mc_info.imi_slave_init_handler             = ia64_tpa(slave_init_ptr->fp);
1269         ia64_mc_info.imi_slave_init_handler_size        = 0;
1270
1271         IA64_MCA_DEBUG("%s: OS INIT handler at %lx\n", __FUNCTION__,
1272                        ia64_mc_info.imi_monarch_init_handler);
1273
1274         /* Register the os init handler with SAL */
1275         if ((rc = ia64_sal_set_vectors(SAL_VECTOR_OS_INIT,
1276                                        ia64_mc_info.imi_monarch_init_handler,
1277                                        ia64_tpa(ia64_getreg(_IA64_REG_GP)),
1278                                        ia64_mc_info.imi_monarch_init_handler_size,
1279                                        ia64_mc_info.imi_slave_init_handler,
1280                                        ia64_tpa(ia64_getreg(_IA64_REG_GP)),
1281                                        ia64_mc_info.imi_slave_init_handler_size)))
1282         {
1283                 printk(KERN_ERR "Failed to register m/s INIT handlers with SAL "
1284                        "(status %ld)\n", rc);
1285                 return;
1286         }
1287
1288         IA64_MCA_DEBUG("%s: registered OS INIT handler with SAL\n", __FUNCTION__);
1289
1290         /*
1291          *  Configure the CMCI/P vector and handler. Interrupts for CMC are
1292          *  per-processor, so AP CMC interrupts are setup in smp_callin() (smpboot.c).
1293          */
1294         register_percpu_irq(IA64_CMC_VECTOR, &cmci_irqaction);
1295         register_percpu_irq(IA64_CMCP_VECTOR, &cmcp_irqaction);
1296         ia64_mca_cmc_vector_setup();       /* Setup vector on BSP & enable */
1297
1298         /* Setup the MCA rendezvous interrupt vector */
1299         register_percpu_irq(IA64_MCA_RENDEZ_VECTOR, &mca_rdzv_irqaction);
1300
1301         /* Setup the MCA wakeup interrupt vector */
1302         register_percpu_irq(IA64_MCA_WAKEUP_VECTOR, &mca_wkup_irqaction);
1303
1304 #ifdef CONFIG_ACPI
1305         /* Setup the CPEI/P vector and handler */
1306         {
1307                 irq_desc_t *desc;
1308                 unsigned int irq;
1309
1310                 cpe_vector = acpi_request_vector(ACPI_INTERRUPT_CPEI);
1311
1312                 if (cpe_vector >= 0) {
1313                         for (irq = 0; irq < NR_IRQS; ++irq)
1314                                 if (irq_to_vector(irq) == cpe_vector) {
1315                                         desc = irq_descp(irq);
1316                                         desc->status |= IRQ_PER_CPU;
1317                                         setup_irq(irq, &mca_cpe_irqaction);
1318                                 }
1319                         ia64_mca_register_cpev(cpe_vector);
1320                 }
1321                 register_percpu_irq(IA64_CPEP_VECTOR, &mca_cpep_irqaction);
1322         }
1323 #endif
1324
1325         /* Initialize the areas set aside by the OS to buffer the
1326          * platform/processor error states for MCA/INIT/CMC
1327          * handling.
1328          */
1329         ia64_log_init(SAL_INFO_TYPE_MCA);
1330         ia64_log_init(SAL_INFO_TYPE_INIT);
1331         ia64_log_init(SAL_INFO_TYPE_CMC);
1332         ia64_log_init(SAL_INFO_TYPE_CPE);
1333
1334         printk(KERN_INFO "MCA related initialization done\n");
1335 }
1336
1337 /*
1338  * ia64_mca_late_init
1339  *
1340  *      Opportunity to setup things that require initialization later
1341  *      than ia64_mca_init.  Setup a timer to poll for CPEs if the
1342  *      platform doesn't support an interrupt driven mechanism.
1343  *
1344  *  Inputs  :   None
1345  *  Outputs :   Status
1346  */
1347 static int __init
1348 ia64_mca_late_init(void)
1349 {
1350         init_timer(&cmc_poll_timer);
1351         cmc_poll_timer.function = ia64_mca_cmc_poll;
1352
1353         /* Reset to the correct state */
1354         cmc_polling_enabled = 0;
1355
1356         init_timer(&cpe_poll_timer);
1357         cpe_poll_timer.function = ia64_mca_cpe_poll;
1358
1359 #ifdef CONFIG_ACPI
1360         /* If platform doesn't support CPEI, get the timer going. */
1361         if (cpe_vector < 0 && cpe_poll_enabled) {
1362                 ia64_mca_cpe_poll(0UL);
1363         } else {
1364                 cpe_poll_enabled = 0;
1365         }
1366 #endif
1367
1368         return 0;
1369 }
1370
1371 device_initcall(ia64_mca_late_init);