2 * Copyright 2000 MontaVista Software Inc.
3 * Author: MontaVista Software, Inc.
4 * ppopov@mvista.com or source@mvista.com
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
14 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
17 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
18 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
19 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
20 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 #include <linux/config.h>
27 #include <linux/init.h>
28 #include <linux/sched.h>
29 #include <linux/ioport.h>
31 #include <linux/console.h>
32 #include <linux/delay.h>
35 #include <asm/bootinfo.h>
37 #include <asm/mipsregs.h>
38 #include <asm/reboot.h>
39 #include <asm/pgtable.h>
40 #include <asm/au1000.h>
41 #include <asm/pb1000.h>
43 #ifdef CONFIG_USB_OHCI
44 // Enable the workaround for the OHCI DoneHead
45 // register corruption problem.
46 #define CONFIG_AU1000_OHCI_FIX
47 ^^^^^^^^^^^^^^^^^^^^^^
48 !!! I shall not define symbols starting with CONFIG_ !!!
51 void board_reset (void)
55 void __init board_setup(void)
57 u32 pin_func, static_cfg0;
58 u32 sys_freqctrl, sys_clksrc;
59 u32 prid = read_c0_prid();
61 // set AUX clock to 12MHz * 8 = 96 MHz
62 au_writel(8, SYS_AUXPLL);
63 au_writel(0, SYS_PINSTATERD);
66 #if defined (CONFIG_USB_OHCI) || defined (CONFIG_AU1X00_USB_DEVICE)
67 /* zero and disable FREQ2 */
68 sys_freqctrl = au_readl(SYS_FREQCTRL0);
69 sys_freqctrl &= ~0xFFF00000;
70 au_writel(sys_freqctrl, SYS_FREQCTRL0);
72 /* zero and disable USBH/USBD clocks */
73 sys_clksrc = au_readl(SYS_CLKSRC);
74 sys_clksrc &= ~0x00007FE0;
75 au_writel(sys_clksrc, SYS_CLKSRC);
77 sys_freqctrl = au_readl(SYS_FREQCTRL0);
78 sys_freqctrl &= ~0xFFF00000;
80 sys_clksrc = au_readl(SYS_CLKSRC);
81 sys_clksrc &= ~0x00007FE0;
83 switch (prid & 0x000000FF)
88 /* CPU core freq to 48MHz to slow it way down... */
89 au_writel(4, SYS_CPUPLL);
92 * Setup 48MHz FREQ2 from CPUPLL for USB Host
94 /* FRDIV2=3 -> div by 8 of 384MHz -> 48MHz */
95 sys_freqctrl |= ((3<<22) | (1<<21) | (0<<20));
96 au_writel(sys_freqctrl, SYS_FREQCTRL0);
98 /* CPU core freq to 384MHz */
99 au_writel(0x20, SYS_CPUPLL);
101 printk("Au1000: 48MHz OHCI workaround enabled\n");
104 default: /* HC and newer */
105 // FREQ2 = aux/2 = 48 MHz
106 sys_freqctrl |= ((0<<22) | (1<<21) | (1<<20));
107 au_writel(sys_freqctrl, SYS_FREQCTRL0);
112 * Route 48MHz FREQ2 into USB Host and/or Device
114 #ifdef CONFIG_USB_OHCI
115 sys_clksrc |= ((4<<12) | (0<<11) | (0<<10));
117 #ifdef CONFIG_AU1X00_USB_DEVICE
118 sys_clksrc |= ((4<<7) | (0<<6) | (0<<5));
120 au_writel(sys_clksrc, SYS_CLKSRC);
122 // configure pins GPIO[14:9] as GPIO
123 pin_func = au_readl(SYS_PINFUNC) & (u32)(~0x8080);
125 #ifndef CONFIG_AU1X00_USB_DEVICE
126 // 2nd USB port is USB host
129 au_writel(pin_func, SYS_PINFUNC);
130 au_writel(0x2800, SYS_TRIOUTCLR);
131 au_writel(0x0030, SYS_OUTPUTCLR);
132 #endif // defined (CONFIG_USB_OHCI) || defined (CONFIG_AU1X00_USB_DEVICE)
134 // make gpio 15 an input (for interrupt line)
135 pin_func = au_readl(SYS_PINFUNC) & (u32)(~0x100);
136 // we don't need I2S, so make it available for GPIO[31:29]
138 au_writel(pin_func, SYS_PINFUNC);
140 au_writel(0x8000, SYS_TRIOUTCLR);
142 static_cfg0 = au_readl(MEM_STCFG0) & (u32)(~0xc00);
143 au_writel(static_cfg0, MEM_STCFG0);
145 // configure RCE2* for LCD
146 au_writel(0x00000004, MEM_STCFG2);
149 au_writel(0x09000000, MEM_STTIME2);
151 // Set 32-bit base address decoding for RCE2*
152 au_writel(0x10003ff0, MEM_STADDR2);
155 // expand CE0 to cover PCI
156 au_writel(0x11803e40, MEM_STADDR1);
158 // burst visibility on
159 au_writel(au_readl(MEM_STCFG0) | 0x1000, MEM_STCFG0);
161 au_writel(0x83, MEM_STCFG1); // ewait enabled, flash timing
162 au_writel(0x33030a10, MEM_STTIME1); // slower timing for FPGA
164 /* setup the static bus controller */
165 au_writel(0x00000002, MEM_STCFG3); /* type = PCMCIA */
166 au_writel(0x280E3D07, MEM_STTIME3); /* 250ns cycle time */
167 au_writel(0x10000000, MEM_STADDR3); /* any PCMCIA select */
170 au_writel(0, PCI_BRIDGE_CONFIG); // set extend byte to 0
171 au_writel(0, SDRAM_MBAR); // set mbar to 0
172 au_writel(0x2, SDRAM_CMD); // enable memory accesses
176 /* Enable Au1000 BCLK switching - note: sed1356 must not use
177 * its BCLK (Au1000 LCLK) for any timings */
178 switch (prid & 0x000000FF)
184 default: /* HC and newer */
185 /* Enable sys bus clock divider when IDLE state or no bus
187 au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL);