arch/mips/dec/setup.c

   1 /*
   2  * System-specific setup, especially interrupts.
   3  *
   4  * This file is subject to the terms and conditions of the GNU General Public
   5  * License.  See the file "COPYING" in the main directory of this archive
   6  * for more details.
   7  *
   8  * Copyright (C) 1998 Harald Koerfgen
   9  * Copyright (C) 2000, 2001, 2002, 2003, 2005  Maciej W. Rozycki
  10  */
  11 #include <linux/console.h>
  12 #include <linux/init.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/ioport.h>
  15 #include <linux/module.h>
  16 #include <linux/param.h>
  17 #include <linux/sched.h>
  18 #include <linux/spinlock.h>
  19 #include <linux/types.h>
  20 #include <linux/pm.h>
  21
  22 #include <asm/bootinfo.h>
  23 #include <asm/cpu.h>
  24 #include <asm/cpu-features.h>
  25 #include <asm/irq.h>
  26 #include <asm/irq_cpu.h>
  27 #include <asm/mipsregs.h>
  28 #include <asm/reboot.h>
  29 #include <asm/time.h>
  30 #include <asm/traps.h>
  31 #include <asm/wbflush.h>
  32
  33 #include <asm/dec/interrupts.h>
  34 #include <asm/dec/ioasic.h>
  35 #include <asm/dec/ioasic_addrs.h>
  36 #include <asm/dec/ioasic_ints.h>
  37 #include <asm/dec/kn01.h>
  38 #include <asm/dec/kn02.h>
  39 #include <asm/dec/kn02ba.h>
  40 #include <asm/dec/kn02ca.h>
  41 #include <asm/dec/kn03.h>
  42 #include <asm/dec/kn230.h>
  43 #include <asm/dec/system.h>
  44
  45
  46 extern void dec_machine_restart(char *command);
  47 extern void dec_machine_halt(void);
  48 extern void dec_machine_power_off(void);
  49 extern irqreturn_t dec_intr_halt(int irq, void *dev_id, struct pt_regs *regs);
  50
  51 extern asmlinkage void decstation_handle_int(void);
  52
  53 unsigned long dec_kn_slot_base, dec_kn_slot_size;
  54
  55 EXPORT_SYMBOL(dec_kn_slot_base);
  56 EXPORT_SYMBOL(dec_kn_slot_size);
  57
  58 spinlock_t ioasic_ssr_lock;
  59
  60 volatile u32 *ioasic_base;
  61
  62 EXPORT_SYMBOL(ioasic_base);
  63
  64 /*
  65  * IRQ routing and priority tables.  Priorites are set as follows:
  66  *
  67  *              KN01    KN230   KN02    KN02-BA KN02-CA KN03
  68  *
  69  * MEMORY       CPU     CPU     CPU     ASIC    CPU     CPU
  70  * RTC          CPU     CPU     CPU     ASIC    CPU     CPU
  71  * DMA          -       -       -       ASIC    ASIC    ASIC
  72  * SERIAL0      CPU     CPU     CSR     ASIC    ASIC    ASIC
  73  * SERIAL1      -       -       -       ASIC    -       ASIC
  74  * SCSI         CPU     CPU     CSR     ASIC    ASIC    ASIC
  75  * ETHERNET     CPU     *       CSR     ASIC    ASIC    ASIC
  76  * other        -       -       -       ASIC    -       -
  77  * TC2          -       -       CSR     CPU     ASIC    ASIC
  78  * TC1          -       -       CSR     CPU     ASIC    ASIC
  79  * TC0          -       -       CSR     CPU     ASIC    ASIC
  80  * other        -       CPU     -       CPU     ASIC    ASIC
  81  * other        -       -       -       -       CPU     CPU
  82  *
  83  * * -- shared with SCSI
  84  */
  85
  86 int dec_interrupt[DEC_NR_INTS] = {
  87         [0 ... DEC_NR_INTS - 1] = -1
  88 };
  89
  90 EXPORT_SYMBOL(dec_interrupt);
  91
  92 int_ptr cpu_mask_nr_tbl[DEC_MAX_CPU_INTS][2] = {
  93         { { .i = ~0 }, { .p = dec_intr_unimplemented } },
  94 };
  95 int_ptr asic_mask_nr_tbl[DEC_MAX_ASIC_INTS][2] = {
  96         { { .i = ~0 }, { .p = asic_intr_unimplemented } },
  97 };
  98 int cpu_fpu_mask = DEC_CPU_IRQ_MASK(DEC_CPU_INR_FPU);
  99
 100 static struct irqaction ioirq = {
 101         .handler = no_action,
 102         .name = "cascade",
 103 };
 104 static struct irqaction fpuirq = {
 105         .handler = no_action,
 106         .name = "fpu",
 107 };
 108
 109 static struct irqaction busirq = {
 110         .flags = SA_INTERRUPT,
 111         .name = "bus error",
 112 };
 113
 114 static struct irqaction haltirq = {
 115         .handler = dec_intr_halt,
 116         .name = "halt",
 117 };
 118
 119
 120 /*
 121  * Bus error (DBE/IBE exceptions and bus interrupts) handling setup.
 122  */
 123 static void __init dec_be_init(void)
 124 {
 125         switch (mips_machtype) {
 126         case MACH_DS23100:      /* DS2100/DS3100 Pmin/Pmax */
 127                 board_be_handler = dec_kn01_be_handler;
 128                 busirq.handler = dec_kn01_be_interrupt;
 129                 busirq.flags |= SA_SHIRQ;
 130                 dec_kn01_be_init();
 131                 break;
 132         case MACH_DS5000_1XX:   /* DS5000/1xx 3min */
 133         case MACH_DS5000_XX:    /* DS5000/xx Maxine */
 134                 board_be_handler = dec_kn02xa_be_handler;
 135                 busirq.handler = dec_kn02xa_be_interrupt;
 136                 dec_kn02xa_be_init();
 137                 break;
 138         case MACH_DS5000_200:   /* DS5000/200 3max */
 139         case MACH_DS5000_2X0:   /* DS5000/240 3max+ */
 140         case MACH_DS5900:       /* DS5900 bigmax */
 141                 board_be_handler = dec_ecc_be_handler;
 142                 busirq.handler = dec_ecc_be_interrupt;
 143                 dec_ecc_be_init();
 144                 break;
 145         }
 146 }
 147
 148
 149 extern void dec_time_init(void);
 150 extern void dec_timer_setup(struct irqaction *);
 151
 152 void __init plat_setup(void)
 153 {
 154         board_be_init = dec_be_init;
 155         board_time_init = dec_time_init;
 156         board_timer_setup = dec_timer_setup;
 157
 158         wbflush_setup();
 159
 160         _machine_restart = dec_machine_restart;
 161         _machine_halt = dec_machine_halt;
 162         pm_power_off = dec_machine_power_off;
 163
 164         ioport_resource.start = ~0UL;
 165         ioport_resource.end = 0UL;
 166 }
 167
 168 /*
 169  * Machine-specific initialisation for KN01, aka DS2100 (aka Pmin)
 170  * or DS3100 (aka Pmax).
 171  */
 172 static int kn01_interrupt[DEC_NR_INTS] __initdata = {
 173         [DEC_IRQ_CASCADE]       = -1,
 174         [DEC_IRQ_AB_RECV]       = -1,
 175         [DEC_IRQ_AB_XMIT]       = -1,
 176         [DEC_IRQ_DZ11]          = DEC_CPU_IRQ_NR(KN01_CPU_INR_DZ11),
 177         [DEC_IRQ_ASC]           = -1,
 178         [DEC_IRQ_FLOPPY]        = -1,
 179         [DEC_IRQ_FPU]           = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
 180         [DEC_IRQ_HALT]          = -1,
 181         [DEC_IRQ_ISDN]          = -1,
 182         [DEC_IRQ_LANCE]         = DEC_CPU_IRQ_NR(KN01_CPU_INR_LANCE),
 183         [DEC_IRQ_BUS]           = DEC_CPU_IRQ_NR(KN01_CPU_INR_BUS),
 184         [DEC_IRQ_PSU]           = -1,
 185         [DEC_IRQ_RTC]           = DEC_CPU_IRQ_NR(KN01_CPU_INR_RTC),
 186         [DEC_IRQ_SCC0]          = -1,
 187         [DEC_IRQ_SCC1]          = -1,
 188         [DEC_IRQ_SII]           = DEC_CPU_IRQ_NR(KN01_CPU_INR_SII),
 189         [DEC_IRQ_TC0]           = -1,
 190         [DEC_IRQ_TC1]           = -1,
 191         [DEC_IRQ_TC2]           = -1,
 192         [DEC_IRQ_TIMER]         = -1,
 193         [DEC_IRQ_VIDEO]         = DEC_CPU_IRQ_NR(KN01_CPU_INR_VIDEO),
 194         [DEC_IRQ_ASC_MERR]      = -1,
 195         [DEC_IRQ_ASC_ERR]       = -1,
 196         [DEC_IRQ_ASC_DMA]       = -1,
 197         [DEC_IRQ_FLOPPY_ERR]    = -1,
 198         [DEC_IRQ_ISDN_ERR]      = -1,
 199         [DEC_IRQ_ISDN_RXDMA]    = -1,
 200         [DEC_IRQ_ISDN_TXDMA]    = -1,
 201         [DEC_IRQ_LANCE_MERR]    = -1,
 202         [DEC_IRQ_SCC0A_RXERR]   = -1,
 203         [DEC_IRQ_SCC0A_RXDMA]   = -1,
 204         [DEC_IRQ_SCC0A_TXERR]   = -1,
 205         [DEC_IRQ_SCC0A_TXDMA]   = -1,
 206         [DEC_IRQ_AB_RXERR]      = -1,
 207         [DEC_IRQ_AB_RXDMA]      = -1,
 208         [DEC_IRQ_AB_TXERR]      = -1,
 209         [DEC_IRQ_AB_TXDMA]      = -1,
 210         [DEC_IRQ_SCC1A_RXERR]   = -1,
 211         [DEC_IRQ_SCC1A_RXDMA]   = -1,
 212         [DEC_IRQ_SCC1A_TXERR]   = -1,
 213         [DEC_IRQ_SCC1A_TXDMA]   = -1,
 214 };
 215
 216 static int_ptr kn01_cpu_mask_nr_tbl[][2] __initdata = {
 217         { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_BUS) },
 218                 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_BUS) } },
 219         { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_RTC) },
 220                 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_RTC) } },
 221         { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_DZ11) },
 222                 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_DZ11) } },
 223         { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_SII) },
 224                 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_SII) } },
 225         { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_LANCE) },
 226                 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_LANCE) } },
 227         { { .i = DEC_CPU_IRQ_ALL },
 228                 { .p = cpu_all_int } },
 229 };
 230
 231 static void __init dec_init_kn01(void)
 232 {
 233         /* IRQ routing. */
 234         memcpy(&dec_interrupt, &kn01_interrupt,
 235                 sizeof(kn01_interrupt));
 236
 237         /* CPU IRQ priorities. */
 238         memcpy(&cpu_mask_nr_tbl, &kn01_cpu_mask_nr_tbl,
 239                 sizeof(kn01_cpu_mask_nr_tbl));
 240
 241         mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
 242
 243 }                               /* dec_init_kn01 */
 244
 245
 246 /*
 247  * Machine-specific initialisation for KN230, aka DS5100, aka MIPSmate.
 248  */
 249 static int kn230_interrupt[DEC_NR_INTS] __initdata = {
 250         [DEC_IRQ_CASCADE]       = -1,
 251         [DEC_IRQ_AB_RECV]       = -1,
 252         [DEC_IRQ_AB_XMIT]       = -1,
 253         [DEC_IRQ_DZ11]          = DEC_CPU_IRQ_NR(KN230_CPU_INR_DZ11),
 254         [DEC_IRQ_ASC]           = -1,
 255         [DEC_IRQ_FLOPPY]        = -1,
 256         [DEC_IRQ_FPU]           = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
 257         [DEC_IRQ_HALT]          = DEC_CPU_IRQ_NR(KN230_CPU_INR_HALT),
 258         [DEC_IRQ_ISDN]          = -1,
 259         [DEC_IRQ_LANCE]         = DEC_CPU_IRQ_NR(KN230_CPU_INR_LANCE),
 260         [DEC_IRQ_BUS]           = DEC_CPU_IRQ_NR(KN230_CPU_INR_BUS),
 261         [DEC_IRQ_PSU]           = -1,
 262         [DEC_IRQ_RTC]           = DEC_CPU_IRQ_NR(KN230_CPU_INR_RTC),
 263         [DEC_IRQ_SCC0]          = -1,
 264         [DEC_IRQ_SCC1]          = -1,
 265         [DEC_IRQ_SII]           = DEC_CPU_IRQ_NR(KN230_CPU_INR_SII),
 266         [DEC_IRQ_TC0]           = -1,
 267         [DEC_IRQ_TC1]           = -1,
 268         [DEC_IRQ_TC2]           = -1,
 269         [DEC_IRQ_TIMER]         = -1,
 270         [DEC_IRQ_VIDEO]         = -1,
 271         [DEC_IRQ_ASC_MERR]      = -1,
 272         [DEC_IRQ_ASC_ERR]       = -1,
 273         [DEC_IRQ_ASC_DMA]       = -1,
 274         [DEC_IRQ_FLOPPY_ERR]    = -1,
 275         [DEC_IRQ_ISDN_ERR]      = -1,
 276         [DEC_IRQ_ISDN_RXDMA]    = -1,
 277         [DEC_IRQ_ISDN_TXDMA]    = -1,
 278         [DEC_IRQ_LANCE_MERR]    = -1,
 279         [DEC_IRQ_SCC0A_RXERR]   = -1,
 280         [DEC_IRQ_SCC0A_RXDMA]   = -1,
 281         [DEC_IRQ_SCC0A_TXERR]   = -1,
 282         [DEC_IRQ_SCC0A_TXDMA]   = -1,
 283         [DEC_IRQ_AB_RXERR]      = -1,
 284         [DEC_IRQ_AB_RXDMA]      = -1,
 285         [DEC_IRQ_AB_TXERR]      = -1,
 286         [DEC_IRQ_AB_TXDMA]      = -1,
 287         [DEC_IRQ_SCC1A_RXERR]   = -1,
 288         [DEC_IRQ_SCC1A_RXDMA]   = -1,
 289         [DEC_IRQ_SCC1A_TXERR]   = -1,
 290         [DEC_IRQ_SCC1A_TXDMA]   = -1,
 291 };
 292
 293 static int_ptr kn230_cpu_mask_nr_tbl[][2] __initdata = {
 294         { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_BUS) },
 295                 { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_BUS) } },
 296         { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_RTC) },
 297                 { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_RTC) } },
 298         { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_DZ11) },
 299                 { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_DZ11) } },
 300         { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_SII) },
 301                 { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_SII) } },
 302         { { .i = DEC_CPU_IRQ_ALL },
 303                 { .p = cpu_all_int } },
 304 };
 305
 306 static void __init dec_init_kn230(void)
 307 {
 308         /* IRQ routing. */
 309         memcpy(&dec_interrupt, &kn230_interrupt,
 310                 sizeof(kn230_interrupt));
 311
 312         /* CPU IRQ priorities. */
 313         memcpy(&cpu_mask_nr_tbl, &kn230_cpu_mask_nr_tbl,
 314                 sizeof(kn230_cpu_mask_nr_tbl));
 315
 316         mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
 317
 318 }                               /* dec_init_kn230 */
 319
 320
 321 /*
 322  * Machine-specific initialisation for KN02, aka DS5000/200, aka 3max.
 323  */
 324 static int kn02_interrupt[DEC_NR_INTS] __initdata = {
 325         [DEC_IRQ_CASCADE]       = DEC_CPU_IRQ_NR(KN02_CPU_INR_CASCADE),
 326         [DEC_IRQ_AB_RECV]       = -1,
 327         [DEC_IRQ_AB_XMIT]       = -1,
 328         [DEC_IRQ_DZ11]          = KN02_IRQ_NR(KN02_CSR_INR_DZ11),
 329         [DEC_IRQ_ASC]           = KN02_IRQ_NR(KN02_CSR_INR_ASC),
 330         [DEC_IRQ_FLOPPY]        = -1,
 331         [DEC_IRQ_FPU]           = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
 332         [DEC_IRQ_HALT]          = -1,
 333         [DEC_IRQ_ISDN]          = -1,
 334         [DEC_IRQ_LANCE]         = KN02_IRQ_NR(KN02_CSR_INR_LANCE),
 335         [DEC_IRQ_BUS]           = DEC_CPU_IRQ_NR(KN02_CPU_INR_BUS),
 336         [DEC_IRQ_PSU]           = -1,
 337         [DEC_IRQ_RTC]           = DEC_CPU_IRQ_NR(KN02_CPU_INR_RTC),
 338         [DEC_IRQ_SCC0]          = -1,
 339         [DEC_IRQ_SCC1]          = -1,
 340         [DEC_IRQ_SII]           = -1,
 341         [DEC_IRQ_TC0]           = KN02_IRQ_NR(KN02_CSR_INR_TC0),
 342         [DEC_IRQ_TC1]           = KN02_IRQ_NR(KN02_CSR_INR_TC1),
 343         [DEC_IRQ_TC2]           = KN02_IRQ_NR(KN02_CSR_INR_TC2),
 344         [DEC_IRQ_TIMER]         = -1,
 345         [DEC_IRQ_VIDEO]         = -1,
 346         [DEC_IRQ_ASC_MERR]      = -1,
 347         [DEC_IRQ_ASC_ERR]       = -1,
 348         [DEC_IRQ_ASC_DMA]       = -1,
 349         [DEC_IRQ_FLOPPY_ERR]    = -1,
 350         [DEC_IRQ_ISDN_ERR]      = -1,
 351         [DEC_IRQ_ISDN_RXDMA]    = -1,
 352         [DEC_IRQ_ISDN_TXDMA]    = -1,
 353         [DEC_IRQ_LANCE_MERR]    = -1,
 354         [DEC_IRQ_SCC0A_RXERR]   = -1,
 355         [DEC_IRQ_SCC0A_RXDMA]   = -1,
 356         [DEC_IRQ_SCC0A_TXERR]   = -1,
 357         [DEC_IRQ_SCC0A_TXDMA]   = -1,
 358         [DEC_IRQ_AB_RXERR]      = -1,
 359         [DEC_IRQ_AB_RXDMA]      = -1,
 360         [DEC_IRQ_AB_TXERR]      = -1,
 361         [DEC_IRQ_AB_TXDMA]      = -1,
 362         [DEC_IRQ_SCC1A_RXERR]   = -1,
 363         [DEC_IRQ_SCC1A_RXDMA]   = -1,
 364         [DEC_IRQ_SCC1A_TXERR]   = -1,
 365         [DEC_IRQ_SCC1A_TXDMA]   = -1,
 366 };
 367
 368 static int_ptr kn02_cpu_mask_nr_tbl[][2] __initdata = {
 369         { { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_BUS) },
 370                 { .i = DEC_CPU_IRQ_NR(KN02_CPU_INR_BUS) } },
 371         { { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_RTC) },
 372                 { .i = DEC_CPU_IRQ_NR(KN02_CPU_INR_RTC) } },
 373         { { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_CASCADE) },
 374                 { .p = kn02_io_int } },
 375         { { .i = DEC_CPU_IRQ_ALL },
 376                 { .p = cpu_all_int } },
 377 };
 378
 379 static int_ptr kn02_asic_mask_nr_tbl[][2] __initdata = {
 380         { { .i = KN02_IRQ_MASK(KN02_CSR_INR_DZ11) },
 381                 { .i = KN02_IRQ_NR(KN02_CSR_INR_DZ11) } },
 382         { { .i = KN02_IRQ_MASK(KN02_CSR_INR_ASC) },
 383                 { .i = KN02_IRQ_NR(KN02_CSR_INR_ASC) } },
 384         { { .i = KN02_IRQ_MASK(KN02_CSR_INR_LANCE) },
 385                 { .i = KN02_IRQ_NR(KN02_CSR_INR_LANCE) } },
 386         { { .i = KN02_IRQ_MASK(KN02_CSR_INR_TC2) },
 387                 { .i = KN02_IRQ_NR(KN02_CSR_INR_TC2) } },
 388         { { .i = KN02_IRQ_MASK(KN02_CSR_INR_TC1) },
 389                 { .i = KN02_IRQ_NR(KN02_CSR_INR_TC1) } },
 390         { { .i = KN02_IRQ_MASK(KN02_CSR_INR_TC0) },
 391                 { .i = KN02_IRQ_NR(KN02_CSR_INR_TC0) } },
 392         { { .i = KN02_IRQ_ALL },
 393                 { .p = kn02_all_int } },
 394 };
 395
 396 static void __init dec_init_kn02(void)
 397 {
 398         /* IRQ routing. */
 399         memcpy(&dec_interrupt, &kn02_interrupt,
 400                 sizeof(kn02_interrupt));
 401
 402         /* CPU IRQ priorities. */
 403         memcpy(&cpu_mask_nr_tbl, &kn02_cpu_mask_nr_tbl,
 404                 sizeof(kn02_cpu_mask_nr_tbl));
 405
 406         /* KN02 CSR IRQ priorities. */
 407         memcpy(&asic_mask_nr_tbl, &kn02_asic_mask_nr_tbl,
 408                 sizeof(kn02_asic_mask_nr_tbl));
 409
 410         mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
 411         init_kn02_irqs(KN02_IRQ_BASE);
 412
 413 }                               /* dec_init_kn02 */
 414
 415
 416 /*
 417  * Machine-specific initialisation for KN02-BA, aka DS5000/1xx
 418  * (xx = 20, 25, 33), aka 3min.  Also applies to KN04(-BA), aka
 419  * DS5000/150, aka 4min.
 420  */
 421 static int kn02ba_interrupt[DEC_NR_INTS] __initdata = {
 422         [DEC_IRQ_CASCADE]       = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_CASCADE),
 423         [DEC_IRQ_AB_RECV]       = -1,
 424         [DEC_IRQ_AB_XMIT]       = -1,
 425         [DEC_IRQ_DZ11]          = -1,
 426         [DEC_IRQ_ASC]           = IO_IRQ_NR(KN02BA_IO_INR_ASC),
 427         [DEC_IRQ_FLOPPY]        = -1,
 428         [DEC_IRQ_FPU]           = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
 429         [DEC_IRQ_HALT]          = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_HALT),
 430         [DEC_IRQ_ISDN]          = -1,
 431         [DEC_IRQ_LANCE]         = IO_IRQ_NR(KN02BA_IO_INR_LANCE),
 432         [DEC_IRQ_BUS]           = IO_IRQ_NR(KN02BA_IO_INR_BUS),
 433         [DEC_IRQ_PSU]           = IO_IRQ_NR(KN02BA_IO_INR_PSU),
 434         [DEC_IRQ_RTC]           = IO_IRQ_NR(KN02BA_IO_INR_RTC),
 435         [DEC_IRQ_SCC0]          = IO_IRQ_NR(KN02BA_IO_INR_SCC0),
 436         [DEC_IRQ_SCC1]          = IO_IRQ_NR(KN02BA_IO_INR_SCC1),
 437         [DEC_IRQ_SII]           = -1,
 438         [DEC_IRQ_TC0]           = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC0),
 439         [DEC_IRQ_TC1]           = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC1),
 440         [DEC_IRQ_TC2]           = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC2),
 441         [DEC_IRQ_TIMER]         = -1,
 442         [DEC_IRQ_VIDEO]         = -1,
 443         [DEC_IRQ_ASC_MERR]      = IO_IRQ_NR(IO_INR_ASC_MERR),
 444         [DEC_IRQ_ASC_ERR]       = IO_IRQ_NR(IO_INR_ASC_ERR),
 445         [DEC_IRQ_ASC_DMA]       = IO_IRQ_NR(IO_INR_ASC_DMA),
 446         [DEC_IRQ_FLOPPY_ERR]    = -1,
 447         [DEC_IRQ_ISDN_ERR]      = -1,
 448         [DEC_IRQ_ISDN_RXDMA]    = -1,
 449         [DEC_IRQ_ISDN_TXDMA]    = -1,
 450         [DEC_IRQ_LANCE_MERR]    = IO_IRQ_NR(IO_INR_LANCE_MERR),
 451         [DEC_IRQ_SCC0A_RXERR]   = IO_IRQ_NR(IO_INR_SCC0A_RXERR),
 452         [DEC_IRQ_SCC0A_RXDMA]   = IO_IRQ_NR(IO_INR_SCC0A_RXDMA),
 453         [DEC_IRQ_SCC0A_TXERR]   = IO_IRQ_NR(IO_INR_SCC0A_TXERR),
 454         [DEC_IRQ_SCC0A_TXDMA]   = IO_IRQ_NR(IO_INR_SCC0A_TXDMA),
 455         [DEC_IRQ_AB_RXERR]      = -1,
 456         [DEC_IRQ_AB_RXDMA]      = -1,
 457         [DEC_IRQ_AB_TXERR]      = -1,
 458         [DEC_IRQ_AB_TXDMA]      = -1,
 459         [DEC_IRQ_SCC1A_RXERR]   = IO_IRQ_NR(IO_INR_SCC1A_RXERR),
 460         [DEC_IRQ_SCC1A_RXDMA]   = IO_IRQ_NR(IO_INR_SCC1A_RXDMA),
 461         [DEC_IRQ_SCC1A_TXERR]   = IO_IRQ_NR(IO_INR_SCC1A_TXERR),
 462         [DEC_IRQ_SCC1A_TXDMA]   = IO_IRQ_NR(IO_INR_SCC1A_TXDMA),
 463 };
 464
 465 static int_ptr kn02ba_cpu_mask_nr_tbl[][2] __initdata = {
 466         { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_CASCADE) },
 467                 { .p = kn02xa_io_int } },
 468         { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC2) },
 469                 { .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC2) } },
 470         { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC1) },
 471                 { .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC1) } },
 472         { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC0) },
 473                 { .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC0) } },
 474         { { .i = DEC_CPU_IRQ_ALL },
 475                 { .p = cpu_all_int } },
 476 };
 477
 478 static int_ptr kn02ba_asic_mask_nr_tbl[][2] __initdata = {
 479         { { .i = IO_IRQ_MASK(KN02BA_IO_INR_BUS) },
 480                 { .i = IO_IRQ_NR(KN02BA_IO_INR_BUS) } },
 481         { { .i = IO_IRQ_MASK(KN02BA_IO_INR_RTC) },
 482                 { .i = IO_IRQ_NR(KN02BA_IO_INR_RTC) } },
 483         { { .i = IO_IRQ_DMA },
 484                 { .p = asic_dma_int } },
 485         { { .i = IO_IRQ_MASK(KN02BA_IO_INR_SCC0) },
 486                 { .i = IO_IRQ_NR(KN02BA_IO_INR_SCC0) } },
 487         { { .i = IO_IRQ_MASK(KN02BA_IO_INR_SCC1) },
 488                 { .i = IO_IRQ_NR(KN02BA_IO_INR_SCC1) } },
 489         { { .i = IO_IRQ_MASK(KN02BA_IO_INR_ASC) },
 490                 { .i = IO_IRQ_NR(KN02BA_IO_INR_ASC) } },
 491         { { .i = IO_IRQ_MASK(KN02BA_IO_INR_LANCE) },
 492                 { .i = IO_IRQ_NR(KN02BA_IO_INR_LANCE) } },
 493         { { .i = IO_IRQ_ALL },
 494                 { .p = asic_all_int } },
 495 };
 496
 497 static void __init dec_init_kn02ba(void)
 498 {
 499         /* IRQ routing. */
 500         memcpy(&dec_interrupt, &kn02ba_interrupt,
 501                 sizeof(kn02ba_interrupt));
 502
 503         /* CPU IRQ priorities. */
 504         memcpy(&cpu_mask_nr_tbl, &kn02ba_cpu_mask_nr_tbl,
 505                 sizeof(kn02ba_cpu_mask_nr_tbl));
 506
 507         /* I/O ASIC IRQ priorities. */
 508         memcpy(&asic_mask_nr_tbl, &kn02ba_asic_mask_nr_tbl,
 509                 sizeof(kn02ba_asic_mask_nr_tbl));
 510
 511         mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
 512         init_ioasic_irqs(IO_IRQ_BASE);
 513
 514 }                               /* dec_init_kn02ba */
 515
 516
 517 /*
 518  * Machine-specific initialisation for KN02-CA, aka DS5000/xx,
 519  * (xx = 20, 25, 33), aka MAXine.  Also applies to KN04(-CA), aka
 520  * DS5000/50, aka 4MAXine.
 521  */
 522 static int kn02ca_interrupt[DEC_NR_INTS] __initdata = {
 523         [DEC_IRQ_CASCADE]       = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_CASCADE),
 524         [DEC_IRQ_AB_RECV]       = IO_IRQ_NR(KN02CA_IO_INR_AB_RECV),
 525         [DEC_IRQ_AB_XMIT]       = IO_IRQ_NR(KN02CA_IO_INR_AB_XMIT),
 526         [DEC_IRQ_DZ11]          = -1,
 527         [DEC_IRQ_ASC]           = IO_IRQ_NR(KN02CA_IO_INR_ASC),
 528         [DEC_IRQ_FLOPPY]        = IO_IRQ_NR(KN02CA_IO_INR_FLOPPY),
 529         [DEC_IRQ_FPU]           = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
 530         [DEC_IRQ_HALT]          = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_HALT),
 531         [DEC_IRQ_ISDN]          = IO_IRQ_NR(KN02CA_IO_INR_ISDN),
 532         [DEC_IRQ_LANCE]         = IO_IRQ_NR(KN02CA_IO_INR_LANCE),
 533         [DEC_IRQ_BUS]           = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_BUS),
 534         [DEC_IRQ_PSU]           = -1,
 535         [DEC_IRQ_RTC]           = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_RTC),
 536         [DEC_IRQ_SCC0]          = IO_IRQ_NR(KN02CA_IO_INR_SCC0),
 537         [DEC_IRQ_SCC1]          = -1,
 538         [DEC_IRQ_SII]           = -1,
 539         [DEC_IRQ_TC0]           = IO_IRQ_NR(KN02CA_IO_INR_TC0),
 540         [DEC_IRQ_TC1]           = IO_IRQ_NR(KN02CA_IO_INR_TC1),
 541         [DEC_IRQ_TC2]           = -1,
 542         [DEC_IRQ_TIMER]         = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_TIMER),
 543         [DEC_IRQ_VIDEO]         = IO_IRQ_NR(KN02CA_IO_INR_VIDEO),
 544         [DEC_IRQ_ASC_MERR]      = IO_IRQ_NR(IO_INR_ASC_MERR),
 545         [DEC_IRQ_ASC_ERR]       = IO_IRQ_NR(IO_INR_ASC_ERR),
 546         [DEC_IRQ_ASC_DMA]       = IO_IRQ_NR(IO_INR_ASC_DMA),
 547         [DEC_IRQ_FLOPPY_ERR]    = IO_IRQ_NR(IO_INR_FLOPPY_ERR),
 548         [DEC_IRQ_ISDN_ERR]      = IO_IRQ_NR(IO_INR_ISDN_ERR),
 549         [DEC_IRQ_ISDN_RXDMA]    = IO_IRQ_NR(IO_INR_ISDN_RXDMA),
 550         [DEC_IRQ_ISDN_TXDMA]    = IO_IRQ_NR(IO_INR_ISDN_TXDMA),
 551         [DEC_IRQ_LANCE_MERR]    = IO_IRQ_NR(IO_INR_LANCE_MERR),
 552         [DEC_IRQ_SCC0A_RXERR]   = IO_IRQ_NR(IO_INR_SCC0A_RXERR),
 553         [DEC_IRQ_SCC0A_RXDMA]   = IO_IRQ_NR(IO_INR_SCC0A_RXDMA),
 554         [DEC_IRQ_SCC0A_TXERR]   = IO_IRQ_NR(IO_INR_SCC0A_TXERR),
 555         [DEC_IRQ_SCC0A_TXDMA]   = IO_IRQ_NR(IO_INR_SCC0A_TXDMA),
 556         [DEC_IRQ_AB_RXERR]      = IO_IRQ_NR(IO_INR_AB_RXERR),
 557         [DEC_IRQ_AB_RXDMA]      = IO_IRQ_NR(IO_INR_AB_RXDMA),
 558         [DEC_IRQ_AB_TXERR]      = IO_IRQ_NR(IO_INR_AB_TXERR),
 559         [DEC_IRQ_AB_TXDMA]      = IO_IRQ_NR(IO_INR_AB_TXDMA),
 560         [DEC_IRQ_SCC1A_RXERR]   = -1,
 561         [DEC_IRQ_SCC1A_RXDMA]   = -1,
 562         [DEC_IRQ_SCC1A_TXERR]   = -1,
 563         [DEC_IRQ_SCC1A_TXDMA]   = -1,
 564 };
 565
 566 static int_ptr kn02ca_cpu_mask_nr_tbl[][2] __initdata = {
 567         { { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_BUS) },
 568                 { .i = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_BUS) } },
 569         { { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_RTC) },
 570                 { .i = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_RTC) } },
 571         { { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_CASCADE) },
 572                 { .p = kn02xa_io_int } },
 573         { { .i = DEC_CPU_IRQ_ALL },
 574                 { .p = cpu_all_int } },
 575 };
 576
 577 static int_ptr kn02ca_asic_mask_nr_tbl[][2] __initdata = {
 578         { { .i = IO_IRQ_DMA },
 579                 { .p = asic_dma_int } },
 580         { { .i = IO_IRQ_MASK(KN02CA_IO_INR_SCC0) },
 581                 { .i = IO_IRQ_NR(KN02CA_IO_INR_SCC0) } },
 582         { { .i = IO_IRQ_MASK(KN02CA_IO_INR_ASC) },
 583                 { .i = IO_IRQ_NR(KN02CA_IO_INR_ASC) } },
 584         { { .i = IO_IRQ_MASK(KN02CA_IO_INR_LANCE) },
 585                 { .i = IO_IRQ_NR(KN02CA_IO_INR_LANCE) } },
 586         { { .i = IO_IRQ_MASK(KN02CA_IO_INR_TC1) },
 587                 { .i = IO_IRQ_NR(KN02CA_IO_INR_TC1) } },
 588         { { .i = IO_IRQ_MASK(KN02CA_IO_INR_TC0) },
 589                 { .i = IO_IRQ_NR(KN02CA_IO_INR_TC0) } },
 590         { { .i = IO_IRQ_ALL },
 591                 { .p = asic_all_int } },
 592 };
 593
 594 static void __init dec_init_kn02ca(void)
 595 {
 596         /* IRQ routing. */
 597         memcpy(&dec_interrupt, &kn02ca_interrupt,
 598                 sizeof(kn02ca_interrupt));
 599
 600         /* CPU IRQ priorities. */
 601         memcpy(&cpu_mask_nr_tbl, &kn02ca_cpu_mask_nr_tbl,
 602                 sizeof(kn02ca_cpu_mask_nr_tbl));
 603
 604         /* I/O ASIC IRQ priorities. */
 605         memcpy(&asic_mask_nr_tbl, &kn02ca_asic_mask_nr_tbl,
 606                 sizeof(kn02ca_asic_mask_nr_tbl));
 607
 608         mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
 609         init_ioasic_irqs(IO_IRQ_BASE);
 610
 611 }                               /* dec_init_kn02ca */
 612
 613
 614 /*
 615  * Machine-specific initialisation for KN03, aka DS5000/240,
 616  * aka 3max+ and DS5900, aka BIGmax.  Also applies to KN05, aka
 617  * DS5000/260, aka 4max+ and DS5900/260.
 618  */
 619 static int kn03_interrupt[DEC_NR_INTS] __initdata = {
 620         [DEC_IRQ_CASCADE]       = DEC_CPU_IRQ_NR(KN03_CPU_INR_CASCADE),
 621         [DEC_IRQ_AB_RECV]       = -1,
 622         [DEC_IRQ_AB_XMIT]       = -1,
 623         [DEC_IRQ_DZ11]          = -1,
 624         [DEC_IRQ_ASC]           = IO_IRQ_NR(KN03_IO_INR_ASC),
 625         [DEC_IRQ_FLOPPY]        = -1,
 626         [DEC_IRQ_FPU]           = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
 627         [DEC_IRQ_HALT]          = DEC_CPU_IRQ_NR(KN03_CPU_INR_HALT),
 628         [DEC_IRQ_ISDN]          = -1,
 629         [DEC_IRQ_LANCE]         = IO_IRQ_NR(KN03_IO_INR_LANCE),
 630         [DEC_IRQ_BUS]           = DEC_CPU_IRQ_NR(KN03_CPU_INR_BUS),
 631         [DEC_IRQ_PSU]           = IO_IRQ_NR(KN03_IO_INR_PSU),
 632         [DEC_IRQ_RTC]           = DEC_CPU_IRQ_NR(KN03_CPU_INR_RTC),
 633         [DEC_IRQ_SCC0]          = IO_IRQ_NR(KN03_IO_INR_SCC0),
 634         [DEC_IRQ_SCC1]          = IO_IRQ_NR(KN03_IO_INR_SCC1),
 635         [DEC_IRQ_SII]           = -1,
 636         [DEC_IRQ_TC0]           = IO_IRQ_NR(KN03_IO_INR_TC0),
 637         [DEC_IRQ_TC1]           = IO_IRQ_NR(KN03_IO_INR_TC1),
 638         [DEC_IRQ_TC2]           = IO_IRQ_NR(KN03_IO_INR_TC2),
 639         [DEC_IRQ_TIMER]         = -1,
 640         [DEC_IRQ_VIDEO]         = -1,
 641         [DEC_IRQ_ASC_MERR]      = IO_IRQ_NR(IO_INR_ASC_MERR),
 642         [DEC_IRQ_ASC_ERR]       = IO_IRQ_NR(IO_INR_ASC_ERR),
 643         [DEC_IRQ_ASC_DMA]       = IO_IRQ_NR(IO_INR_ASC_DMA),
 644         [DEC_IRQ_FLOPPY_ERR]    = -1,
 645         [DEC_IRQ_ISDN_ERR]      = -1,
 646         [DEC_IRQ_ISDN_RXDMA]    = -1,
 647         [DEC_IRQ_ISDN_TXDMA]    = -1,
 648         [DEC_IRQ_LANCE_MERR]    = IO_IRQ_NR(IO_INR_LANCE_MERR),
 649         [DEC_IRQ_SCC0A_RXERR]   = IO_IRQ_NR(IO_INR_SCC0A_RXERR),
 650         [DEC_IRQ_SCC0A_RXDMA]   = IO_IRQ_NR(IO_INR_SCC0A_RXDMA),
 651         [DEC_IRQ_SCC0A_TXERR]   = IO_IRQ_NR(IO_INR_SCC0A_TXERR),
 652         [DEC_IRQ_SCC0A_TXDMA]   = IO_IRQ_NR(IO_INR_SCC0A_TXDMA),
 653         [DEC_IRQ_AB_RXERR]      = -1,
 654         [DEC_IRQ_AB_RXDMA]      = -1,
 655         [DEC_IRQ_AB_TXERR]      = -1,
 656         [DEC_IRQ_AB_TXDMA]      = -1,
 657         [DEC_IRQ_SCC1A_RXERR]   = IO_IRQ_NR(IO_INR_SCC1A_RXERR),
 658         [DEC_IRQ_SCC1A_RXDMA]   = IO_IRQ_NR(IO_INR_SCC1A_RXDMA),
 659         [DEC_IRQ_SCC1A_TXERR]   = IO_IRQ_NR(IO_INR_SCC1A_TXERR),
 660         [DEC_IRQ_SCC1A_TXDMA]   = IO_IRQ_NR(IO_INR_SCC1A_TXDMA),
 661 };
 662
 663 static int_ptr kn03_cpu_mask_nr_tbl[][2] __initdata = {
 664         { { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_BUS) },
 665                 { .i = DEC_CPU_IRQ_NR(KN03_CPU_INR_BUS) } },
 666         { { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_RTC) },
 667                 { .i = DEC_CPU_IRQ_NR(KN03_CPU_INR_RTC) } },
 668         { { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_CASCADE) },
 669                 { .p = kn03_io_int } },
 670         { { .i = DEC_CPU_IRQ_ALL },
 671                 { .p = cpu_all_int } },
 672 };
 673
 674 static int_ptr kn03_asic_mask_nr_tbl[][2] __initdata = {
 675         { { .i = IO_IRQ_DMA },
 676                 { .p = asic_dma_int } },
 677         { { .i = IO_IRQ_MASK(KN03_IO_INR_SCC0) },
 678                 { .i = IO_IRQ_NR(KN03_IO_INR_SCC0) } },
 679         { { .i = IO_IRQ_MASK(KN03_IO_INR_SCC1) },
 680                 { .i = IO_IRQ_NR(KN03_IO_INR_SCC1) } },
 681         { { .i = IO_IRQ_MASK(KN03_IO_INR_ASC) },
 682                 { .i = IO_IRQ_NR(KN03_IO_INR_ASC) } },
 683         { { .i = IO_IRQ_MASK(KN03_IO_INR_LANCE) },
 684                 { .i = IO_IRQ_NR(KN03_IO_INR_LANCE) } },
 685         { { .i = IO_IRQ_MASK(KN03_IO_INR_TC2) },
 686                 { .i = IO_IRQ_NR(KN03_IO_INR_TC2) } },
 687         { { .i = IO_IRQ_MASK(KN03_IO_INR_TC1) },
 688                 { .i = IO_IRQ_NR(KN03_IO_INR_TC1) } },
 689         { { .i = IO_IRQ_MASK(KN03_IO_INR_TC0) },
 690                 { .i = IO_IRQ_NR(KN03_IO_INR_TC0) } },
 691         { { .i = IO_IRQ_ALL },
 692                 { .p = asic_all_int } },
 693 };
 694
 695 static void __init dec_init_kn03(void)
 696 {
 697         /* IRQ routing. */
 698         memcpy(&dec_interrupt, &kn03_interrupt,
 699                 sizeof(kn03_interrupt));
 700
 701         /* CPU IRQ priorities. */
 702         memcpy(&cpu_mask_nr_tbl, &kn03_cpu_mask_nr_tbl,
 703                 sizeof(kn03_cpu_mask_nr_tbl));
 704
 705         /* I/O ASIC IRQ priorities. */
 706         memcpy(&asic_mask_nr_tbl, &kn03_asic_mask_nr_tbl,
 707                 sizeof(kn03_asic_mask_nr_tbl));
 708
 709         mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
 710         init_ioasic_irqs(IO_IRQ_BASE);
 711
 712 }                               /* dec_init_kn03 */
 713
 714
 715 void __init arch_init_irq(void)
 716 {
 717         switch (mips_machtype) {
 718         case MACH_DS23100:      /* DS2100/DS3100 Pmin/Pmax */
 719                 dec_init_kn01();
 720                 break;
 721         case MACH_DS5100:       /* DS5100 MIPSmate */
 722                 dec_init_kn230();
 723                 break;
 724         case MACH_DS5000_200:   /* DS5000/200 3max */
 725                 dec_init_kn02();
 726                 break;
 727         case MACH_DS5000_1XX:   /* DS5000/1xx 3min */
 728                 dec_init_kn02ba();
 729                 break;
 730         case MACH_DS5000_2X0:   /* DS5000/240 3max+ */
 731         case MACH_DS5900:       /* DS5900 bigmax */
 732                 dec_init_kn03();
 733                 break;
 734         case MACH_DS5000_XX:    /* Personal DS5000/xx */
 735                 dec_init_kn02ca();
 736                 break;
 737         case MACH_DS5800:       /* DS5800 Isis */
 738                 panic("Don't know how to set this up!");
 739                 break;
 740         case MACH_DS5400:       /* DS5400 MIPSfair */
 741                 panic("Don't know how to set this up!");
 742                 break;
 743         case MACH_DS5500:       /* DS5500 MIPSfair-2 */
 744                 panic("Don't know how to set this up!");
 745                 break;
 746         }
 747         set_except_vector(0, decstation_handle_int);
 748
 749         /* Free the FPU interrupt if the exception is present. */
 750         if (!cpu_has_nofpuex) {
 751                 cpu_fpu_mask = 0;
 752                 dec_interrupt[DEC_IRQ_FPU] = -1;
 753         }
 754
 755         /* Register board interrupts: FPU and cascade. */
 756         if (dec_interrupt[DEC_IRQ_FPU] >= 0)
 757                 setup_irq(dec_interrupt[DEC_IRQ_FPU], &fpuirq);
 758         if (dec_interrupt[DEC_IRQ_CASCADE] >= 0)
 759                 setup_irq(dec_interrupt[DEC_IRQ_CASCADE], &ioirq);
 760
 761         /* Register the bus error interrupt. */
 762         if (dec_interrupt[DEC_IRQ_BUS] >= 0 && busirq.handler)
 763                 setup_irq(dec_interrupt[DEC_IRQ_BUS], &busirq);
 764
 765         /* Register the HALT interrupt. */
 766         if (dec_interrupt[DEC_IRQ_HALT] >= 0)
 767                 setup_irq(dec_interrupt[DEC_IRQ_HALT], &haltirq);
 768 }