2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
7 * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org)
8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
10 #include <linux/config.h>
11 #include <linux/init.h>
12 #include <linux/kernel.h>
13 #include <linux/sched.h>
15 #include <linux/bitops.h>
17 #include <asm/bcache.h>
18 #include <asm/bootinfo.h>
19 #include <asm/cacheops.h>
21 #include <asm/cpu-features.h>
24 #include <asm/pgtable.h>
25 #include <asm/r4kcache.h>
26 #include <asm/system.h>
27 #include <asm/mmu_context.h>
30 static unsigned long icache_size, dcache_size, scache_size;
33 * Dummy cache handling routines for machines without boardcaches
35 static void no_sc_noop(void) {}
37 static struct bcache_ops no_sc_ops = {
38 .bc_enable = (void *)no_sc_noop,
39 .bc_disable = (void *)no_sc_noop,
40 .bc_wback_inv = (void *)no_sc_noop,
41 .bc_inv = (void *)no_sc_noop
44 struct bcache_ops *bcops = &no_sc_ops;
46 #define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x2010)
47 #define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x2020)
49 #define R4600_HIT_CACHEOP_WAR_IMPL \
51 if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) \
52 *(volatile unsigned long *)CKSEG1; \
53 if (R4600_V1_HIT_CACHEOP_WAR) \
54 __asm__ __volatile__("nop;nop;nop;nop"); \
57 static void (*r4k_blast_dcache_page)(unsigned long addr);
59 static inline void r4k_blast_dcache_page_dc32(unsigned long addr)
61 R4600_HIT_CACHEOP_WAR_IMPL;
62 blast_dcache32_page(addr);
65 static inline void r4k_blast_dcache_page_setup(void)
67 unsigned long dc_lsize = cpu_dcache_line_size();
70 r4k_blast_dcache_page = blast_dcache16_page;
71 else if (dc_lsize == 32)
72 r4k_blast_dcache_page = r4k_blast_dcache_page_dc32;
75 static void (* r4k_blast_dcache_page_indexed)(unsigned long addr);
77 static inline void r4k_blast_dcache_page_indexed_setup(void)
79 unsigned long dc_lsize = cpu_dcache_line_size();
82 r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed;
83 else if (dc_lsize == 32)
84 r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed;
87 static void (* r4k_blast_dcache)(void);
89 static inline void r4k_blast_dcache_setup(void)
91 unsigned long dc_lsize = cpu_dcache_line_size();
94 r4k_blast_dcache = blast_dcache16;
95 else if (dc_lsize == 32)
96 r4k_blast_dcache = blast_dcache32;
99 /* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */
100 #define JUMP_TO_ALIGN(order) \
101 __asm__ __volatile__( \
103 ".align\t" #order "\n\t" \
106 #define CACHE32_UNROLL32_ALIGN JUMP_TO_ALIGN(10) /* 32 * 32 = 1024 */
107 #define CACHE32_UNROLL32_ALIGN2 JUMP_TO_ALIGN(11)
109 static inline void blast_r4600_v1_icache32(void)
113 local_irq_save(flags);
115 local_irq_restore(flags);
118 static inline void tx49_blast_icache32(void)
120 unsigned long start = INDEX_BASE;
121 unsigned long end = start + current_cpu_data.icache.waysize;
122 unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
123 unsigned long ws_end = current_cpu_data.icache.ways <<
124 current_cpu_data.icache.waybit;
125 unsigned long ws, addr;
127 CACHE32_UNROLL32_ALIGN2;
128 /* I'm in even chunk. blast odd chunks */
129 for (ws = 0; ws < ws_end; ws += ws_inc)
130 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
131 cache32_unroll32(addr|ws,Index_Invalidate_I);
132 CACHE32_UNROLL32_ALIGN;
133 /* I'm in odd chunk. blast even chunks */
134 for (ws = 0; ws < ws_end; ws += ws_inc)
135 for (addr = start; addr < end; addr += 0x400 * 2)
136 cache32_unroll32(addr|ws,Index_Invalidate_I);
139 static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page)
143 local_irq_save(flags);
144 blast_icache32_page_indexed(page);
145 local_irq_restore(flags);
148 static inline void tx49_blast_icache32_page_indexed(unsigned long page)
150 unsigned long start = page;
151 unsigned long end = start + PAGE_SIZE;
152 unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
153 unsigned long ws_end = current_cpu_data.icache.ways <<
154 current_cpu_data.icache.waybit;
155 unsigned long ws, addr;
157 CACHE32_UNROLL32_ALIGN2;
158 /* I'm in even chunk. blast odd chunks */
159 for (ws = 0; ws < ws_end; ws += ws_inc)
160 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
161 cache32_unroll32(addr|ws,Index_Invalidate_I);
162 CACHE32_UNROLL32_ALIGN;
163 /* I'm in odd chunk. blast even chunks */
164 for (ws = 0; ws < ws_end; ws += ws_inc)
165 for (addr = start; addr < end; addr += 0x400 * 2)
166 cache32_unroll32(addr|ws,Index_Invalidate_I);
169 static void (* r4k_blast_icache_page)(unsigned long addr);
171 static inline void r4k_blast_icache_page_setup(void)
173 unsigned long ic_lsize = cpu_icache_line_size();
176 r4k_blast_icache_page = blast_icache16_page;
177 else if (ic_lsize == 32)
178 r4k_blast_icache_page = blast_icache32_page;
179 else if (ic_lsize == 64)
180 r4k_blast_icache_page = blast_icache64_page;
184 static void (* r4k_blast_icache_page_indexed)(unsigned long addr);
186 static inline void r4k_blast_icache_page_indexed_setup(void)
188 unsigned long ic_lsize = cpu_icache_line_size();
191 r4k_blast_icache_page_indexed = blast_icache16_page_indexed;
192 else if (ic_lsize == 32) {
193 if (TX49XX_ICACHE_INDEX_INV_WAR)
194 r4k_blast_icache_page_indexed =
195 tx49_blast_icache32_page_indexed;
196 else if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
197 r4k_blast_icache_page_indexed =
198 blast_icache32_r4600_v1_page_indexed;
200 r4k_blast_icache_page_indexed =
201 blast_icache32_page_indexed;
202 } else if (ic_lsize == 64)
203 r4k_blast_icache_page_indexed = blast_icache64_page_indexed;
206 static void (* r4k_blast_icache)(void);
208 static inline void r4k_blast_icache_setup(void)
210 unsigned long ic_lsize = cpu_icache_line_size();
213 r4k_blast_icache = blast_icache16;
214 else if (ic_lsize == 32) {
215 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
216 r4k_blast_icache = blast_r4600_v1_icache32;
217 else if (TX49XX_ICACHE_INDEX_INV_WAR)
218 r4k_blast_icache = tx49_blast_icache32;
220 r4k_blast_icache = blast_icache32;
221 } else if (ic_lsize == 64)
222 r4k_blast_icache = blast_icache64;
225 static void (* r4k_blast_scache_page)(unsigned long addr);
227 static inline void r4k_blast_scache_page_setup(void)
229 unsigned long sc_lsize = cpu_scache_line_size();
232 r4k_blast_scache_page = blast_scache16_page;
233 else if (sc_lsize == 32)
234 r4k_blast_scache_page = blast_scache32_page;
235 else if (sc_lsize == 64)
236 r4k_blast_scache_page = blast_scache64_page;
237 else if (sc_lsize == 128)
238 r4k_blast_scache_page = blast_scache128_page;
241 static void (* r4k_blast_scache)(void);
243 static inline void r4k_blast_scache_setup(void)
245 unsigned long sc_lsize = cpu_scache_line_size();
248 r4k_blast_scache = blast_scache16;
249 else if (sc_lsize == 32)
250 r4k_blast_scache = blast_scache32;
251 else if (sc_lsize == 64)
252 r4k_blast_scache = blast_scache64;
253 else if (sc_lsize == 128)
254 r4k_blast_scache = blast_scache128;
258 * This is former mm's flush_cache_all() which really should be
259 * flush_cache_vunmap these days ...
261 static inline void local_r4k_flush_cache_all(void * args)
267 static void r4k_flush_cache_all(void)
269 if (!cpu_has_dc_aliases)
272 on_each_cpu(local_r4k_flush_cache_all, NULL, 1, 1);
275 static inline void local_r4k___flush_cache_all(void * args)
280 switch (current_cpu_data.cputype) {
291 static void r4k___flush_cache_all(void)
293 on_each_cpu(local_r4k___flush_cache_all, NULL, 1, 1);
296 static inline void local_r4k_flush_cache_range(void * args)
298 struct vm_area_struct *vma = args;
301 if (!(cpu_context(smp_processor_id(), vma->vm_mm)))
304 exec = vma->vm_flags & VM_EXEC;
305 if (cpu_has_dc_aliases || exec)
311 static void r4k_flush_cache_range(struct vm_area_struct *vma,
312 unsigned long start, unsigned long end)
314 on_each_cpu(local_r4k_flush_cache_range, vma, 1, 1);
317 static inline void local_r4k_flush_cache_mm(void * args)
319 struct mm_struct *mm = args;
321 if (!cpu_has_dc_aliases)
324 if (!cpu_context(smp_processor_id(), mm))
331 * Kludge alert. For obscure reasons R4000SC and R4400SC go nuts if we
332 * only flush the primary caches but R10000 and R12000 behave sane ...
334 if (current_cpu_data.cputype == CPU_R4000SC ||
335 current_cpu_data.cputype == CPU_R4000MC ||
336 current_cpu_data.cputype == CPU_R4400SC ||
337 current_cpu_data.cputype == CPU_R4400MC)
341 static void r4k_flush_cache_mm(struct mm_struct *mm)
343 on_each_cpu(local_r4k_flush_cache_mm, mm, 1, 1);
346 struct flush_cache_page_args {
347 struct vm_area_struct *vma;
351 static inline void local_r4k_flush_cache_page(void *args)
353 struct flush_cache_page_args *fcp_args = args;
354 struct vm_area_struct *vma = fcp_args->vma;
355 unsigned long page = fcp_args->page;
356 int exec = vma->vm_flags & VM_EXEC;
357 struct mm_struct *mm = vma->vm_mm;
363 * If ownes no valid ASID yet, cannot possibly have gotten
364 * this page into the cache.
366 if (cpu_context(smp_processor_id(), mm) == 0)
370 pgdp = pgd_offset(mm, page);
371 pmdp = pmd_offset(pgdp, page);
372 ptep = pte_offset(pmdp, page);
375 * If the page isn't marked valid, the page cannot possibly be
378 if (!(pte_val(*ptep) & _PAGE_PRESENT))
382 * Doing flushes for another ASID than the current one is
383 * too difficult since stupid R4k caches do a TLB translation
384 * for every cache flush operation. So we do indexed flushes
385 * in that case, which doesn't overly flush the cache too much.
387 if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) {
388 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc))
389 r4k_blast_dcache_page(page);
391 r4k_blast_icache_page(page);
397 * Do indexed flush, too much work to get the (possible) TLB refills
400 page = INDEX_BASE + (page & (dcache_size - 1));
401 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc))
402 r4k_blast_dcache_page_indexed(page);
404 if (cpu_has_vtag_icache) {
405 int cpu = smp_processor_id();
407 if (cpu_context(cpu, vma->vm_mm) != 0)
408 drop_mmu_context(vma->vm_mm, cpu);
410 r4k_blast_icache_page_indexed(page);
414 static void r4k_flush_cache_page(struct vm_area_struct *vma,
417 struct flush_cache_page_args args;
422 on_each_cpu(local_r4k_flush_cache_page, &args, 1, 1);
425 static inline void local_r4k_flush_data_cache_page(void * addr)
427 r4k_blast_dcache_page((unsigned long) addr);
430 static void r4k_flush_data_cache_page(unsigned long addr)
432 on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr, 1, 1);
435 struct flush_icache_range_args {
440 static inline void local_r4k_flush_icache_range(void *args)
442 struct flush_icache_range_args *fir_args = args;
443 unsigned long dc_lsize = current_cpu_data.dcache.linesz;
444 unsigned long ic_lsize = current_cpu_data.icache.linesz;
445 unsigned long start = fir_args->start;
446 unsigned long end = fir_args->end;
447 unsigned long addr, aend;
449 if (!cpu_has_ic_fills_f_dc) {
450 if (end - start > dcache_size)
453 addr = start & ~(dc_lsize - 1);
454 aend = (end - 1) & ~(dc_lsize - 1);
457 /* Hit_Writeback_Inv_D */
458 protected_writeback_dcache_line(addr);
466 if (end - start > icache_size)
469 addr = start & ~(ic_lsize - 1);
470 aend = (end - 1) & ~(ic_lsize - 1);
472 /* Hit_Invalidate_I */
473 protected_flush_icache_line(addr);
481 static void r4k_flush_icache_range(unsigned long start, unsigned long end)
483 struct flush_icache_range_args args;
488 on_each_cpu(local_r4k_flush_icache_range, &args, 1, 1);
492 * Ok, this seriously sucks. We use them to flush a user page but don't
493 * know the virtual address, so we have to blast away the whole icache
494 * which is significantly more expensive than the real thing. Otoh we at
495 * least know the kernel address of the page so we can flush it
499 struct flush_icache_page_args {
500 struct vm_area_struct *vma;
504 static inline void local_r4k_flush_icache_page(void *args)
506 struct flush_icache_page_args *fip_args = args;
507 struct vm_area_struct *vma = fip_args->vma;
508 struct page *page = fip_args->page;
511 * Tricky ... Because we don't know the virtual address we've got the
512 * choice of either invalidating the entire primary and secondary
513 * caches or invalidating the secondary caches also. With the subset
514 * enforcment on R4000SC, R4400SC, R10000 and R12000 invalidating the
515 * secondary cache will result in any entries in the primary caches
516 * also getting invalidated which hopefully is a bit more economical.
518 if (cpu_has_subset_pcaches) {
519 unsigned long addr = (unsigned long) page_address(page);
521 r4k_blast_scache_page(addr);
522 ClearPageDcacheDirty(page);
527 if (!cpu_has_ic_fills_f_dc) {
528 unsigned long addr = (unsigned long) page_address(page);
529 r4k_blast_dcache_page(addr);
530 ClearPageDcacheDirty(page);
534 * We're not sure of the virtual address(es) involved here, so
535 * we have to flush the entire I-cache.
537 if (cpu_has_vtag_icache) {
538 int cpu = smp_processor_id();
540 if (cpu_context(cpu, vma->vm_mm) != 0)
541 drop_mmu_context(vma->vm_mm, cpu);
546 static void r4k_flush_icache_page(struct vm_area_struct *vma,
549 struct flush_icache_page_args args;
552 * If there's no context yet, or the page isn't executable, no I-cache
555 if (!(vma->vm_flags & VM_EXEC))
561 on_each_cpu(local_r4k_flush_icache_page, &args, 1, 1);
565 #ifdef CONFIG_DMA_NONCOHERENT
567 static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
569 unsigned long end, a;
571 /* Catch bad driver code */
574 if (cpu_has_subset_pcaches) {
575 unsigned long sc_lsize = current_cpu_data.scache.linesz;
577 if (size >= scache_size) {
582 a = addr & ~(sc_lsize - 1);
583 end = (addr + size - 1) & ~(sc_lsize - 1);
585 flush_scache_line(a); /* Hit_Writeback_Inv_SD */
594 * Either no secondary cache or the available caches don't have the
595 * subset property so we have to flush the primary caches
598 if (size >= dcache_size) {
601 unsigned long dc_lsize = current_cpu_data.dcache.linesz;
603 R4600_HIT_CACHEOP_WAR_IMPL;
604 a = addr & ~(dc_lsize - 1);
605 end = (addr + size - 1) & ~(dc_lsize - 1);
607 flush_dcache_line(a); /* Hit_Writeback_Inv_D */
614 bc_wback_inv(addr, size);
617 static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
619 unsigned long end, a;
621 /* Catch bad driver code */
624 if (cpu_has_subset_pcaches) {
625 unsigned long sc_lsize = current_cpu_data.scache.linesz;
627 if (size >= scache_size) {
632 a = addr & ~(sc_lsize - 1);
633 end = (addr + size - 1) & ~(sc_lsize - 1);
635 flush_scache_line(a); /* Hit_Writeback_Inv_SD */
643 if (size >= dcache_size) {
646 unsigned long dc_lsize = current_cpu_data.dcache.linesz;
648 R4600_HIT_CACHEOP_WAR_IMPL;
649 a = addr & ~(dc_lsize - 1);
650 end = (addr + size - 1) & ~(dc_lsize - 1);
652 flush_dcache_line(a); /* Hit_Writeback_Inv_D */
661 #endif /* CONFIG_DMA_NONCOHERENT */
664 * While we're protected against bad userland addresses we don't care
665 * very much about what happens in that case. Usually a segmentation
666 * fault will dump the process later on anyway ...
668 static void local_r4k_flush_cache_sigtramp(void * arg)
670 unsigned long ic_lsize = current_cpu_data.icache.linesz;
671 unsigned long dc_lsize = current_cpu_data.dcache.linesz;
672 unsigned long addr = (unsigned long) arg;
674 R4600_HIT_CACHEOP_WAR_IMPL;
675 protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
676 protected_flush_icache_line(addr & ~(ic_lsize - 1));
677 if (MIPS4K_ICACHE_REFILL_WAR) {
678 __asm__ __volatile__ (
693 : "i" (Hit_Invalidate_I));
695 if (MIPS_CACHE_SYNC_WAR)
696 __asm__ __volatile__ ("sync");
699 static void r4k_flush_cache_sigtramp(unsigned long addr)
701 on_each_cpu(local_r4k_flush_cache_sigtramp, (void *) addr, 1, 1);
704 static void r4k_flush_icache_all(void)
706 if (cpu_has_vtag_icache)
710 static inline void rm7k_erratum31(void)
712 const unsigned long ic_lsize = 32;
715 /* RM7000 erratum #31. The icache is screwed at startup. */
719 for (addr = INDEX_BASE; addr <= INDEX_BASE + 4096; addr += ic_lsize) {
720 __asm__ __volatile__ (
723 "cache\t%1, 0(%0)\n\t"
724 "cache\t%1, 0x1000(%0)\n\t"
725 "cache\t%1, 0x2000(%0)\n\t"
726 "cache\t%1, 0x3000(%0)\n\t"
727 "cache\t%2, 0(%0)\n\t"
728 "cache\t%2, 0x1000(%0)\n\t"
729 "cache\t%2, 0x2000(%0)\n\t"
730 "cache\t%2, 0x3000(%0)\n\t"
731 "cache\t%1, 0(%0)\n\t"
732 "cache\t%1, 0x1000(%0)\n\t"
733 "cache\t%1, 0x2000(%0)\n\t"
734 "cache\t%1, 0x3000(%0)\n\t"
738 : "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill));
742 static char *way_string[] = { NULL, "direct mapped", "2-way", "3-way", "4-way",
743 "5-way", "6-way", "7-way", "8-way"
746 static void __init probe_pcache(void)
748 struct cpuinfo_mips *c = ¤t_cpu_data;
749 unsigned int config = read_c0_config();
750 unsigned int prid = read_c0_prid();
751 unsigned long config1;
754 switch (c->cputype) {
755 case CPU_R4600: /* QED style two way caches? */
759 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
760 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
762 c->icache.waybit = ffs(icache_size/2) - 1;
764 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
765 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
767 c->dcache.waybit= ffs(dcache_size/2) - 1;
769 c->options |= MIPS_CPU_CACHE_CDEX_P;
774 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
775 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
779 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
780 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
782 c->dcache.waybit = 0;
784 c->options |= MIPS_CPU_CACHE_CDEX_P;
788 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
789 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
793 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
794 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
796 c->dcache.waybit = 0;
798 c->options |= MIPS_CPU_CACHE_CDEX_P;
808 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
809 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
811 c->icache.waybit = 0; /* doesn't matter */
813 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
814 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
816 c->dcache.waybit = 0; /* does not matter */
818 c->options |= MIPS_CPU_CACHE_CDEX_P;
823 icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29));
824 c->icache.linesz = 64;
826 c->icache.waybit = 0;
828 dcache_size = 1 << (12 + ((config & R10K_CONF_DC) >> 26));
829 c->dcache.linesz = 32;
831 c->dcache.waybit = 0;
833 c->options |= MIPS_CPU_PREFETCH;
837 write_c0_config(config & ~CONF_EB);
839 /* Workaround for cache instruction bug of VR4131 */
840 if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U ||
841 c->processor_id == 0x0c82U) {
842 config &= ~0x00000030U;
843 config |= 0x00410000U;
844 write_c0_config(config);
846 icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
847 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
849 c->icache.waybit = ffs(icache_size/2) - 1;
851 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
852 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
854 c->dcache.waybit = ffs(dcache_size/2) - 1;
856 c->options |= MIPS_CPU_CACHE_CDEX_P;
865 icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
866 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
868 c->icache.waybit = 0; /* doesn't matter */
870 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
871 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
873 c->dcache.waybit = 0; /* does not matter */
875 c->options |= MIPS_CPU_CACHE_CDEX_P;
882 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
883 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
885 c->icache.waybit = ffs(icache_size / c->icache.ways) - 1;
887 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
888 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
890 c->dcache.waybit = ffs(dcache_size / c->dcache.ways) - 1;
892 #if !defined(CONFIG_SMP) || !defined(RM9000_CDEX_SMP_WAR)
893 c->options |= MIPS_CPU_CACHE_CDEX_P;
895 c->options |= MIPS_CPU_PREFETCH;
899 if (!(config & MIPS_CONF_M))
900 panic("Don't know how to probe P-caches on this cpu.");
903 * So we seem to be a MIPS32 or MIPS64 CPU
904 * So let's probe the I-cache ...
906 config1 = read_c0_config1();
908 if ((lsize = ((config1 >> 19) & 7)))
909 c->icache.linesz = 2 << lsize;
911 c->icache.linesz = lsize;
912 c->icache.sets = 64 << ((config1 >> 22) & 7);
913 c->icache.ways = 1 + ((config1 >> 16) & 7);
915 icache_size = c->icache.sets *
918 c->icache.waybit = ffs(icache_size/c->icache.ways) - 1;
920 if (config & 0x8) /* VI bit */
921 c->icache.flags |= MIPS_CACHE_VTAG;
924 * Now probe the MIPS32 / MIPS64 data cache.
928 if ((lsize = ((config1 >> 10) & 7)))
929 c->dcache.linesz = 2 << lsize;
931 c->dcache.linesz= lsize;
932 c->dcache.sets = 64 << ((config1 >> 13) & 7);
933 c->dcache.ways = 1 + ((config1 >> 7) & 7);
935 dcache_size = c->dcache.sets *
938 c->dcache.waybit = ffs(dcache_size/c->dcache.ways) - 1;
940 c->options |= MIPS_CPU_PREFETCH;
945 * Processor configuration sanity check for the R4000SC erratum
946 * #5. With page sizes larger than 32kB there is no possibility
947 * to get a VCE exception anymore so we don't care about this
948 * misconfiguration. The case is rather theoretical anyway;
949 * presumably no vendor is shipping his hardware in the "bad"
952 if ((prid & 0xff00) == PRID_IMP_R4000 && (prid & 0xff) < 0x40 &&
953 !(config & CONF_SC) && c->icache.linesz != 16 &&
955 panic("Improper R4000SC processor configuration detected");
957 /* compute a couple of other cache variables */
958 c->icache.waysize = icache_size / c->icache.ways;
959 c->dcache.waysize = dcache_size / c->dcache.ways;
961 c->icache.sets = icache_size / (c->icache.linesz * c->icache.ways);
962 c->dcache.sets = dcache_size / (c->dcache.linesz * c->dcache.ways);
965 * R10000 and R12000 P-caches are odd in a positive way. They're 32kB
966 * 2-way virtually indexed so normally would suffer from aliases. So
967 * normally they'd suffer from aliases but magic in the hardware deals
968 * with that for us so we don't need to take care ourselves.
970 if (c->cputype != CPU_R10000 && c->cputype != CPU_R12000)
971 if (c->dcache.waysize > PAGE_SIZE)
972 c->dcache.flags |= MIPS_CACHE_ALIASES;
974 switch (c->cputype) {
977 * Some older 20Kc chips doesn't have the 'VI' bit in
978 * the config register.
980 c->icache.flags |= MIPS_CACHE_VTAG;
984 c->icache.flags |= MIPS_CACHE_IC_F_DC;
988 printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",
990 cpu_has_vtag_icache ? "virtually tagged" : "physically tagged",
991 way_string[c->icache.ways], c->icache.linesz);
993 printk("Primary data cache %ldkB, %s, linesize %d bytes.\n",
994 dcache_size >> 10, way_string[c->dcache.ways], c->dcache.linesz);
998 * If you even _breathe_ on this function, look at the gcc output and make sure
999 * it does not pop things on and off the stack for the cache sizing loop that
1000 * executes in KSEG1 space or else you will crash and burn badly. You have
1003 static int __init probe_scache(void)
1005 extern unsigned long stext;
1006 unsigned long flags, addr, begin, end, pow2;
1007 unsigned int config = read_c0_config();
1008 struct cpuinfo_mips *c = ¤t_cpu_data;
1011 if (config & CONF_SC)
1014 begin = (unsigned long) &stext;
1015 begin &= ~((4 * 1024 * 1024) - 1);
1016 end = begin + (4 * 1024 * 1024);
1019 * This is such a bitch, you'd think they would make it easy to do
1020 * this. Away you daemons of stupidity!
1022 local_irq_save(flags);
1024 /* Fill each size-multiple cache line with a valid tag. */
1026 for (addr = begin; addr < end; addr = (begin + pow2)) {
1027 unsigned long *p = (unsigned long *) addr;
1028 __asm__ __volatile__("nop" : : "r" (*p)); /* whee... */
1032 /* Load first line with zero (therefore invalid) tag. */
1035 __asm__ __volatile__("nop; nop; nop; nop;"); /* avoid the hazard */
1036 cache_op(Index_Store_Tag_I, begin);
1037 cache_op(Index_Store_Tag_D, begin);
1038 cache_op(Index_Store_Tag_SD, begin);
1040 /* Now search for the wrap around point. */
1041 pow2 = (128 * 1024);
1043 for (addr = begin + (128 * 1024); addr < end; addr = begin + pow2) {
1044 cache_op(Index_Load_Tag_SD, addr);
1045 __asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */
1046 if (!read_c0_taglo())
1050 local_irq_restore(flags);
1054 c->scache.linesz = 16 << ((config & R4K_CONF_SB) >> 22);
1056 c->dcache.waybit = 0; /* does not matter */
1061 typedef int (*probe_func_t)(unsigned long);
1062 extern int r5k_sc_init(void);
1063 extern int rm7k_sc_init(void);
1065 static void __init setup_scache(void)
1067 struct cpuinfo_mips *c = ¤t_cpu_data;
1068 unsigned int config = read_c0_config();
1069 probe_func_t probe_scache_kseg1;
1073 * Do the probing thing on R4000SC and R4400SC processors. Other
1074 * processors don't have a S-cache that would be relevant to the
1075 * Linux memory managment.
1077 switch (c->cputype) {
1082 probe_scache_kseg1 = (probe_func_t) (CKSEG1ADDR(&probe_scache));
1083 sc_present = probe_scache_kseg1(config);
1085 c->options |= MIPS_CPU_CACHE_CDEX_S;
1090 scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16);
1091 c->scache.linesz = 64 << ((config >> 13) & 1);
1093 c->scache.waybit= 0;
1099 #ifdef CONFIG_R5000_CPU_SCACHE
1106 #ifdef CONFIG_RM7000_CPU_SCACHE
1118 if ((c->isa_level == MIPS_CPU_ISA_M32 ||
1119 c->isa_level == MIPS_CPU_ISA_M64) &&
1120 !(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
1121 panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
1123 /* compute a couple of other cache variables */
1124 c->scache.waysize = scache_size / c->scache.ways;
1126 c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
1128 printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1129 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1131 c->options |= MIPS_CPU_SUBSET_CACHES;
1134 static inline void coherency_setup(void)
1136 change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);
1139 * c0_status.cu=0 specifies that updates by the sc instruction use
1140 * the coherency mode specified by the TLB; 1 means cachable
1141 * coherent update on write will be used. Not all processors have
1142 * this bit and; some wire it to zero, others like Toshiba had the
1143 * silly idea of putting something else there ...
1145 switch (current_cpu_data.cputype) {
1152 clear_c0_config(CONF_CU);
1157 void __init ld_mmu_r4xx0(void)
1159 extern void build_clear_page(void);
1160 extern void build_copy_page(void);
1161 extern char except_vec2_generic;
1162 struct cpuinfo_mips *c = ¤t_cpu_data;
1164 /* Default cache error handler for R4000 and R5000 family */
1165 memcpy((void *)(CAC_BASE + 0x100), &except_vec2_generic, 0x80);
1166 memcpy((void *)(UNCAC_BASE + 0x100), &except_vec2_generic, 0x80);
1171 if (c->dcache.sets * c->dcache.ways > PAGE_SIZE)
1172 c->dcache.flags |= MIPS_CACHE_ALIASES;
1174 r4k_blast_dcache_page_setup();
1175 r4k_blast_dcache_page_indexed_setup();
1176 r4k_blast_dcache_setup();
1177 r4k_blast_icache_page_setup();
1178 r4k_blast_icache_page_indexed_setup();
1179 r4k_blast_icache_setup();
1180 r4k_blast_scache_page_setup();
1181 r4k_blast_scache_setup();
1184 * Some MIPS32 and MIPS64 processors have physically indexed caches.
1185 * This code supports virtually indexed processors and will be
1186 * unnecessarily inefficient on physically indexed processors.
1188 shm_align_mask = max_t( unsigned long,
1189 c->dcache.sets * c->dcache.linesz - 1,
1192 flush_cache_all = r4k_flush_cache_all;
1193 __flush_cache_all = r4k___flush_cache_all;
1194 flush_cache_mm = r4k_flush_cache_mm;
1195 flush_cache_page = r4k_flush_cache_page;
1196 flush_icache_page = r4k_flush_icache_page;
1197 flush_cache_range = r4k_flush_cache_range;
1199 flush_cache_sigtramp = r4k_flush_cache_sigtramp;
1200 flush_icache_all = r4k_flush_icache_all;
1201 flush_data_cache_page = r4k_flush_data_cache_page;
1202 flush_icache_range = r4k_flush_icache_range;
1204 #ifdef CONFIG_DMA_NONCOHERENT
1205 _dma_cache_wback_inv = r4k_dma_cache_wback_inv;
1206 _dma_cache_wback = r4k_dma_cache_wback_inv;
1207 _dma_cache_inv = r4k_dma_cache_inv;
1210 __flush_cache_all();