2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
7 * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org)
8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
10 #include <linux/config.h>
11 #include <linux/init.h>
12 #include <linux/kernel.h>
13 #include <linux/sched.h>
15 #include <linux/bitops.h>
17 #include <asm/bcache.h>
18 #include <asm/bootinfo.h>
19 #include <asm/cacheops.h>
21 #include <asm/cpu-features.h>
24 #include <asm/pgtable.h>
25 #include <asm/r4kcache.h>
26 #include <asm/system.h>
27 #include <asm/mmu_context.h>
30 static unsigned long icache_size, dcache_size, scache_size;
33 * Dummy cache handling routines for machines without boardcaches
35 static void no_sc_noop(void) {}
37 static struct bcache_ops no_sc_ops = {
38 .bc_enable = (void *)no_sc_noop,
39 .bc_disable = (void *)no_sc_noop,
40 .bc_wback_inv = (void *)no_sc_noop,
41 .bc_inv = (void *)no_sc_noop
44 struct bcache_ops *bcops = &no_sc_ops;
46 #define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x2010)
47 #define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x2020)
49 #define R4600_HIT_CACHEOP_WAR_IMPL \
51 if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) \
52 *(volatile unsigned long *)KSEG1; \
53 if (R4600_V1_HIT_CACHEOP_WAR) \
54 __asm__ __volatile__("nop;nop;nop;nop"); \
57 static void (*r4k_blast_dcache_page)(unsigned long addr);
59 static inline void r4k_blast_dcache_page_dc32(unsigned long addr)
61 R4600_HIT_CACHEOP_WAR_IMPL;
62 blast_dcache32_page(addr);
65 static inline void r4k_blast_dcache_page_setup(void)
67 unsigned long dc_lsize = cpu_dcache_line_size();
70 r4k_blast_dcache_page = blast_dcache16_page;
71 else if (dc_lsize == 32)
72 r4k_blast_dcache_page = r4k_blast_dcache_page_dc32;
75 static void (* r4k_blast_dcache_page_indexed)(unsigned long addr);
77 static inline void r4k_blast_dcache_page_indexed_setup(void)
79 unsigned long dc_lsize = cpu_dcache_line_size();
82 r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed;
83 else if (dc_lsize == 32)
84 r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed;
87 static void (* r4k_blast_dcache)(void);
89 static void r4k_blast_dcache_setup(void)
91 unsigned long dc_lsize = cpu_dcache_line_size();
94 r4k_blast_dcache = blast_dcache16;
95 else if (dc_lsize == 32)
96 r4k_blast_dcache = blast_dcache32;
99 /* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */
100 #define JUMP_TO_ALIGN(order) \
101 __asm__ __volatile__( \
103 ".align\t" #order "\n\t" \
106 #define CACHE32_UNROLL32_ALIGN JUMP_TO_ALIGN(10) /* 32 * 32 = 1024 */
107 #define CACHE32_UNROLL32_ALIGN2 JUMP_TO_ALIGN(11)
109 static inline void blast_r4600_v1_icache32(void)
113 local_irq_save(flags);
115 local_irq_restore(flags);
118 static inline void tx49_blast_icache32(void)
120 unsigned long start = INDEX_BASE;
121 unsigned long end = start + current_cpu_data.icache.waysize;
122 unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
123 unsigned long ws_end = current_cpu_data.icache.ways <<
124 current_cpu_data.icache.waybit;
125 unsigned long ws, addr;
127 CACHE32_UNROLL32_ALIGN2;
128 /* I'm in even chunk. blast odd chunks */
129 for (ws = 0; ws < ws_end; ws += ws_inc)
130 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
131 cache32_unroll32(addr|ws,Index_Invalidate_I);
132 CACHE32_UNROLL32_ALIGN;
133 /* I'm in odd chunk. blast even chunks */
134 for (ws = 0; ws < ws_end; ws += ws_inc)
135 for (addr = start; addr < end; addr += 0x400 * 2)
136 cache32_unroll32(addr|ws,Index_Invalidate_I);
139 static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page)
143 local_irq_save(flags);
144 blast_icache32_page_indexed(page);
145 local_irq_restore(flags);
148 static inline void tx49_blast_icache32_page_indexed(unsigned long page)
150 unsigned long start = page;
151 unsigned long end = start + PAGE_SIZE;
152 unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
153 unsigned long ws_end = current_cpu_data.icache.ways <<
154 current_cpu_data.icache.waybit;
155 unsigned long ws, addr;
157 CACHE32_UNROLL32_ALIGN2;
158 /* I'm in even chunk. blast odd chunks */
159 for (ws = 0; ws < ws_end; ws += ws_inc)
160 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
161 cache32_unroll32(addr|ws,Index_Invalidate_I);
162 CACHE32_UNROLL32_ALIGN;
163 /* I'm in odd chunk. blast even chunks */
164 for (ws = 0; ws < ws_end; ws += ws_inc)
165 for (addr = start; addr < end; addr += 0x400 * 2)
166 cache32_unroll32(addr|ws,Index_Invalidate_I);
169 static void (* r4k_blast_icache_page)(unsigned long addr);
171 static inline void r4k_blast_icache_page_setup(void)
173 unsigned long ic_lsize = cpu_icache_line_size();
176 r4k_blast_icache_page = blast_icache16_page;
177 else if (ic_lsize == 32)
178 r4k_blast_icache_page = blast_icache32_page;
179 else if (ic_lsize == 64)
180 r4k_blast_icache_page = blast_icache64_page;
184 static void (* r4k_blast_icache_page_indexed)(unsigned long addr);
186 static inline void r4k_blast_icache_page_indexed_setup(void)
188 unsigned long ic_lsize = cpu_icache_line_size();
191 r4k_blast_icache_page_indexed = blast_icache16_page_indexed;
192 else if (ic_lsize == 32) {
193 if (TX49XX_ICACHE_INDEX_INV_WAR)
194 r4k_blast_icache_page_indexed =
195 tx49_blast_icache32_page_indexed;
196 else if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
197 r4k_blast_icache_page_indexed =
198 blast_icache32_r4600_v1_page_indexed;
200 r4k_blast_icache_page_indexed =
201 blast_icache32_page_indexed;
202 } else if (ic_lsize == 64)
203 r4k_blast_icache_page_indexed = blast_icache64_page_indexed;
206 static void (* r4k_blast_icache)(void);
208 static inline void r4k_blast_icache_setup(void)
210 unsigned long ic_lsize = cpu_icache_line_size();
213 r4k_blast_icache = blast_icache16;
214 else if (ic_lsize == 32) {
215 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
216 r4k_blast_icache = blast_r4600_v1_icache32;
217 else if (TX49XX_ICACHE_INDEX_INV_WAR)
218 r4k_blast_icache = tx49_blast_icache32;
220 r4k_blast_icache = blast_icache32;
221 } else if (ic_lsize == 64)
222 r4k_blast_icache = blast_icache64;
225 static void (* r4k_blast_scache_page)(unsigned long addr);
227 static inline void r4k_blast_scache_page_setup(void)
229 unsigned long sc_lsize = cpu_scache_line_size();
232 r4k_blast_scache_page = blast_scache16_page;
233 else if (sc_lsize == 32)
234 r4k_blast_scache_page = blast_scache32_page;
235 else if (sc_lsize == 64)
236 r4k_blast_scache_page = blast_scache64_page;
237 else if (sc_lsize == 128)
238 r4k_blast_scache_page = blast_scache128_page;
241 static void (* r4k_blast_scache)(void);
243 static inline void r4k_blast_scache_setup(void)
245 unsigned long sc_lsize = cpu_scache_line_size();
248 r4k_blast_scache = blast_scache16;
249 else if (sc_lsize == 32)
250 r4k_blast_scache = blast_scache32;
251 else if (sc_lsize == 64)
252 r4k_blast_scache = blast_scache64;
253 else if (sc_lsize == 128)
254 r4k_blast_scache = blast_scache128;
257 static void r4k_flush_cache_all(void)
259 if (!cpu_has_dc_aliases)
266 static void r4k___flush_cache_all(void)
271 switch (current_cpu_data.cputype) {
282 static void r4k_flush_cache_range(struct vm_area_struct *vma,
283 unsigned long start, unsigned long end)
287 if (!(cpu_context(smp_processor_id(), vma->vm_mm)))
290 exec = vma->vm_flags & VM_EXEC;
291 if (cpu_has_dc_aliases || exec)
297 static void r4k_flush_cache_mm(struct mm_struct *mm)
299 if (!cpu_has_dc_aliases)
302 if (!cpu_context(smp_processor_id(), mm))
309 * Kludge alert. For obscure reasons R4000SC and R4400SC go nuts if we
310 * only flush the primary caches but R10000 and R12000 behave sane ...
312 if (current_cpu_data.cputype == CPU_R4000SC ||
313 current_cpu_data.cputype == CPU_R4000MC ||
314 current_cpu_data.cputype == CPU_R4400SC ||
315 current_cpu_data.cputype == CPU_R4400MC)
319 static void r4k_flush_cache_page(struct vm_area_struct *vma,
322 int exec = vma->vm_flags & VM_EXEC;
323 struct mm_struct *mm = vma->vm_mm;
329 * If ownes no valid ASID yet, cannot possibly have gotten
330 * this page into the cache.
332 if (cpu_context(smp_processor_id(), mm) == 0)
336 pgdp = pgd_offset(mm, page);
337 pmdp = pmd_offset(pgdp, page);
338 ptep = pte_offset(pmdp, page);
341 * If the page isn't marked valid, the page cannot possibly be
344 if (!(pte_val(*ptep) & _PAGE_PRESENT))
348 * Doing flushes for another ASID than the current one is
349 * too difficult since stupid R4k caches do a TLB translation
350 * for every cache flush operation. So we do indexed flushes
351 * in that case, which doesn't overly flush the cache too much.
353 if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) {
354 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc))
355 r4k_blast_dcache_page(page);
357 r4k_blast_icache_page(page);
363 * Do indexed flush, too much work to get the (possible) TLB refills
366 page = INDEX_BASE + (page & (dcache_size - 1));
367 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc))
368 r4k_blast_dcache_page_indexed(page);
370 if (cpu_has_vtag_icache) {
371 int cpu = smp_processor_id();
373 if (cpu_context(cpu, vma->vm_mm) != 0)
374 drop_mmu_context(vma->vm_mm, cpu);
376 r4k_blast_icache_page_indexed(page);
380 static void r4k_flush_data_cache_page(unsigned long addr)
382 r4k_blast_dcache_page(addr);
385 static void r4k_flush_icache_range(unsigned long start, unsigned long end)
387 unsigned long dc_lsize = current_cpu_data.dcache.linesz;
388 unsigned long addr, aend;
390 if (!cpu_has_ic_fills_f_dc) {
391 if (end - start > dcache_size)
394 addr = start & ~(dc_lsize - 1);
395 aend = (end - 1) & ~(dc_lsize - 1);
398 /* Hit_Writeback_Inv_D */
399 protected_writeback_dcache_line(addr);
407 if (end - start > icache_size)
410 addr = start & ~(dc_lsize - 1);
411 aend = (end - 1) & ~(dc_lsize - 1);
413 /* Hit_Invalidate_I */
414 protected_flush_icache_line(addr);
423 * Ok, this seriously sucks. We use them to flush a user page but don't
424 * know the virtual address, so we have to blast away the whole icache
425 * which is significantly more expensive than the real thing. Otoh we at
426 * least know the kernel address of the page so we can flush it
429 static void r4k_flush_icache_page(struct vm_area_struct *vma, struct page *page)
432 * If there's no context yet, or the page isn't executable, no icache
435 if (!(vma->vm_flags & VM_EXEC))
439 * Tricky ... Because we don't know the virtual address we've got the
440 * choice of either invalidating the entire primary and secondary
441 * caches or invalidating the secondary caches also. With the subset
442 * enforcment on R4000SC, R4400SC, R10000 and R12000 invalidating the
443 * secondary cache will result in any entries in the primary caches
444 * also getting invalidated which hopefully is a bit more economical.
446 if (cpu_has_subset_pcaches) {
447 unsigned long addr = (unsigned long) page_address(page);
449 r4k_blast_scache_page(addr);
450 ClearPageDcacheDirty(page);
455 if (!cpu_has_ic_fills_f_dc) {
456 unsigned long addr = (unsigned long) page_address(page);
457 r4k_blast_dcache_page(addr);
458 ClearPageDcacheDirty(page);
462 * We're not sure of the virtual address(es) involved here, so
463 * we have to flush the entire I-cache.
465 if (cpu_has_vtag_icache) {
466 int cpu = smp_processor_id();
468 if (cpu_context(cpu, vma->vm_mm) != 0)
469 drop_mmu_context(vma->vm_mm, cpu);
474 #ifdef CONFIG_DMA_NONCOHERENT
476 static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
478 unsigned long end, a;
480 /* Catch bad driver code */
483 if (cpu_has_subset_pcaches) {
484 unsigned long sc_lsize = current_cpu_data.scache.linesz;
486 if (size >= scache_size) {
491 a = addr & ~(sc_lsize - 1);
492 end = (addr + size - 1) & ~(sc_lsize - 1);
494 flush_scache_line(a); /* Hit_Writeback_Inv_SD */
503 * Either no secondary cache or the available caches don't have the
504 * subset property so we have to flush the primary caches
507 if (size >= dcache_size) {
510 unsigned long dc_lsize = current_cpu_data.dcache.linesz;
512 R4600_HIT_CACHEOP_WAR_IMPL;
513 a = addr & ~(dc_lsize - 1);
514 end = (addr + size - 1) & ~(dc_lsize - 1);
516 flush_dcache_line(a); /* Hit_Writeback_Inv_D */
523 bc_wback_inv(addr, size);
526 static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
528 unsigned long end, a;
530 /* Catch bad driver code */
533 if (cpu_has_subset_pcaches) {
534 unsigned long sc_lsize = current_cpu_data.scache.linesz;
536 if (size >= scache_size) {
541 a = addr & ~(sc_lsize - 1);
542 end = (addr + size - 1) & ~(sc_lsize - 1);
544 flush_scache_line(a); /* Hit_Writeback_Inv_SD */
552 if (size >= dcache_size) {
555 unsigned long dc_lsize = current_cpu_data.dcache.linesz;
557 R4600_HIT_CACHEOP_WAR_IMPL;
558 a = addr & ~(dc_lsize - 1);
559 end = (addr + size - 1) & ~(dc_lsize - 1);
561 flush_dcache_line(a); /* Hit_Writeback_Inv_D */
570 #endif /* CONFIG_DMA_NONCOHERENT */
573 * While we're protected against bad userland addresses we don't care
574 * very much about what happens in that case. Usually a segmentation
575 * fault will dump the process later on anyway ...
577 static void r4k_flush_cache_sigtramp(unsigned long addr)
579 unsigned long ic_lsize = current_cpu_data.icache.linesz;
580 unsigned long dc_lsize = current_cpu_data.dcache.linesz;
582 R4600_HIT_CACHEOP_WAR_IMPL;
583 protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
584 protected_flush_icache_line(addr & ~(ic_lsize - 1));
585 if (MIPS4K_ICACHE_REFILL_WAR) {
586 __asm__ __volatile__ (
601 : "i" (Hit_Invalidate_I));
603 if (MIPS_CACHE_SYNC_WAR)
604 __asm__ __volatile__ ("sync");
607 static void r4k_flush_icache_all(void)
609 if (cpu_has_vtag_icache)
613 static inline void rm7k_erratum31(void)
615 const unsigned long ic_lsize = 32;
618 /* RM7000 erratum #31. The icache is screwed at startup. */
622 for (addr = INDEX_BASE; addr <= INDEX_BASE + 4096; addr += ic_lsize) {
623 __asm__ __volatile__ (
626 "cache\t%1, 0(%0)\n\t"
627 "cache\t%1, 0x1000(%0)\n\t"
628 "cache\t%1, 0x2000(%0)\n\t"
629 "cache\t%1, 0x3000(%0)\n\t"
630 "cache\t%2, 0(%0)\n\t"
631 "cache\t%2, 0x1000(%0)\n\t"
632 "cache\t%2, 0x2000(%0)\n\t"
633 "cache\t%2, 0x3000(%0)\n\t"
634 "cache\t%1, 0(%0)\n\t"
635 "cache\t%1, 0x1000(%0)\n\t"
636 "cache\t%1, 0x2000(%0)\n\t"
637 "cache\t%1, 0x3000(%0)\n\t"
641 : "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill));
645 static char *way_string[] = { NULL, "direct mapped", "2-way", "3-way", "4-way",
646 "5-way", "6-way", "7-way", "8-way"
649 static void __init probe_pcache(void)
651 struct cpuinfo_mips *c = ¤t_cpu_data;
652 unsigned int config = read_c0_config();
653 unsigned int prid = read_c0_prid();
654 unsigned long config1;
657 switch (c->cputype) {
658 case CPU_R4600: /* QED style two way caches? */
662 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
663 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
665 c->icache.waybit = ffs(icache_size/2) - 1;
667 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
668 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
670 c->dcache.waybit= ffs(dcache_size/2) - 1;
672 c->options |= MIPS_CPU_CACHE_CDEX_P;
677 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
678 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
682 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
683 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
685 c->dcache.waybit = 0;
687 c->options |= MIPS_CPU_CACHE_CDEX_P;
691 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
692 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
696 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
697 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
699 c->dcache.waybit = 0;
701 c->options |= MIPS_CPU_CACHE_CDEX_P;
711 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
712 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
714 c->icache.waybit = 0; /* doesn't matter */
716 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
717 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
719 c->dcache.waybit = 0; /* does not matter */
721 c->options |= MIPS_CPU_CACHE_CDEX_P;
726 icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29));
727 c->icache.linesz = 64;
729 c->icache.waybit = 0;
731 dcache_size = 1 << (12 + ((config & R10K_CONF_DC) >> 26));
732 c->dcache.linesz = 32;
734 c->dcache.waybit = 0;
736 c->options |= MIPS_CPU_PREFETCH;
740 write_c0_config(config & ~CONF_EB);
742 /* Workaround for cache instruction bug of VR4131 */
743 if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U ||
744 c->processor_id == 0x0c82U) {
745 config &= ~0x00000030U;
746 config |= 0x00410000U;
747 write_c0_config(config);
749 icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
750 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
752 c->icache.waybit = ffs(icache_size/2) - 1;
754 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
755 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
757 c->dcache.waybit = ffs(dcache_size/2) - 1;
759 c->options |= MIPS_CPU_CACHE_CDEX_P;
768 icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
769 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
771 c->icache.waybit = 0; /* doesn't matter */
773 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
774 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
776 c->dcache.waybit = 0; /* does not matter */
778 c->options |= MIPS_CPU_CACHE_CDEX_P;
785 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
786 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
788 c->icache.waybit = ffs(icache_size / c->icache.ways) - 1;
790 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
791 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
793 c->dcache.waybit = ffs(dcache_size / c->dcache.ways) - 1;
795 #if !defined(CONFIG_SMP) || !defined(RM9000_CDEX_SMP_WAR)
796 c->options |= MIPS_CPU_CACHE_CDEX_P;
798 c->options |= MIPS_CPU_PREFETCH;
802 if (!(config & MIPS_CONF_M))
803 panic("Don't know how to probe P-caches on this cpu.");
806 * So we seem to be a MIPS32 or MIPS64 CPU
807 * So let's probe the I-cache ...
809 config1 = read_c0_config1();
811 if ((lsize = ((config1 >> 19) & 7)))
812 c->icache.linesz = 2 << lsize;
814 c->icache.linesz = lsize;
815 c->icache.sets = 64 << ((config1 >> 22) & 7);
816 c->icache.ways = 1 + ((config1 >> 16) & 7);
818 icache_size = c->icache.sets *
821 c->icache.waybit = ffs(icache_size/c->icache.ways) - 1;
823 if (config & 0x8) /* VI bit */
824 c->icache.flags |= MIPS_CACHE_VTAG;
827 * Now probe the MIPS32 / MIPS64 data cache.
831 if ((lsize = ((config1 >> 10) & 7)))
832 c->dcache.linesz = 2 << lsize;
834 c->dcache.linesz= lsize;
835 c->dcache.sets = 64 << ((config1 >> 13) & 7);
836 c->dcache.ways = 1 + ((config1 >> 7) & 7);
838 dcache_size = c->dcache.sets *
841 c->dcache.waybit = ffs(dcache_size/c->dcache.ways) - 1;
843 c->options |= MIPS_CPU_PREFETCH;
848 * Processor configuration sanity check for the R4000SC erratum
849 * #5. With page sizes larger than 32kB there is no possibility
850 * to get a VCE exception anymore so we don't care about this
851 * misconfiguration. The case is rather theoretical anyway;
852 * presumably no vendor is shipping his hardware in the "bad"
855 if ((prid & 0xff00) == PRID_IMP_R4000 && (prid & 0xff) < 0x40 &&
856 !(config & CONF_SC) && c->icache.linesz != 16 &&
858 panic("Improper R4000SC processor configuration detected");
860 /* compute a couple of other cache variables */
861 c->icache.waysize = icache_size / c->icache.ways;
862 c->dcache.waysize = dcache_size / c->dcache.ways;
864 c->icache.sets = icache_size / (c->icache.linesz * c->icache.ways);
865 c->dcache.sets = dcache_size / (c->dcache.linesz * c->dcache.ways);
868 * R10000 and R12000 P-caches are odd in a positive way. They're 32kB
869 * 2-way virtually indexed so normally would suffer from aliases. So
870 * normally they'd suffer from aliases but magic in the hardware deals
871 * with that for us so we don't need to take care ourselves.
873 if (c->cputype != CPU_R10000 && c->cputype != CPU_R12000)
874 if (c->dcache.waysize > PAGE_SIZE)
875 c->dcache.flags |= MIPS_CACHE_ALIASES;
877 switch (c->cputype) {
880 * Some older 20Kc chips doesn't have the 'VI' bit in
881 * the config register.
883 c->icache.flags |= MIPS_CACHE_VTAG;
887 c->icache.flags |= MIPS_CACHE_IC_F_DC;
891 printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",
893 cpu_has_vtag_icache ? "virtually tagged" : "physically tagged",
894 way_string[c->icache.ways], c->icache.linesz);
896 printk("Primary data cache %ldkB %s, linesize %d bytes.\n",
897 dcache_size >> 10, way_string[c->dcache.ways], c->dcache.linesz);
901 * If you even _breathe_ on this function, look at the gcc output and make sure
902 * it does not pop things on and off the stack for the cache sizing loop that
903 * executes in KSEG1 space or else you will crash and burn badly. You have
906 static int __init probe_scache(void)
908 extern unsigned long stext;
909 unsigned long flags, addr, begin, end, pow2;
910 unsigned int config = read_c0_config();
911 struct cpuinfo_mips *c = ¤t_cpu_data;
914 if (config & CONF_SC)
917 begin = (unsigned long) &stext;
918 begin &= ~((4 * 1024 * 1024) - 1);
919 end = begin + (4 * 1024 * 1024);
922 * This is such a bitch, you'd think they would make it easy to do
923 * this. Away you daemons of stupidity!
925 local_irq_save(flags);
927 /* Fill each size-multiple cache line with a valid tag. */
929 for (addr = begin; addr < end; addr = (begin + pow2)) {
930 unsigned long *p = (unsigned long *) addr;
931 __asm__ __volatile__("nop" : : "r" (*p)); /* whee... */
935 /* Load first line with zero (therefore invalid) tag. */
938 __asm__ __volatile__("nop; nop; nop; nop;"); /* avoid the hazard */
939 cache_op(Index_Store_Tag_I, begin);
940 cache_op(Index_Store_Tag_D, begin);
941 cache_op(Index_Store_Tag_SD, begin);
943 /* Now search for the wrap around point. */
946 for (addr = begin + (128 * 1024); addr < end; addr = begin + pow2) {
947 cache_op(Index_Load_Tag_SD, addr);
948 __asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */
949 if (!read_c0_taglo())
953 local_irq_restore(flags);
957 c->scache.linesz = 16 << ((config & R4K_CONF_SB) >> 22);
959 c->dcache.waybit = 0; /* does not matter */
964 typedef int (*probe_func_t)(unsigned long);
965 extern int r5k_sc_init(void);
966 extern int rm7k_sc_init(void);
968 static void __init setup_scache(void)
970 struct cpuinfo_mips *c = ¤t_cpu_data;
971 unsigned int config = read_c0_config();
972 probe_func_t probe_scache_kseg1;
976 * Do the probing thing on R4000SC and R4400SC processors. Other
977 * processors don't have a S-cache that would be relevant to the
978 * Linux memory managment.
980 switch (c->cputype) {
985 probe_scache_kseg1 = (probe_func_t) (KSEG1ADDR(&probe_scache));
986 sc_present = probe_scache_kseg1(config);
988 c->options |= MIPS_CPU_CACHE_CDEX_S;
993 scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16);
994 c->scache.linesz = 64 << ((config >> 13) & 1);
1002 #ifdef CONFIG_R5000_CPU_SCACHE
1009 #ifdef CONFIG_RM7000_CPU_SCACHE
1021 if ((c->isa_level == MIPS_CPU_ISA_M32 ||
1022 c->isa_level == MIPS_CPU_ISA_M64) &&
1023 !(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
1024 panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
1026 /* compute a couple of other cache variables */
1027 c->scache.waysize = scache_size / c->scache.ways;
1029 c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
1031 printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1032 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1034 c->options |= MIPS_CPU_SUBSET_CACHES;
1037 static inline void coherency_setup(void)
1039 change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);
1042 * c0_status.cu=0 specifies that updates by the sc instruction use
1043 * the coherency mode specified by the TLB; 1 means cachable
1044 * coherent update on write will be used. Not all processors have
1045 * this bit and; some wire it to zero, others like Toshiba had the
1046 * silly idea of putting something else there ...
1048 switch (current_cpu_data.cputype) {
1055 clear_c0_config(CONF_CU);
1060 void __init ld_mmu_r4xx0(void)
1062 extern void build_clear_page(void);
1063 extern void build_copy_page(void);
1064 extern char except_vec2_generic;
1065 struct cpuinfo_mips *c = ¤t_cpu_data;
1067 /* Default cache error handler for R4000 and R5000 family */
1068 memcpy((void *)(CAC_BASE + 0x100), &except_vec2_generic, 0x80);
1069 memcpy((void *)(UNCAC_BASE + 0x100), &except_vec2_generic, 0x80);
1074 if (c->dcache.sets * c->dcache.ways > PAGE_SIZE)
1075 c->dcache.flags |= MIPS_CACHE_ALIASES;
1077 r4k_blast_dcache_page_setup();
1078 r4k_blast_dcache_page_indexed_setup();
1079 r4k_blast_dcache_setup();
1080 r4k_blast_icache_page_setup();
1081 r4k_blast_icache_page_indexed_setup();
1082 r4k_blast_icache_setup();
1083 r4k_blast_scache_page_setup();
1084 r4k_blast_scache_setup();
1087 * Some MIPS32 and MIPS64 processors have physically indexed caches.
1088 * This code supports virtually indexed processors and will be
1089 * unnecessarily inefficient on physically indexed processors.
1091 shm_align_mask = max_t( unsigned long,
1092 c->dcache.sets * c->dcache.linesz - 1,
1095 flush_cache_all = r4k_flush_cache_all;
1096 __flush_cache_all = r4k___flush_cache_all;
1097 flush_cache_mm = r4k_flush_cache_mm;
1098 flush_cache_page = r4k_flush_cache_page;
1099 flush_icache_page = r4k_flush_icache_page;
1100 flush_cache_range = r4k_flush_cache_range;
1102 flush_cache_sigtramp = r4k_flush_cache_sigtramp;
1103 flush_icache_all = r4k_flush_icache_all;
1104 flush_data_cache_page = r4k_flush_data_cache_page;
1105 flush_icache_range = r4k_flush_icache_range;
1107 #ifdef CONFIG_DMA_NONCOHERENT
1108 _dma_cache_wback_inv = r4k_dma_cache_wback_inv;
1109 _dma_cache_wback = r4k_dma_cache_wback_inv;
1110 _dma_cache_inv = r4k_dma_cache_inv;
1113 __flush_cache_all();