2 * Code to handle x86 style IRQs plus some generic interrupt stuff.
4 * Copyright (C) 1992 Linus Torvalds
5 * Copyright (C) 1994, 1995, 1996, 1997, 1998 Ralf Baechle
6 * Copyright (C) 1999 SuSE GmbH (Philipp Rumpf, prumpf@tux.org)
7 * Copyright (C) 1999-2000 Grant Grundler
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2, or (at your option)
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <linux/bitops.h>
24 #include <linux/config.h>
25 #include <linux/eisa.h>
26 #include <linux/errno.h>
27 #include <linux/init.h>
28 #include <linux/module.h>
29 #include <linux/signal.h>
30 #include <linux/types.h>
31 #include <linux/ioport.h>
32 #include <linux/timex.h>
33 #include <linux/slab.h>
34 #include <linux/random.h>
35 #include <linux/sched.h>
36 #include <linux/interrupt.h>
37 #include <linux/kernel_stat.h>
38 #include <linux/irq.h>
39 #include <linux/seq_file.h>
40 #include <linux/spinlock.h>
42 #include <asm/cache.h>
46 #undef PARISC_IRQ_CR16_COUNTS
48 extern irqreturn_t timer_interrupt(int, void *, struct pt_regs *);
49 extern irqreturn_t ipi_interrupt(int, void *, struct pt_regs *);
52 #define DBG_IRQ(irq, x) if ((irq) != TIMER_IRQ) printk x
54 #define DBG_IRQ(irq, x) do { } while (0)
55 #endif /* DEBUG_IRQ */
57 #define EIEM_MASK(irq) (1UL<<(CPU_IRQ_MAX - irq))
59 /* Bits in EIEM correlate with cpu_irq_action[].
60 ** Numbered *Big Endian*! (ie bit 0 is MSB)
62 static volatile unsigned long cpu_eiem = 0;
64 static void cpu_set_eiem(void *info)
66 set_eiem((unsigned long) info);
69 static inline void cpu_disable_irq(unsigned int irq)
71 unsigned long eirr_bit = EIEM_MASK(irq);
73 cpu_eiem &= ~eirr_bit;
74 on_each_cpu(cpu_set_eiem, (void *) cpu_eiem, 1, 1);
77 static void cpu_enable_irq(unsigned int irq)
79 unsigned long eirr_bit = EIEM_MASK(irq);
81 mtctl(eirr_bit, 23); /* clear EIRR bit before unmasking */
83 on_each_cpu(cpu_set_eiem, (void *) cpu_eiem, 1, 1);
86 static unsigned int cpu_startup_irq(unsigned int irq)
92 void no_ack_irq(unsigned int irq) { }
93 void no_end_irq(unsigned int irq) { }
95 static struct hw_interrupt_type cpu_interrupt_type = {
97 .startup = cpu_startup_irq,
98 .shutdown = cpu_disable_irq,
99 .enable = cpu_enable_irq,
100 .disable = cpu_disable_irq,
103 // .set_affinity = cpu_set_affinity_irq,
106 int show_interrupts(struct seq_file *p, void *v)
108 int i = *(loff_t *) v, j;
113 for_each_online_cpu(j)
114 seq_printf(p, " CPU%d", j);
116 #ifdef PARISC_IRQ_CR16_COUNTS
117 seq_printf(p, " [min/avg/max] (CPU cycle counts)");
123 spin_lock_irqsave(&irq_desc[i].lock, flags);
124 struct irqaction *action = irq_desc[i].action;
127 seq_printf(p, "%3d: ", i);
129 for_each_online_cpu(j)
130 seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
132 seq_printf(p, "%10u ", kstat_irqs(i));
135 seq_printf(p, " %14s", irq_desc[i].handler->typename);
136 #ifndef PARISC_IRQ_CR16_COUNTS
137 seq_printf(p, " %s", action->name);
139 while ((action = action->next))
140 seq_printf(p, ", %s", action->name);
142 for ( ;action; action = action->next) {
143 unsigned int k, avg, min, max;
145 min = max = action->cr16_hist[0];
147 for (avg = k = 0; k < PARISC_CR16_HIST_SIZE; k++) {
148 int hist = action->cr16_hist[k];
155 if (hist > max) max = hist;
156 if (hist < min) min = hist;
160 seq_printf(p, " %s[%d/%d/%d]", action->name,
167 spin_unlock_irqrestore(&irq_desc[i].lock, flags);
176 ** The following form a "set": Virtual IRQ, Transaction Address, Trans Data.
177 ** Respectively, these map to IRQ region+EIRR, Processor HPA, EIRR bit.
179 ** To use txn_XXX() interfaces, get a Virtual IRQ first.
180 ** Then use that to get the Transaction address and data.
183 int cpu_claim_irq(unsigned int irq, struct hw_interrupt_type *type, void *data)
185 if (irq_desc[irq].action)
187 if (irq_desc[irq].handler != &cpu_interrupt_type)
191 irq_desc[irq].handler = type;
192 irq_desc[irq].handler_data = data;
193 cpu_interrupt_type.enable(irq);
198 int txn_claim_irq(int irq)
200 return cpu_claim_irq(irq, NULL, NULL) ? -1 : irq;
203 int txn_alloc_irq(void)
207 /* never return irq 0 cause that's the interval timer */
208 for (irq = CPU_IRQ_BASE + 1; irq <= CPU_IRQ_MAX; irq++) {
209 if (cpu_claim_irq(irq, NULL, NULL) < 0)
214 /* unlikely, but be prepared */
218 unsigned long txn_alloc_addr(int virt_irq)
220 static int next_cpu = -1;
222 next_cpu++; /* assign to "next" CPU we want this bugger on */
225 while ((next_cpu < NR_CPUS) && (!cpu_data[next_cpu].txn_addr ||
226 !cpu_online(next_cpu)))
229 if (next_cpu >= NR_CPUS)
230 next_cpu = 0; /* nothing else, assign monarch */
232 return cpu_data[next_cpu].txn_addr;
237 ** The alloc process needs to accept a parameter to accommodate limitations
238 ** of the HW/SW which use these bits:
239 ** Legacy PA I/O (GSC/NIO): 5 bits (architected EIM register)
240 ** V-class (EPIC): 6 bits
241 ** N/L-class/A500: 8 bits (iosapic)
242 ** PCI 2.2 MSI: 16 bits (I think)
243 ** Existing PCI devices: 32-bits (all Symbios SCSI/ATM/HyperFabric)
245 ** On the service provider side:
246 ** o PA 1.1 (and PA2.0 narrow mode) 5-bits (width of EIR register)
247 ** o PA 2.0 wide mode 6-bits (per processor)
248 ** o IA64 8-bits (0-256 total)
250 ** So a Legacy PA I/O device on a PA 2.0 box can't use all
251 ** the bits supported by the processor...and the N/L-class
252 ** I/O subsystem supports more bits than PA2.0 has. The first
253 ** case is the problem.
255 unsigned int txn_alloc_data(int virt_irq, unsigned int bits_wide)
257 /* XXX FIXME : bits_wide indicates how wide the transaction
258 ** data is allowed to be...we may need a different virt_irq
259 ** if this one won't work. Another reason to index virtual
260 ** irq's into a table which can manage CPU/IRQ bit separately.
262 if ((virt_irq - CPU_IRQ_BASE) > (1 << (bits_wide - 1))) {
263 panic("Sorry -- didn't allocate valid IRQ for this device\n");
266 return virt_irq - CPU_IRQ_BASE;
269 /* ONLY called from entry.S:intr_extint() */
270 void do_cpu_irq_mask(struct pt_regs *regs)
272 unsigned long eirr_val;
273 unsigned int i=3; /* limit time in interrupt context */
276 * PSW_I or EIEM bits cannot be enabled until after the
277 * interrupts are processed.
278 * timer_interrupt() assumes it won't get interrupted when it
279 * holds the xtime_lock...an unmasked interrupt source could
280 * interrupt and deadlock by trying to grab xtime_lock too.
281 * Keeping PSW_I and EIEM disabled avoids this.
283 set_eiem(0UL); /* disable all extr interrupt for now */
285 /* 1) only process IRQs that are enabled/unmasked (cpu_eiem)
286 * 2) We loop here on EIRR contents in order to avoid
287 * nested interrupts or having to take another interrupt
288 * when we could have just handled it right away.
289 * 3) Limit the number of times we loop to make sure other
290 * processing can occur.
293 unsigned long bit = (1UL << (BITS_PER_LONG - 1));
295 eirr_val = mfctl(23) & cpu_eiem;
296 if (!eirr_val || !i--)
299 mtctl(eirr_val, 23); /* reset bits we are going to process */
302 if (eirr_val != (1UL << MAX_CPU_IRQ))
303 printk(KERN_DEBUG "do_cpu_irq_mask 0x%x & 0x%x\n", eirr_val, cpu_eiem);
306 /* Work our way from MSb to LSb...same order we alloc EIRs */
307 for (irq = TIMER_IRQ; eirr_val && bit; bit>>=1, irq++) {
308 if (!(bit & eirr_val & cpu_eiem))
311 /* clear bit in mask - can exit loop sooner */
321 static struct irqaction timer_action = {
322 .handler = timer_interrupt,
327 static struct irqaction ipi_action = {
328 .handler = ipi_interrupt,
333 static void claim_cpu_irqs(void)
336 for (i = CPU_IRQ_BASE; i <= CPU_IRQ_MAX; i++) {
337 irq_desc[i].handler = &cpu_interrupt_type;
340 irq_desc[TIMER_IRQ].action = &timer_action;
341 irq_desc[TIMER_IRQ].status |= IRQ_PER_CPU;
343 irq_desc[IPI_IRQ].action = &ipi_action;
344 irq_desc[IPI_IRQ].status = IRQ_PER_CPU;
348 void __init init_IRQ(void)
350 local_irq_disable(); /* PARANOID - should already be disabled */
351 mtctl(~0UL, 23); /* EIRR : clear all pending external intr */
355 cpu_eiem = EIEM_MASK(IPI_IRQ) | EIEM_MASK(TIMER_IRQ);
357 cpu_eiem = EIEM_MASK(TIMER_IRQ);
359 set_eiem(cpu_eiem); /* EIEM : enable all external intr */
363 void hw_resend_irq(struct hw_interrupt_type *type, unsigned int irq)
365 /* XXX: Needs to be written. We managed without it so far, but
366 * we really ought to write it.
370 void ack_bad_irq(unsigned int irq)
372 printk("unexpected IRQ %d\n", irq);