3 Copyright © 1997-1998 by PowerLogix R & D, Inc.
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 - First public release, contributed by PowerLogix.
24 - Terry: Made sure code disabled interrupts before running. (Previously
25 it was assumed interrupts were already disabled).
26 - Terry: Updated for tentative G4 support. 4MB of memory is now flushed
27 instead of 2MB. (Prob. only 3 is necessary).
28 - Terry: Updated for workaround to HID0[DPM] processor bug
29 during global invalidates.
32 - Terry: Added isync to correct for an errata.
35 - DanM: Finally added the 7450 patch I've had for the past
36 several months. The L2CR is similar, but I'm going
37 to assume the user of this functions knows what they
40 Author: Terry Greeniaus (tgree@phys.ualberta.ca)
41 Please e-mail updates to this file to me, thanks!
43 #include <linux/config.h>
44 #include <asm/processor.h>
45 #include <asm/cputable.h>
46 #include <asm/ppc_asm.h>
47 #include <asm/cache.h>
51 When setting the L2CR register, you must do a few special
52 things. If you are enabling the cache, you must perform a
53 global invalidate. If you are disabling the cache, you must
54 flush the cache contents first. This routine takes care of
55 doing these things. When first enabling the cache, make sure
56 you pass in the L2CR you want, as well as passing in the
57 global invalidate bit set. A global invalidate will only be
58 performed if the L2I bit is set in applyThis. When enabling
59 the cache, you should also set the L2E bit in applyThis. If
60 you want to modify the L2CR contents after the cache has been
61 enabled, the recommended procedure is to first call
62 __setL2CR(0) to disable the cache and then call it again with
63 the new values for L2CR. Examples:
65 _setL2CR(0) - disables the cache
66 _setL2CR(0xB3A04000) - enables my G3 upgrade card:
67 - L2E set to turn on the cache
70 - L2RAM set to pipelined synchronous late-write
71 - L2I set to perform a global invalidation
73 - L2DF set because this upgrade card
76 A similar call should work for your card. You need to know
77 the correct setting for your card and then place them in the
78 fields I have outlined above. Other fields support optional
79 features, such as L2DO which caches only data, or L2TS which
80 causes cache pushes from the L1 cache to go to the L2 cache
81 instead of to main memory.
84 Starting with the 7450, the bits in this register have moved
85 or behave differently. The Enable, Parity Enable, Size,
86 and L2 Invalidate are the only bits that have not moved.
87 The size is read-only for these processors with internal L2
88 cache, and the invalidate is a control as well as status.
93 * Summary: this procedure ignores the L2I bit in the value passed in,
94 * flushes the cache if it was already enabled, always invalidates the
95 * cache, then enables the cache if the L2E bit is set in the value
100 /* Make sure this is a 750 or 7400 chip */
104 END_FTR_SECTION_IFCLR(CPU_FTR_L2CR)
108 /* Stop DST streams */
112 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
114 /* Turn off interrupts and data relocation. */
115 mfmsr r7 /* Save MSR in r7 */
117 rlwinm r4,r4,0,28,26 /* Turn off DR bit */
122 /* Before we perform the global invalidation, we must disable dynamic
123 * power management via HID0[DPM] to work around a processor bug where
124 * DPM can possibly interfere with the state machine in the processor
125 * that invalidates the L2 cache tags.
127 mfspr r8,HID0 /* Save HID0 in r8 */
128 rlwinm r4,r8,0,12,10 /* Turn off HID0[DPM] */
130 mtspr HID0,r4 /* Disable DPM */
133 /* Get the current enable bit of the L2CR into r4 */
136 /* Tweak some bits */
137 rlwinm r5,r3,0,0,0 /* r5 contains the new enable bit */
138 rlwinm r3,r3,0,11,9 /* Turn off the invalidate bit */
139 rlwinm r3,r3,0,1,31 /* Turn off the enable bit */
141 /* Check to see if we need to flush */
145 /* Flush the cache. First, read the first 4MB of memory (physical) to
146 * put new data in the cache. (Actually we only need
147 * the size of the L2 cache plus the size of the L1 cache, but 4MB will
148 * cover everything just to be safe).
151 /**** Might be a good idea to set L2DO here - to prevent instructions
152 from getting into the cache. But since we invalidate
153 the next time we enable the cache it doesn't really matter.
154 Don't do this unless you accomodate all processor variations.
155 The bit moved on the 7450.....
158 /* TODO: use HW flush assist when available */
165 addi r4,r4,32 /* Go to start of next cache line */
169 /* Now, flush the first 4MB of memory */
176 addi r4,r4,32 /* Go to start of next cache line */
180 /* Set up the L2CR configuration bits (and switch L2 off) */
181 /* CPU errata: Make sure the mtspr below is already in the
185 .balign L1_CACHE_LINE_SIZE
198 /* Perform a global invalidation */
203 isync /* For errata */
206 /* On the 7450, we wait for the L2I bit to clear......
212 END_FTR_SECTION_IFSET(CPU_FTR_SPEC7450)
214 /* Wait for the invalidation to complete */
216 rlwinm. r4,r3,0,31,31
219 11: rlwinm r3,r3,0,11,9 /* Turn off the L2I bit */
224 /* See if we need to enable the cache */
228 /* Enable the cache */
235 /* Restore HID0[DPM] to whatever it was before */
240 /* Restore MSR (restores EE and DR bits to original state) */
249 /* Return the L2CR contents */
253 END_FTR_SECTION_IFSET(CPU_FTR_L2CR)
258 * Here is a similar routine for dealing with the L3 cache
259 * on the 745x family of chips
263 /* Make sure this is a 745x chip */
267 END_FTR_SECTION_IFCLR(CPU_FTR_L3CR)
269 /* Turn off interrupts and data relocation. */
270 mfmsr r7 /* Save MSR in r7 */
272 rlwinm r4,r4,0,28,26 /* Turn off DR bit */
277 /* Stop DST streams */
281 /* Get the current enable bit of the L3CR into r4 */
284 /* Tweak some bits */
285 rlwinm r5,r3,0,0,0 /* r5 contains the new enable bit */
286 rlwinm r3,r3,0,22,20 /* Turn off the invalidate bit */
287 rlwinm r3,r3,0,1,31 /* Turn off the enable bit */
288 rlwinm r3,r3,0,5,3 /* Turn off the clken bit */
289 /* Check to see if we need to flush */
296 /* TODO: use HW flush assist */
304 addi r4,r4,32 /* Go to start of next cache line */
308 /* Set up the L3CR configuration bits (and switch L3 off) */
313 oris r3,r3,L3CR_L3RES@h /* Set reserved bit 5 */
316 oris r3,r3,L3CR_L3CLKEN@h /* Set clken */
320 /* Wait for stabilize */
325 /* Perform a global invalidation */
332 /* We wait for the L3I bit to clear...... */
333 10: mfspr r3,SPRN_L3CR
338 rlwinm r3,r3,0,5,3 /* Turn off the clken bit */
342 /* Wait for stabilize */
347 /* See if we need to enable the cache */
351 /* Enable the cache */
352 oris r3,r3,(L3CR_L3E | L3CR_L3CLKEN)@h
356 /* Wait for stabilize */
361 /* Restore MSR (restores EE and DR bits to original state) */
368 /* Return the L3CR contents */
372 END_FTR_SECTION_IFSET(CPU_FTR_L3CR)
375 /* --- End of PowerLogix code ---
379 /* flush_disable_L1() - Flush and disable L1 cache
381 * clobbers r0, r3, ctr, cr0
384 _GLOBAL(__flush_disable_L1)
385 /* Stop pending alitvec streams and memory accesses */
388 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
391 /* Load counter to 0x4000 cache lines (512k) and
392 * load cache with datas
394 li r3,0x4000 /* 512kB / 32B */
399 addi r3,r3,0x0020 /* Go to start of next cache line */
404 /* Now flush those cache lines */
405 li r3,0x4000 /* 512kB / 32B */
410 addi r3,r3,0x0020 /* Go to start of next cache line */
414 /* We can now disable the L1 cache (HID0:DCE, HID0:ICE) */
422 /* inval_enable_L1 - Invalidate and enable L1 cache
424 * Assumes L1 is already disabled and MSR:EE is off
428 _GLOBAL(__inval_enable_L1)
429 /* Enable and then Flash inval the instruction & data cache */
431 ori r3,r3, HID0_ICE|HID0_ICFI|HID0_DCE|HID0_DCI
435 xori r3,r3, HID0_ICFI|HID0_DCI