arch/ppc/platforms/4xx/bamboo.c

   1 /*
   2  * arch/ppc/platforms/4xx/bamboo.c
   3  *
   4  * Bamboo board specific routines
   5  *
   6  * Wade Farnsworth <wfarnsworth@mvista.com>
   7  * Copyright 2004 MontaVista Software Inc.
   8  *
   9  * This program is free software; you can redistribute  it and/or modify it
  10  * under  the terms of  the GNU General  Public License as published by the
  11  * Free Software Foundation;  either version 2 of the  License, or (at your
  12  * option) any later version.
  13  */
  14
  15 #include <linux/config.h>
  16 #include <linux/stddef.h>
  17 #include <linux/kernel.h>
  18 #include <linux/init.h>
  19 #include <linux/errno.h>
  20 #include <linux/reboot.h>
  21 #include <linux/pci.h>
  22 #include <linux/kdev_t.h>
  23 #include <linux/types.h>
  24 #include <linux/major.h>
  25 #include <linux/blkdev.h>
  26 #include <linux/console.h>
  27 #include <linux/delay.h>
  28 #include <linux/ide.h>
  29 #include <linux/initrd.h>
  30 #include <linux/seq_file.h>
  31 #include <linux/root_dev.h>
  32 #include <linux/tty.h>
  33 #include <linux/serial.h>
  34 #include <linux/serial_core.h>
  35 #include <linux/ethtool.h>
  36
  37 #include <asm/system.h>
  38 #include <asm/pgtable.h>
  39 #include <asm/page.h>
  40 #include <asm/dma.h>
  41 #include <asm/io.h>
  42 #include <asm/machdep.h>
  43 #include <asm/ocp.h>
  44 #include <asm/pci-bridge.h>
  45 #include <asm/time.h>
  46 #include <asm/todc.h>
  47 #include <asm/bootinfo.h>
  48 #include <asm/ppc4xx_pic.h>
  49 #include <asm/ppcboot.h>
  50
  51 #include <syslib/gen550.h>
  52 #include <syslib/ibm440gx_common.h>
  53
  54 extern bd_t __res;
  55
  56 static struct ibm44x_clocks clocks __initdata;
  57
  58 /*
  59  * Bamboo external IRQ triggering/polarity settings
  60  */
  61 unsigned char ppc4xx_uic_ext_irq_cfg[] __initdata = {
  62         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ0: Ethernet transceiver */
  63         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ1: Expansion connector */
  64         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ2: PCI slot 0 */
  65         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ3: PCI slot 1 */
  66         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ4: PCI slot 2 */
  67         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ5: PCI slot 3 */
  68         (IRQ_SENSE_EDGE  | IRQ_POLARITY_NEGATIVE), /* IRQ6: SMI pushbutton */
  69         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ7: EXT */
  70         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ8: EXT */
  71         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ9: EXT */
  72 };
  73
  74 static void __init
  75 bamboo_calibrate_decr(void)
  76 {
  77         unsigned int freq;
  78
  79         if (mfspr(SPRN_CCR1) & CCR1_TCS)
  80                 freq = BAMBOO_TMRCLK;
  81         else
  82                 freq = clocks.cpu;
  83
  84         ibm44x_calibrate_decr(freq);
  85
  86 }
  87
  88 static int
  89 bamboo_show_cpuinfo(struct seq_file *m)
  90 {
  91         seq_printf(m, "vendor\t\t: IBM\n");
  92         seq_printf(m, "machine\t\t: PPC440EP EVB (Bamboo)\n");
  93
  94         return 0;
  95 }
  96
  97 static inline int
  98 bamboo_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
  99 {
 100         static char pci_irq_table[][4] =
 101         /*
 102          *      PCI IDSEL/INTPIN->INTLINE
 103          *         A   B   C   D
 104          */
 105         {
 106                 { 28, 28, 28, 28 },     /* IDSEL 1 - PCI Slot 0 */
 107                 { 27, 27, 27, 27 },     /* IDSEL 2 - PCI Slot 1 */
 108                 { 26, 26, 26, 26 },     /* IDSEL 3 - PCI Slot 2 */
 109                 { 25, 25, 25, 25 },     /* IDSEL 4 - PCI Slot 3 */
 110         };
 111
 112         const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
 113         return PCI_IRQ_TABLE_LOOKUP;
 114 }
 115
 116 static void __init bamboo_set_emacdata(void)
 117 {
 118         u8 * base_addr;
 119         struct ocp_def *def;
 120         struct ocp_func_emac_data *emacdata;
 121         u8 val;
 122         int mode;
 123         u32 excluded = 0;
 124
 125         base_addr = ioremap64(BAMBOO_FPGA_SELECTION1_REG_ADDR, 16);
 126         val = readb(base_addr);
 127         iounmap((void *) base_addr);
 128         if (BAMBOO_SEL_MII(val))
 129                 mode = PHY_MODE_MII;
 130         else if (BAMBOO_SEL_RMII(val))
 131                 mode = PHY_MODE_RMII;
 132         else
 133                 mode = PHY_MODE_SMII;
 134
 135         /*
 136          * SW2 on the Bamboo is used for ethernet configuration and is accessed
 137          * via the CONFIG2 register in the FPGA.  If the ANEG pin is set,
 138          * overwrite the supported features with the settings in SW2.
 139          *
 140          * This is used as a workaround for the improperly biased RJ-45 sockets
 141          * on the Rev. 0 Bamboo.  By default only 10baseT is functional.
 142          * Removing inductors L17 and L18 from the board allows 100baseT, but
 143          * disables 10baseT.  The Rev. 1 has no such limitations.
 144          */
 145
 146         base_addr = ioremap64(BAMBOO_FPGA_CONFIG2_REG_ADDR, 8);
 147         val = readb(base_addr);
 148         iounmap((void *) base_addr);
 149         if (!BAMBOO_AUTONEGOTIATE(val)) {
 150                 excluded |= SUPPORTED_Autoneg;
 151                 if (BAMBOO_FORCE_100Mbps(val)) {
 152                         excluded |= SUPPORTED_10baseT_Full;
 153                         excluded |= SUPPORTED_10baseT_Half;
 154                         if (BAMBOO_FULL_DUPLEX_EN(val))
 155                                 excluded |= SUPPORTED_100baseT_Half;
 156                         else
 157                                 excluded |= SUPPORTED_100baseT_Full;
 158                 } else {
 159                         excluded |= SUPPORTED_100baseT_Full;
 160                         excluded |= SUPPORTED_100baseT_Half;
 161                         if (BAMBOO_FULL_DUPLEX_EN(val))
 162                                 excluded |= SUPPORTED_10baseT_Half;
 163                         else
 164                                 excluded |= SUPPORTED_10baseT_Full;
 165                 }
 166         }
 167
 168         /* Set mac_addr, phy mode and unsupported phy features for each EMAC */
 169
 170         def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 0);
 171         emacdata = def->additions;
 172         memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
 173         emacdata->phy_mode = mode;
 174         emacdata->phy_feat_exc = excluded;
 175
 176         def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 1);
 177         emacdata = def->additions;
 178         memcpy(emacdata->mac_addr, __res.bi_enet1addr, 6);
 179         emacdata->phy_mode = mode;
 180         emacdata->phy_feat_exc = excluded;
 181 }
 182
 183 static int
 184 bamboo_exclude_device(unsigned char bus, unsigned char devfn)
 185 {
 186         return (bus == 0 && devfn == 0);
 187 }
 188
 189 #define PCI_READW(offset) \
 190         (readw((void *)((u32)pci_reg_base+offset)))
 191
 192 #define PCI_WRITEW(value, offset) \
 193         (writew(value, (void *)((u32)pci_reg_base+offset)))
 194
 195 #define PCI_WRITEL(value, offset) \
 196         (writel(value, (void *)((u32)pci_reg_base+offset)))
 197
 198 static void __init
 199 bamboo_setup_pci(void)
 200 {
 201         void *pci_reg_base;
 202         unsigned long memory_size;
 203         memory_size = ppc_md.find_end_of_memory();
 204
 205         pci_reg_base = ioremap64(BAMBOO_PCIL0_BASE, BAMBOO_PCIL0_SIZE);
 206
 207         /* Enable PCI I/O, Mem, and Busmaster cycles */
 208         PCI_WRITEW(PCI_READW(PCI_COMMAND) |
 209                    PCI_COMMAND_MEMORY |
 210                    PCI_COMMAND_MASTER, PCI_COMMAND);
 211
 212         /* Disable region first */
 213         PCI_WRITEL(0, BAMBOO_PCIL0_PMM0MA);
 214
 215         /* PLB starting addr: 0x00000000A0000000 */
 216         PCI_WRITEL(BAMBOO_PCI_PHY_MEM_BASE, BAMBOO_PCIL0_PMM0LA);
 217
 218         /* PCI start addr, 0xA0000000 (PCI Address) */
 219         PCI_WRITEL(BAMBOO_PCI_MEM_BASE, BAMBOO_PCIL0_PMM0PCILA);
 220         PCI_WRITEL(0, BAMBOO_PCIL0_PMM0PCIHA);
 221
 222         /* Enable no pre-fetch, enable region */
 223         PCI_WRITEL(((0xffffffff -
 224                      (BAMBOO_PCI_UPPER_MEM - BAMBOO_PCI_MEM_BASE)) | 0x01),
 225                       BAMBOO_PCIL0_PMM0MA);
 226
 227         /* Disable region one */
 228         PCI_WRITEL(0, BAMBOO_PCIL0_PMM1MA);
 229         PCI_WRITEL(0, BAMBOO_PCIL0_PMM1LA);
 230         PCI_WRITEL(0, BAMBOO_PCIL0_PMM1PCILA);
 231         PCI_WRITEL(0, BAMBOO_PCIL0_PMM1PCIHA);
 232         PCI_WRITEL(0, BAMBOO_PCIL0_PMM1MA);
 233
 234         /* Disable region two */
 235         PCI_WRITEL(0, BAMBOO_PCIL0_PMM2MA);
 236         PCI_WRITEL(0, BAMBOO_PCIL0_PMM2LA);
 237         PCI_WRITEL(0, BAMBOO_PCIL0_PMM2PCILA);
 238         PCI_WRITEL(0, BAMBOO_PCIL0_PMM2PCIHA);
 239         PCI_WRITEL(0, BAMBOO_PCIL0_PMM2MA);
 240
 241         /* Now configure the PCI->PLB windows, we only use PTM1
 242          *
 243          * For Inbound flow, set the window size to all available memory
 244          * This is required because if size is smaller,
 245          * then Eth/PCI DD would fail as PCI card not able to access
 246          * the memory allocated by DD.
 247          */
 248
 249         PCI_WRITEL(0, BAMBOO_PCIL0_PTM1MS);     /* disabled region 1 */
 250         PCI_WRITEL(0, BAMBOO_PCIL0_PTM1LA);     /* begin of address map */
 251
 252         memory_size = 1 << fls(memory_size - 1);
 253
 254         /* Size low + Enabled */
 255         PCI_WRITEL((0xffffffff - (memory_size - 1)) | 0x1, BAMBOO_PCIL0_PTM1MS);
 256
 257         eieio();
 258         iounmap(pci_reg_base);
 259 }
 260
 261 static void __init
 262 bamboo_setup_hose(void)
 263 {
 264         unsigned int bar_response, bar;
 265         struct pci_controller *hose;
 266
 267         bamboo_setup_pci();
 268
 269         hose = pcibios_alloc_controller();
 270
 271         if (!hose)
 272                 return;
 273
 274         hose->first_busno = 0;
 275         hose->last_busno = 0xff;
 276
 277         hose->pci_mem_offset = BAMBOO_PCI_MEM_OFFSET;
 278
 279         pci_init_resource(&hose->io_resource,
 280                         BAMBOO_PCI_LOWER_IO,
 281                         BAMBOO_PCI_UPPER_IO,
 282                         IORESOURCE_IO,
 283                         "PCI host bridge");
 284
 285         pci_init_resource(&hose->mem_resources[0],
 286                         BAMBOO_PCI_LOWER_MEM,
 287                         BAMBOO_PCI_UPPER_MEM,
 288                         IORESOURCE_MEM,
 289                         "PCI host bridge");
 290
 291         ppc_md.pci_exclude_device = bamboo_exclude_device;
 292
 293         hose->io_space.start = BAMBOO_PCI_LOWER_IO;
 294         hose->io_space.end = BAMBOO_PCI_UPPER_IO;
 295         hose->mem_space.start = BAMBOO_PCI_LOWER_MEM;
 296         hose->mem_space.end = BAMBOO_PCI_UPPER_MEM;
 297         isa_io_base =
 298                 (unsigned long)ioremap64(BAMBOO_PCI_IO_BASE, BAMBOO_PCI_IO_SIZE);
 299         hose->io_base_virt = (void *)isa_io_base;
 300
 301         setup_indirect_pci(hose,
 302                         BAMBOO_PCI_CFGA_PLB32,
 303                         BAMBOO_PCI_CFGD_PLB32);
 304         hose->set_cfg_type = 1;
 305
 306         /* Zero config bars */
 307         for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
 308                 early_write_config_dword(hose, hose->first_busno,
 309                                          PCI_FUNC(hose->first_busno), bar,
 310                                          0x00000000);
 311                 early_read_config_dword(hose, hose->first_busno,
 312                                         PCI_FUNC(hose->first_busno), bar,
 313                                         &bar_response);
 314         }
 315
 316         hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
 317
 318         ppc_md.pci_swizzle = common_swizzle;
 319         ppc_md.pci_map_irq = bamboo_map_irq;
 320 }
 321
 322 TODC_ALLOC();
 323
 324 static void __init
 325 bamboo_early_serial_map(void)
 326 {
 327         struct uart_port port;
 328
 329         /* Setup ioremapped serial port access */
 330         memset(&port, 0, sizeof(port));
 331         port.membase = ioremap64(PPC440EP_UART0_ADDR, 8);
 332         port.irq = 0;
 333         port.uartclk = clocks.uart0;
 334         port.regshift = 0;
 335         port.iotype = UPIO_MEM;
 336         port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
 337         port.line = 0;
 338
 339         if (early_serial_setup(&port) != 0) {
 340                 printk("Early serial init of port 0 failed\n");
 341         }
 342
 343 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
 344         /* Configure debug serial access */
 345         gen550_init(0, &port);
 346 #endif
 347
 348         port.membase = ioremap64(PPC440EP_UART1_ADDR, 8);
 349         port.irq = 1;
 350         port.uartclk = clocks.uart1;
 351         port.line = 1;
 352
 353         if (early_serial_setup(&port) != 0) {
 354                 printk("Early serial init of port 1 failed\n");
 355         }
 356
 357 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
 358         /* Configure debug serial access */
 359         gen550_init(1, &port);
 360 #endif
 361
 362         port.membase = ioremap64(PPC440EP_UART2_ADDR, 8);
 363         port.irq = 3;
 364         port.uartclk = clocks.uart2;
 365         port.line = 2;
 366
 367         if (early_serial_setup(&port) != 0) {
 368                 printk("Early serial init of port 2 failed\n");
 369         }
 370
 371 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
 372         /* Configure debug serial access */
 373         gen550_init(2, &port);
 374 #endif
 375
 376         port.membase = ioremap64(PPC440EP_UART3_ADDR, 8);
 377         port.irq = 4;
 378         port.uartclk = clocks.uart3;
 379         port.line = 3;
 380
 381         if (early_serial_setup(&port) != 0) {
 382                 printk("Early serial init of port 3 failed\n");
 383         }
 384 }
 385
 386 static void __init
 387 bamboo_setup_arch(void)
 388 {
 389
 390         bamboo_set_emacdata();
 391
 392         ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
 393         ocp_sys_info.opb_bus_freq = clocks.opb;
 394
 395         /* Setup TODC access */
 396         TODC_INIT(TODC_TYPE_DS1743,
 397                         0,
 398                         0,
 399                         ioremap64(BAMBOO_RTC_ADDR, BAMBOO_RTC_SIZE),
 400                         8);
 401
 402         /* init to some ~sane value until calibrate_delay() runs */
 403         loops_per_jiffy = 50000000/HZ;
 404
 405         /* Setup PCI host bridge */
 406         bamboo_setup_hose();
 407
 408 #ifdef CONFIG_BLK_DEV_INITRD
 409         if (initrd_start)
 410                 ROOT_DEV = Root_RAM0;
 411         else
 412 #endif
 413 #ifdef CONFIG_ROOT_NFS
 414                 ROOT_DEV = Root_NFS;
 415 #else
 416                 ROOT_DEV = Root_HDA1;
 417 #endif
 418
 419         bamboo_early_serial_map();
 420
 421         /* Identify the system */
 422         printk("IBM Bamboo port (MontaVista Software, Inc. (source@mvista.com))\n");
 423 }
 424
 425 void __init platform_init(unsigned long r3, unsigned long r4,
 426                 unsigned long r5, unsigned long r6, unsigned long r7)
 427 {
 428         ibm44x_platform_init(r3, r4, r5, r6, r7);
 429
 430         ppc_md.setup_arch = bamboo_setup_arch;
 431         ppc_md.show_cpuinfo = bamboo_show_cpuinfo;
 432         ppc_md.get_irq = NULL;          /* Set in ppc4xx_pic_init() */
 433
 434         ppc_md.calibrate_decr = bamboo_calibrate_decr;
 435         ppc_md.time_init = todc_time_init;
 436         ppc_md.set_rtc_time = todc_set_rtc_time;
 437         ppc_md.get_rtc_time = todc_get_rtc_time;
 438
 439         ppc_md.nvram_read_val = todc_direct_read_val;
 440         ppc_md.nvram_write_val = todc_direct_write_val;
 441 #ifdef CONFIG_KGDB
 442         ppc_md.early_serial_map = bamboo_early_serial_map;
 443 #endif
 444 }
 445