2 * arch/ppc/platforms/4xx/ebony.c
4 * Ebony board specific routines
6 * Matt Porter <mporter@kernel.crashing.org>
7 * Copyright 2002-2004 MontaVista Software Inc.
9 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
10 * Copyright (c) 2003, 2004 Zultys Technologies
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
18 #include <linux/config.h>
19 #include <linux/stddef.h>
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/errno.h>
23 #include <linux/reboot.h>
24 #include <linux/pci.h>
25 #include <linux/kdev_t.h>
26 #include <linux/types.h>
27 #include <linux/major.h>
28 #include <linux/blkdev.h>
29 #include <linux/console.h>
30 #include <linux/delay.h>
31 #include <linux/ide.h>
32 #include <linux/initrd.h>
33 #include <linux/irq.h>
34 #include <linux/seq_file.h>
35 #include <linux/root_dev.h>
36 #include <linux/tty.h>
37 #include <linux/serial.h>
38 #include <linux/serial_core.h>
40 #include <asm/system.h>
41 #include <asm/pgtable.h>
45 #include <asm/machdep.h>
47 #include <asm/pci-bridge.h>
50 #include <asm/bootinfo.h>
51 #include <asm/ppc4xx_pic.h>
53 #include <syslib/gen550.h>
55 static struct ibm44x_clocks clocks __initdata;
58 * Ebony IRQ triggering/polarity settings
60 static u_char ebony_IRQ_initsenses[] __initdata = {
61 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 0: UART 0 */
62 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 1: UART 1 */
63 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 2: IIC 0 */
64 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 3: IIC 1 */
65 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 4: PCI Inb Mess */
66 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 5: PCI Cmd Wrt */
67 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 6: PCI PM */
68 (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 7: PCI MSI 0 */
69 (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 8: PCI MSI 1 */
70 (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 9: PCI MSI 2 */
71 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 10: MAL TX EOB */
72 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 11: MAL RX EOB */
73 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 12: DMA Chan 0 */
74 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 13: DMA Chan 1 */
75 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 14: DMA Chan 2 */
76 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 15: DMA Chan 3 */
77 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 16: Reserved */
78 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 17: Reserved */
79 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 18: GPT Timer 0 */
80 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 19: GPT Timer 1 */
81 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 20: GPT Timer 2 */
82 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 21: GPT Timer 3 */
83 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 22: GPT Timer 4 */
84 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 23: Ext Int 0 */
85 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 24: Ext Int 1 */
86 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 25: Ext Int 2 */
87 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 26: Ext Int 3 */
88 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 27: Ext Int 4 */
89 (IRQ_SENSE_EDGE | IRQ_POLARITY_NEGATIVE), /* 28: Ext Int 5 */
90 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 29: Ext Int 6 */
91 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 30: UIC1 NC Int */
92 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 31: UIC1 Crit Int */
93 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 32: MAL SERR */
94 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 33: MAL TXDE */
95 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 34: MAL RXDE */
96 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 35: ECC Unc Err */
97 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 36: ECC Corr Err */
98 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 37: Ext Bus Ctrl */
99 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 38: Ext Bus Mstr */
100 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 39: OPB->PLB */
101 (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 40: PCI MSI 3 */
102 (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 41: PCI MSI 4 */
103 (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 42: PCI MSI 5 */
104 (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 43: PCI MSI 6 */
105 (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 44: PCI MSI 7 */
106 (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 45: PCI MSI 8 */
107 (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 46: PCI MSI 9 */
108 (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 47: PCI MSI 10 */
109 (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 48: PCI MSI 11 */
110 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 49: PLB Perf Mon */
111 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 50: Ext Int 7 */
112 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 51: Ext Int 8 */
113 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 52: Ext Int 9 */
114 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 53: Ext Int 10 */
115 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 54: Ext Int 11 */
116 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 55: Ext Int 12 */
117 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 56: Ser ROM Err */
118 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 57: Reserved */
119 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 58: Reserved */
120 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 59: PCI Async Err */
121 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 60: EMAC 0 */
122 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 61: EMAC 0 WOL */
123 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 62: EMAC 1 */
124 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 63: EMAC 1 WOL */
128 ebony_calibrate_decr(void)
133 * Determine system clock speed
135 * If we are on Rev. B silicon, then use
136 * default external system clock. If we are
137 * on Rev. C silicon then errata forces us to
138 * use the internal clock.
140 switch (PVR_REV(mfspr(PVR))) {
141 case PVR_REV(PVR_440GP_RB):
142 freq = EBONY_440GP_RB_SYSCLK;
144 case PVR_REV(PVR_440GP_RC1):
146 freq = EBONY_440GP_RC_SYSCLK;
150 ibm44x_calibrate_decr(freq);
154 ebony_show_cpuinfo(struct seq_file *m)
156 seq_printf(m, "vendor\t\t: IBM\n");
157 seq_printf(m, "machine\t\t: Ebony\n");
163 ebony_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
165 static char pci_irq_table[][4] =
167 * PCI IDSEL/INTPIN->INTLINE
171 { 23, 23, 23, 23 }, /* IDSEL 1 - PCI Slot 0 */
172 { 24, 24, 24, 24 }, /* IDSEL 2 - PCI Slot 1 */
173 { 25, 25, 25, 25 }, /* IDSEL 3 - PCI Slot 2 */
174 { 26, 26, 26, 26 }, /* IDSEL 4 - PCI Slot 3 */
177 const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
178 return PCI_IRQ_TABLE_LOOKUP;
181 #define PCIX_WRITEL(value, offset) \
182 (writel(value, (u32)pcix_reg_base+offset))
185 * FIXME: This is only here to "make it work". This will move
186 * to a ibm_pcix.c which will contain a generic IBM PCIX bridge
187 * configuration library. -Matt
190 ebony_setup_pcix(void)
194 pcix_reg_base = ioremap64(PCIX0_REG_BASE, PCIX0_REG_SIZE);
196 /* Disable all windows */
197 PCIX_WRITEL(0, PCIX0_POM0SA);
198 PCIX_WRITEL(0, PCIX0_POM1SA);
199 PCIX_WRITEL(0, PCIX0_POM2SA);
200 PCIX_WRITEL(0, PCIX0_PIM0SA);
201 PCIX_WRITEL(0, PCIX0_PIM1SA);
202 PCIX_WRITEL(0, PCIX0_PIM2SA);
204 /* Setup 2GB PLB->PCI outbound mem window (3_8000_0000->0_8000_0000) */
205 PCIX_WRITEL(0x00000003, PCIX0_POM0LAH);
206 PCIX_WRITEL(0x80000000, PCIX0_POM0LAL);
207 PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH);
208 PCIX_WRITEL(0x80000000, PCIX0_POM0PCIAL);
209 PCIX_WRITEL(0x80000001, PCIX0_POM0SA);
211 /* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */
212 PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH);
213 PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL);
214 PCIX_WRITEL(0x80000007, PCIX0_PIM0SA);
220 ebony_setup_hose(void)
222 struct pci_controller *hose;
224 /* Configure windows on the PCI-X host bridge */
227 hose = pcibios_alloc_controller();
232 hose->first_busno = 0;
233 hose->last_busno = 0xff;
235 hose->pci_mem_offset = EBONY_PCI_MEM_OFFSET;
237 pci_init_resource(&hose->io_resource,
243 pci_init_resource(&hose->mem_resources[0],
249 hose->io_space.start = EBONY_PCI_LOWER_IO;
250 hose->io_space.end = EBONY_PCI_UPPER_IO;
251 hose->mem_space.start = EBONY_PCI_LOWER_MEM;
252 hose->mem_space.end = EBONY_PCI_UPPER_MEM;
254 (unsigned long)ioremap64(EBONY_PCI_IO_BASE, EBONY_PCI_IO_SIZE);
255 hose->io_base_virt = (void *)isa_io_base;
257 setup_indirect_pci(hose,
258 EBONY_PCI_CFGA_PLB32,
259 EBONY_PCI_CFGD_PLB32);
260 hose->set_cfg_type = 1;
262 hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
264 ppc_md.pci_swizzle = common_swizzle;
265 ppc_md.pci_map_irq = ebony_map_irq;
271 ebony_early_serial_map(void)
273 struct uart_port port;
275 /* Setup ioremapped serial port access */
276 memset(&port, 0, sizeof(port));
277 port.membase = ioremap64(PPC440GP_UART0_ADDR, 8);
279 port.uartclk = clocks.uart0;
281 port.iotype = SERIAL_IO_MEM;
282 port.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
285 if (early_serial_setup(&port) != 0) {
286 printk("Early serial init of port 0 failed\n");
289 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
290 /* Configure debug serial access */
291 gen550_init(0, &port);
294 port.membase = ioremap64(PPC440GP_UART1_ADDR, 8);
296 port.uartclk = clocks.uart1;
299 if (early_serial_setup(&port) != 0) {
300 printk("Early serial init of port 1 failed\n");
303 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
304 /* Configure debug serial access */
305 gen550_init(1, &port);
310 ebony_setup_arch(void)
312 unsigned char * vpd_base;
314 struct ocp_func_emac_data *emacdata;
316 /* Set mac_addr for each EMAC */
317 vpd_base = ioremap64(EBONY_VPD_BASE, EBONY_VPD_SIZE);
318 def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 0);
319 emacdata = def->additions;
320 memcpy(emacdata->mac_addr, EBONY_NA0_ADDR(vpd_base), 6);
321 def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 1);
322 emacdata = def->additions;
323 memcpy(emacdata->mac_addr, EBONY_NA1_ADDR(vpd_base), 6);
327 * Determine various clocks.
328 * To be completely correct we should get SysClk
329 * from FPGA, because it can be changed by on-board switches
332 ibm440gp_get_clocks(&clocks, 33333333, 6 * 1843200);
333 ocp_sys_info.opb_bus_freq = clocks.opb;
335 /* Setup TODC access */
336 TODC_INIT(TODC_TYPE_DS1743,
339 ioremap64(EBONY_RTC_ADDR, EBONY_RTC_SIZE),
342 /* init to some ~sane value until calibrate_delay() runs */
343 loops_per_jiffy = 50000000/HZ;
345 /* Setup PCI host bridge */
348 #ifdef CONFIG_BLK_DEV_INITRD
350 ROOT_DEV = Root_RAM0;
353 #ifdef CONFIG_ROOT_NFS
356 ROOT_DEV = Root_HDA1;
359 ebony_early_serial_map();
361 ibm4xxPIC_InitSenses = ebony_IRQ_initsenses;
362 ibm4xxPIC_NumInitSenses = sizeof(ebony_IRQ_initsenses);
364 /* Identify the system */
365 printk("IBM Ebony port (MontaVista Software, Inc. (source@mvista.com))\n");
368 void __init platform_init(unsigned long r3, unsigned long r4,
369 unsigned long r5, unsigned long r6, unsigned long r7)
371 parse_bootinfo((struct bi_record *) (r3 + KERNELBASE));
373 ibm44x_platform_init();
375 ppc_md.setup_arch = ebony_setup_arch;
376 ppc_md.show_cpuinfo = ebony_show_cpuinfo;
377 ppc_md.get_irq = NULL; /* Set in ppc4xx_pic_init() */
379 ppc_md.calibrate_decr = ebony_calibrate_decr;
380 ppc_md.time_init = todc_time_init;
381 ppc_md.set_rtc_time = todc_set_rtc_time;
382 ppc_md.get_rtc_time = todc_get_rtc_time;
384 ppc_md.nvram_read_val = todc_direct_read_val;
385 ppc_md.nvram_write_val = todc_direct_write_val;
387 ppc_md.early_serial_map = ebony_early_serial_map;