2 * arch/ppc/platform/85xx/mpc85xx_cds_common.c
4 * MPC85xx CDS board specific routines
6 * Maintainer: Kumar Gala <kumar.gala@freescale.com>
8 * Copyright 2004 Freescale Semiconductor, Inc
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
16 #include <linux/config.h>
17 #include <linux/stddef.h>
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/errno.h>
21 #include <linux/reboot.h>
22 #include <linux/pci.h>
23 #include <linux/kdev_t.h>
24 #include <linux/major.h>
25 #include <linux/console.h>
26 #include <linux/delay.h>
27 #include <linux/irq.h>
28 #include <linux/seq_file.h>
29 #include <linux/serial.h>
30 #include <linux/module.h>
31 #include <linux/root_dev.h>
32 #include <linux/initrd.h>
33 #include <linux/tty.h>
34 #include <linux/serial_core.h>
36 #include <asm/system.h>
37 #include <asm/pgtable.h>
39 #include <asm/atomic.h>
42 #include <asm/machdep.h>
44 #include <asm/open_pic.h>
45 #include <asm/bootinfo.h>
46 #include <asm/pci-bridge.h>
47 #include <asm/mpc85xx.h>
49 #include <asm/immap_85xx.h>
50 #include <asm/immap_cpm2.h>
54 #include <mm/mmu_decl.h>
55 #include <syslib/cpm2_pic.h>
56 #include <syslib/ppc85xx_common.h>
57 #include <syslib/ppc85xx_setup.h>
61 unsigned long isa_io_base = 0;
62 unsigned long isa_mem_base = 0;
65 extern unsigned long total_memory; /* in mm/init */
67 unsigned char __res[sizeof (bd_t)];
69 static int cds_pci_slot = 2;
70 static volatile u8 * cadmus;
72 /* Internal interrupts are all Level Sensitive, and Positive Polarity */
74 static u_char mpc85xx_cds_openpic_initsenses[] __initdata = {
75 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 0: L2 Cache */
76 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 1: ECM */
77 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 2: DDR DRAM */
78 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 3: LBIU */
79 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 4: DMA 0 */
80 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 5: DMA 1 */
81 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 6: DMA 2 */
82 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 7: DMA 3 */
83 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 8: PCI/PCI-X */
84 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 9: RIO Inbound Port Write Error */
85 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 10: RIO Doorbell Inbound */
86 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 11: RIO Outbound Message */
87 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 12: RIO Inbound Message */
88 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 13: TSEC 0 Transmit */
89 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 14: TSEC 0 Receive */
90 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 15: Unused */
91 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 16: Unused */
92 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 17: Unused */
93 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 18: TSEC 0 Receive/Transmit Error */
94 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 19: TSEC 1 Transmit */
95 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 20: TSEC 1 Receive */
96 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 21: Unused */
97 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 22: Unused */
98 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 23: Unused */
99 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 24: TSEC 1 Receive/Transmit Error */
100 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 25: Fast Ethernet */
101 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 26: DUART */
102 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 27: I2C */
103 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 28: Performance Monitor */
104 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 29: Unused */
105 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 30: CPM */
106 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 31: Unused */
107 #if defined(CONFIG_PCI)
108 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 0: PCI1 slot */
109 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 1: PCI1 slot */
110 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 2: PCI1 slot */
111 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 3: PCI1 slot */
113 0x0, /* External 0: */
114 0x0, /* External 1: */
115 0x0, /* External 2: */
116 0x0, /* External 3: */
118 0x0, /* External 4: */
119 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 5: PHY */
120 0x0, /* External 6: */
121 0x0, /* External 7: */
122 0x0, /* External 8: */
123 0x0, /* External 9: */
124 0x0, /* External 10: */
125 #if defined(CONFIG_85xx_PCI2) && defined(CONFIG_PCI)
126 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 11: PCI2 slot 0 */
128 0x0, /* External 11: */
132 struct ocp_gfar_data mpc85xx_tsec1_def = {
133 .interruptTransmit = MPC85xx_IRQ_TSEC1_TX,
134 .interruptError = MPC85xx_IRQ_TSEC1_ERROR,
135 .interruptReceive = MPC85xx_IRQ_TSEC1_RX,
136 .interruptPHY = MPC85xx_IRQ_EXT5,
137 .flags = (GFAR_HAS_GIGABIT | GFAR_HAS_MULTI_INTR |
143 struct ocp_gfar_data mpc85xx_tsec2_def = {
144 .interruptTransmit = MPC85xx_IRQ_TSEC2_TX,
145 .interruptError = MPC85xx_IRQ_TSEC2_ERROR,
146 .interruptReceive = MPC85xx_IRQ_TSEC2_RX,
147 .interruptPHY = MPC85xx_IRQ_EXT5,
148 .flags = (GFAR_HAS_GIGABIT | GFAR_HAS_MULTI_INTR |
154 struct ocp_fs_i2c_data mpc85xx_i2c1_def = {
155 .flags = FS_I2C_SEPARATE_DFSRR,
158 /* ************************************************************************ */
160 mpc85xx_cds_show_cpuinfo(struct seq_file *m)
162 uint pvid, svid, phid1;
163 uint memsize = total_memory;
164 bd_t *binfo = (bd_t *) __res;
167 /* get the core frequency */
168 freq = binfo->bi_intfreq;
173 seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
174 seq_printf(m, "Machine\t\t: CDS (%x)\n", cadmus[CM_VER]);
175 seq_printf(m, "clock\t\t: %dMHz\n", freq / 1000000);
176 seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
177 seq_printf(m, "SVR\t\t: 0x%x\n", svid);
179 /* Display cpu Pll setting */
181 seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
183 /* Display the amount of memory */
184 seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
190 static void cpm2_cascade(int irq, void *dev_id, struct pt_regs *regs)
192 while((irq = cpm2_get_irq(regs)) >= 0)
196 static struct irqaction cpm2_irqaction = {
197 .handler = cpm2_cascade,
198 .flags = SA_INTERRUPT,
199 .mask = CPU_MASK_NONE,
200 .name = "cpm2_cascade",
202 #endif /* CONFIG_CPM2 */
205 mpc85xx_cds_init_IRQ(void)
207 bd_t *binfo = (bd_t *) __res;
209 volatile cpm2_map_t *immap = cpm2_immr;
213 /* Determine the Physical Address of the OpenPIC regs */
214 phys_addr_t OpenPIC_PAddr = binfo->bi_immr_base + MPC85xx_OPENPIC_OFFSET;
215 OpenPIC_Addr = ioremap(OpenPIC_PAddr, MPC85xx_OPENPIC_SIZE);
216 OpenPIC_InitSenses = mpc85xx_cds_openpic_initsenses;
217 OpenPIC_NumInitSenses = sizeof (mpc85xx_cds_openpic_initsenses);
219 /* Skip reserved space and internal sources */
220 openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200);
221 /* Map PIC IRQs 0-11 */
222 openpic_set_sources(32, 12, OpenPIC_Addr + 0x10000);
224 /* we let openpic interrupts starting from an offset, to
225 * leave space for cascading interrupts underneath.
227 openpic_init(MPC85xx_OPENPIC_IRQ_OFFSET);
230 /* disable all CPM interupts */
231 immap->im_intctl.ic_simrh = 0x0;
232 immap->im_intctl.ic_simrl = 0x0;
234 for (i = CPM_IRQ_OFFSET; i < (NR_CPM_INTS + CPM_IRQ_OFFSET); i++)
235 irq_desc[i].handler = &cpm2_pic;
237 /* Initialize the default interrupt mapping priorities,
238 * in case the boot rom changed something on us.
240 immap->im_intctl.ic_sicr = 0;
241 immap->im_intctl.ic_scprrh = 0x05309770;
242 immap->im_intctl.ic_scprrl = 0x05309770;
244 setup_irq(MPC85xx_IRQ_CPM, &cpm2_irqaction);
255 mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
257 struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
261 /* Handle PCI1 interrupts */
262 char pci_irq_table[][4] =
264 * PCI IDSEL/INTPIN->INTLINE
268 /* Note IRQ assignment for slots is based on which slot the elysium is
269 * in -- in this setup elysium is in slot #2 (this PIRQA as first
270 * interrupt on slot */
272 { 0, 1, 2, 3 }, /* 16 - PMC */
273 { 3, 0, 0, 0 }, /* 17 P2P (Tsi320) */
274 { 0, 1, 2, 3 }, /* 18 - Slot 1 */
275 { 1, 2, 3, 0 }, /* 19 - Slot 2 */
276 { 2, 3, 0, 1 }, /* 20 - Slot 3 */
277 { 3, 0, 1, 2 }, /* 21 - Slot 4 */
280 const long min_idsel = 16, max_idsel = 21, irqs_per_slot = 4;
283 for (i = 0; i < 6; i++)
284 for (j = 0; j < 4; j++)
285 pci_irq_table[i][j] =
286 ((pci_irq_table[i][j] + 5 -
287 cds_pci_slot) & 0x3) + PIRQ0A;
289 return PCI_IRQ_TABLE_LOOKUP;
291 /* Handle PCI2 interrupts (if we have one) */
292 char pci_irq_table[][4] =
295 * We only have one slot and one interrupt
296 * going to PIRQA - PIRQD */
297 { PIRQ1A, PIRQ1A, PIRQ1A, PIRQ1A }, /* 21 - slot 0 */
300 const long min_idsel = 21, max_idsel = 21, irqs_per_slot = 4;
302 return PCI_IRQ_TABLE_LOOKUP;
306 #define ARCADIA_HOST_BRIDGE_IDSEL 17
307 #define ARCADIA_2ND_BRIDGE_IDSEL 3
310 mpc85xx_exclude_device(u_char bus, u_char devfn)
312 if (bus == 0 && PCI_SLOT(devfn) == 0)
313 return PCIBIOS_DEVICE_NOT_FOUND;
314 #ifdef CONFIG_85xx_PCI2
315 /* With the current code we know PCI2 will be bus 2, however this may
316 * not be guarnteed */
317 if (bus == 2 && PCI_SLOT(devfn) == 0)
318 return PCIBIOS_DEVICE_NOT_FOUND;
320 /* We explicitly do not go past the Tundra 320 Bridge */
322 return PCIBIOS_DEVICE_NOT_FOUND;
323 if ((bus == 0) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
324 return PCIBIOS_DEVICE_NOT_FOUND;
326 return PCIBIOS_SUCCESSFUL;
328 #endif /* CONFIG_PCI */
330 /* ************************************************************************
332 * Setup the architecture
336 mpc85xx_cds_setup_arch(void)
339 struct ocp_gfar_data *einfo;
340 bd_t *binfo = (bd_t *) __res;
343 /* get the core frequency */
344 freq = binfo->bi_intfreq;
346 printk("mpc85xx_cds_setup_arch\n");
352 cadmus = ioremap(CADMUS_BASE, CADMUS_SIZE);
353 cds_pci_slot = ((cadmus[CM_CSR] >> 6) & 0x3) + 1;
354 printk("CDS Version = %x in PCI slot %d\n", cadmus[CM_VER], cds_pci_slot);
356 /* Set loops_per_jiffy to a half-way reasonable value,
357 for use until calibrate_delay gets called. */
358 loops_per_jiffy = freq / HZ;
361 /* setup PCI host bridges */
362 mpc85xx_setup_hose();
365 #ifdef CONFIG_SERIAL_8250
366 mpc85xx_early_serial_map();
369 #ifdef CONFIG_SERIAL_TEXT_DEBUG
370 /* Invalidate the entry we stole earlier the serial ports
371 * should be properly mapped */
372 invalidate_tlbcam_entry(NUM_TLBCAMS - 1);
375 def = ocp_get_one_device(OCP_VENDOR_FREESCALE, OCP_FUNC_GFAR, 0);
377 einfo = (struct ocp_gfar_data *) def->additions;
378 memcpy(einfo->mac_addr, binfo->bi_enetaddr, 6);
381 def = ocp_get_one_device(OCP_VENDOR_FREESCALE, OCP_FUNC_GFAR, 1);
383 einfo = (struct ocp_gfar_data *) def->additions;
384 memcpy(einfo->mac_addr, binfo->bi_enet1addr, 6);
387 #ifdef CONFIG_BLK_DEV_INITRD
389 ROOT_DEV = Root_RAM0;
392 #ifdef CONFIG_ROOT_NFS
395 ROOT_DEV = Root_HDA1;
398 ocp_for_each_device(mpc85xx_update_paddr_ocp, &(binfo->bi_immr_base));
401 /* ************************************************************************ */
403 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
404 unsigned long r6, unsigned long r7)
406 /* parse_bootinfo must always be called first */
407 parse_bootinfo(find_bootinfo());
410 * If we were passed in a board information, copy it into the
411 * residual data area.
414 memcpy((void *) __res, (void *) (r3 + KERNELBASE),
418 #ifdef CONFIG_SERIAL_TEXT_DEBUG
420 bd_t *binfo = (bd_t *) __res;
422 /* Use the last TLB entry to map CCSRBAR to allow access to DUART regs */
423 settlbcam(NUM_TLBCAMS - 1, binfo->bi_immr_base,
424 binfo->bi_immr_base, MPC85xx_CCSRBAR_SIZE, _PAGE_IO, 0);
429 #if defined(CONFIG_BLK_DEV_INITRD)
431 * If the init RAM disk has been configured in, and there's a valid
432 * starting address for it, set it up.
435 initrd_start = r4 + KERNELBASE;
436 initrd_end = r5 + KERNELBASE;
438 #endif /* CONFIG_BLK_DEV_INITRD */
440 /* Copy the kernel command line arguments to a safe place. */
443 *(char *) (r7 + KERNELBASE) = 0;
444 strcpy(cmd_line, (char *) (r6 + KERNELBASE));
447 /* setup the PowerPC module struct */
448 ppc_md.setup_arch = mpc85xx_cds_setup_arch;
449 ppc_md.show_cpuinfo = mpc85xx_cds_show_cpuinfo;
451 ppc_md.init_IRQ = mpc85xx_cds_init_IRQ;
452 ppc_md.get_irq = openpic_get_irq;
454 ppc_md.restart = mpc85xx_restart;
455 ppc_md.power_off = mpc85xx_power_off;
456 ppc_md.halt = mpc85xx_halt;
458 ppc_md.find_end_of_memory = mpc85xx_find_end_of_memory;
460 ppc_md.time_init = NULL;
461 ppc_md.set_rtc_time = NULL;
462 ppc_md.get_rtc_time = NULL;
463 ppc_md.calibrate_decr = mpc85xx_calibrate_decr;
465 #if defined(CONFIG_SERIAL_8250) && defined(CONFIG_SERIAL_TEXT_DEBUG)
466 ppc_md.progress = gen550_progress;
467 #endif /* CONFIG_SERIAL_8250 && CONFIG_SERIAL_TEXT_DEBUG */
470 ppc_md.progress("mpc85xx_cds_init(): exit", 0);