2 * arch/ppc/platforms/chestnut.h
4 * Definitions for IBM 750FXGX Eval (Chestnut)
6 * Author: <source@mvista.com>
8 * Based on Artesyn Katana code done by Tim Montgomery <timm@artesyncp.com>
9 * Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il
10 * Based on code done by Mark A. Greer <mgreer@mvista.com>
12 * <2004> (c) MontaVista Software, Inc. This file is licensed under
13 * the terms of the GNU General Public License version 2. This program
14 * is licensed "as is" without any warranty of any kind, whether express
19 * This is the CPU physical memory map (windows must be at least 1MB and start
20 * on a boundary that is a multiple of the window size):
22 * Seems on the IBM 750FXGX Eval board, the MV64460 Registers can be in
23 * only 2 places per switch U17 0x14000000 or 0xf1000000 easily - chose to
24 * implement at 0xf1000000 only at this time
26 * 0xfff00000-0xffffffff - 8 Flash
27 * 0xffd00000-0xffd00004 - CPLD
28 * 0xffc00000-0xffc0000f - UART
29 * 0xffb00000-0xffb07fff - FRAM
30 * 0xffa00000-0xffafffff - *** HOLE ***
31 * 0xff900000-0xff9fffff - MV64460 Integrated SRAM
32 * 0xfe000000-0xff8fffff - *** HOLE ***
33 * 0xfc000000-0xfdffffff - 32bit Flash
34 * 0xf1010000-0xfbffffff - *** HOLE ***
35 * 0xf1000000-0xf100ffff - MV64460 Registers
38 #ifndef __PPC_PLATFORMS_CHESTNUT_H__
39 #define __PPC_PLATFORMS_CHESTNUT_H__
41 #define CHESTNUT_BOOT_8BIT_BASE 0xfff00000
42 #define CHESTNUT_BOOT_8BIT_SIZE_ACTUAL (1024*1024)
43 #define CHESTNUT_BOOT_SRAM_BASE 0xffe00000
44 #define CHESTNUT_BOOT_SRAM_SIZE_ACTUAL (1024*1024)
45 #define CHESTNUT_CPLD_BASE 0xffd00000
46 #define CHESTNUT_CPLD_SIZE_ACTUAL 5
47 #define CHESTNUT_CPLD_REG3 (CHESTNUT_CPLD_BASE+3)
48 #define CHESTNUT_UART_BASE 0xffc00000
49 #define CHESTNUT_UART_SIZE_ACTUAL 16
50 #define CHESTNUT_FRAM_BASE 0xffb00000
51 #define CHESTNUT_FRAM_SIZE_ACTUAL (32*1024)
52 #define CHESTNUT_BRIDGE_REG_BASE 0xf1000000
53 #define CHESTNUT_INTERNAL_SRAM_BASE 0xff900000
54 #define CHESTNUT_INTERNAL_SRAM_SIZE_ACTUAL (256*1024)
55 #define CHESTNUT_32BIT_BASE 0xfc000000
56 #define CHESTNUT_32BIT_SIZE (32*1024*1024)
58 #define CHESTNUT_BOOT_8BIT_SIZE max(MV64360_WINDOW_SIZE_MIN, \
59 CHESTNUT_BOOT_8BIT_SIZE_ACTUAL)
60 #define CHESTNUT_BOOT_SRAM_SIZE max(MV64360_WINDOW_SIZE_MIN, \
61 CHESTNUT_BOOT_SRAM_SIZE_ACTUAL)
62 #define CHESTNUT_CPLD_SIZE max(MV64360_WINDOW_SIZE_MIN, \
63 CHESTNUT_CPLD_SIZE_ACTUAL)
64 #define CHESTNUT_UART_SIZE max(MV64360_WINDOW_SIZE_MIN, \
65 CHESTNUT_UART_SIZE_ACTUAL)
66 #define CHESTNUT_FRAM_SIZE max(MV64360_WINDOW_SIZE_MIN, \
67 CHESTNUT_FRAM_SIZE_ACTUAL)
68 #define CHESTNUT_INTERNAL_SRAM_SIZE max(MV64360_WINDOW_SIZE_MIN, \
69 CHESTNUT_INTERNAL_SRAM_SIZE_ACTUAL)
71 #define CHESTNUT_BUS_SPEED 200000000
72 #define CHESTNUT_PIBS_DATABASE 0xf0000 /* from PIBS src code */
74 #define MV64360_ETH_PORT_SERIAL_CONTROL_REG_PORT0 0x243c
75 #define MV64360_ETH_PORT_SERIAL_CONTROL_REG_PORT1 0x283c
81 #define CHESTNUT_PCI0_MEM_PROC_ADDR 0x80000000
82 #define CHESTNUT_PCI0_MEM_PCI_HI_ADDR 0x00000000
83 #define CHESTNUT_PCI0_MEM_PCI_LO_ADDR 0x80000000
84 #define CHESTNUT_PCI0_MEM_SIZE 0x10000000
85 #define CHESTNUT_PCI0_IO_PROC_ADDR 0xa0000000
86 #define CHESTNUT_PCI0_IO_PCI_ADDR 0x00000000
87 #define CHESTNUT_PCI0_IO_SIZE 0x01000000
90 * Board-specific IRQ info
92 #define CHESTNUT_PCI_SLOT0_IRQ 64+31
93 #define CHESTNUT_PCI_SLOT1_IRQ 64+30
94 #define CHESTNUT_PCI_SLOT2_IRQ 64+29
95 #define CHESTNUT_PCI_SLOT3_IRQ 64+28
97 /* serial port definitions */
98 #define CHESTNUT_UART0_IO_BASE CHESTNUT_UART_BASE+8
99 #define CHESTNUT_UART1_IO_BASE CHESTNUT_UART_BASE
101 #define UART0_INT 64+25
102 #define UART1_INT 64+26
104 #ifdef CONFIG_SERIAL_MANY_PORTS
105 #define RS_TABLE_SIZE 64
107 #define RS_TABLE_SIZE 2
110 /* Rate for the 3.6864 Mhz clock for the onboard serial chip */
111 #define BASE_BAUD ( 3686400 / 16 )
113 #ifdef CONFIG_SERIAL_DETECT_IRQ
114 #define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_SKIP_TEST|ASYNC_AUTO_IRQ)
116 #define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_SKIP_TEST)
119 #define STD_UART_OP(num) \
120 { 0, BASE_BAUD, 0, UART##num##_INT, STD_COM_FLAGS, \
121 iomem_base: (u8 *)CHESTNUT_UART##num##_IO_BASE, \
122 io_type: SERIAL_IO_MEM},
124 #define SERIAL_PORT_DFNS \
128 #endif /* __PPC_PLATFORMS_CHESTNUT_H__ */