arch/ppc/syslib/mv64x60_ocp.c

   1 /*
   2  * arch/ppc/syslib/mv64x60_ocp.c
   3  *
   4  * Common OCP definitions for the Marvell GT64260/MV64360/MV64460/...
   5  * line of host bridges.
   6  *
   7  * Author: Mark A. Greer <mgreer@mvista.com>
   8  *
   9  * 2004 (c) MontaVista, Software, Inc.  This file is licensed under
  10  * the terms of the GNU General Public License version 2.  This program
  11  * is licensed "as is" without any warranty of any kind, whether express
  12  * or implied.
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <asm/mv64x60.h>
  18 #include <asm/ocp.h>
  19
  20 static mv64x60_ocp_mpsc_data_t  mv64x60_ocp_mpsc0_def = {
  21         .mirror_regs            = 0,
  22         .cache_mgmt             = 0,
  23         .max_idle               = 0,
  24         .default_baud           = 9600,
  25         .default_bits           = 8,
  26         .default_parity         = 'n',
  27         .default_flow           = 'n',
  28         .chr_1_val              = 0x00000000,
  29         .chr_2_val              = 0x00000000,
  30         .chr_10_val             = 0x00000003,
  31         .mpcr_val               = 0,
  32         .mrr_val                = 0x3ffffe38,
  33         .rcrr_val               = 0,
  34         .tcrr_val               = 0,
  35         .intr_mask_val          = 0,
  36         .bcr_val                = 0,
  37         .sdma_irq               = MV64x60_IRQ_SDMA_0,
  38         .brg_can_tune           = 0,
  39         .brg_clk_src            = 8,            /* Default to TCLK */
  40         .brg_clk_freq           = 100000000,    /* Default to 100 MHz */
  41 };
  42 static mv64x60_ocp_mpsc_data_t  mv64x60_ocp_mpsc1_def = {
  43         .mirror_regs            = 0,
  44         .cache_mgmt             = 0,
  45         .max_idle               = 0,
  46         .default_baud           = 9600,
  47         .default_bits           = 8,
  48         .default_parity         = 'n',
  49         .default_flow           = 'n',
  50         .chr_1_val              = 0x00000000,
  51         .chr_1_val              = 0x00000000,
  52         .chr_2_val              = 0x00000000,
  53         .chr_10_val             = 0x00000003,
  54         .mpcr_val               = 0,
  55         .mrr_val                = 0x3ffffe38,
  56         .rcrr_val               = 0,
  57         .tcrr_val               = 0,
  58         .intr_mask_val          = 0,
  59         .bcr_val                = 0,
  60         .sdma_irq               = MV64x60_IRQ_SDMA_1,
  61         .brg_can_tune           = 0,
  62         .brg_clk_src            = 8,            /* Default to TCLK */
  63         .brg_clk_freq           = 100000000,    /* Default to 100 MHz */
  64 };
  65 MV64x60_OCP_SYSFS_MPSC_DATA()
  66
  67 struct ocp_def core_ocp[] = {
  68         /* Base address for the block of bridge's regs */
  69         { .vendor       = OCP_VENDOR_MARVELL,                   /* 0x00 */
  70           .function     = OCP_FUNC_HB,
  71           .index        = 0,
  72           .paddr        = 0,
  73           .pm           = OCP_CPM_NA,
  74         },
  75         /* 10/100 Ethernet controller */
  76         { .vendor       = OCP_VENDOR_MARVELL,                   /* 0x01 */
  77           .function     = OCP_FUNC_EMAC,
  78           .index        = 0,
  79           .paddr        = GT64260_ENET_0_OFFSET,
  80           .irq          = MV64x60_IRQ_ETH_0,
  81           .pm           = OCP_CPM_NA,
  82         },
  83         { .vendor       = OCP_VENDOR_MARVELL,                   /* 0x02 */
  84           .function     = OCP_FUNC_EMAC,
  85           .index        = 1,
  86           .paddr        = GT64260_ENET_1_OFFSET,
  87           .irq          = MV64x60_IRQ_ETH_1,
  88           .pm           = OCP_CPM_NA,
  89         },
  90         { .vendor       = OCP_VENDOR_MARVELL,                   /* 0x03 */
  91           .function     = OCP_FUNC_EMAC,
  92           .index        = 2,
  93           .paddr        = GT64260_ENET_2_OFFSET,
  94           .irq          = MV64x60_IRQ_ETH_2,
  95           .pm           = OCP_CPM_NA,
  96         },
  97         /* Multi-Protocol Serial Controller (MPSC) */
  98         { .vendor       = OCP_VENDOR_MARVELL,                   /* 0x04 */
  99           .function     = OCP_FUNC_MPSC,
 100           .index        = 0,
 101           .paddr        = MV64x60_MPSC_0_OFFSET,
 102           .irq          = MV64x60_IRQ_MPSC_0,
 103           .pm           = OCP_CPM_NA,
 104           .additions    = &mv64x60_ocp_mpsc0_def,
 105           .show         = &mv64x60_ocp_show_mpsc
 106         },
 107         { .vendor       = OCP_VENDOR_MARVELL,                   /* 0x05 */
 108           .function     = OCP_FUNC_MPSC,
 109           .index        = 1,
 110           .paddr        = MV64x60_MPSC_1_OFFSET,
 111           .irq          = MV64x60_IRQ_MPSC_1,
 112           .pm           = OCP_CPM_NA,
 113           .additions    = &mv64x60_ocp_mpsc1_def,
 114           .show         = &mv64x60_ocp_show_mpsc
 115         },
 116         /* Inter-Integrated Circuit Controller */
 117         { .vendor       = OCP_VENDOR_MARVELL,                   /* 0x06 */
 118           .function     = OCP_FUNC_I2C,
 119           .index        = 0,
 120           .paddr        = GT64260_I2C_OFFSET,
 121           .irq          = MV64x60_IRQ_I2C,
 122           .pm           = OCP_CPM_NA,
 123         },
 124         /* Programmable Interrupt Controller */
 125         { .vendor       = OCP_VENDOR_MARVELL,                   /* 0x07 */
 126           .function     = OCP_FUNC_PIC,
 127           .index        = 0,
 128           .paddr        = GT64260_IC_OFFSET,
 129           .pm           = OCP_CPM_NA,
 130         },
 131         { .vendor       = OCP_VENDOR_INVALID
 132         }
 133 };