2 * arch/ppc/syslib/ppc85xx_setup.c
4 * MPC85XX common board code
6 * Maintainer: Kumar Gala <kumar.gala@freescale.com>
8 * Copyright 2004 Freescale Semiconductor Inc.
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
16 #include <linux/config.h>
17 #include <linux/types.h>
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/pci.h>
21 #include <linux/serial.h>
22 #include <linux/tty.h> /* for linux/serial_core.h */
23 #include <linux/serial_core.h>
27 #include <asm/mpc85xx.h>
28 #include <asm/immap_85xx.h>
33 #include <syslib/ppc85xx_setup.h>
35 /* Return the amount of memory */
37 mpc85xx_find_end_of_memory(void)
41 binfo = (bd_t *) __res;
43 return binfo->bi_memsize;
46 /* The decrementer counts at the system (internal) clock freq divided by 8 */
48 mpc85xx_calibrate_decr(void)
50 bd_t *binfo = (bd_t *) __res;
51 unsigned int freq, divisor;
53 /* get the core frequency */
54 freq = binfo->bi_busfreq;
56 /* The timebase is updated every 8 bus clocks, HID0[SEL_TBCLK] = 0 */
58 tb_ticks_per_jiffy = freq / divisor / HZ;
59 tb_to_us = mulhwu_scale_factor(freq / divisor, 1000000);
61 /* Set the time base to zero */
65 /* Clear any pending timer interrupts */
66 mtspr(SPRN_TSR, TSR_ENW | TSR_WIS | TSR_DIS | TSR_FIS);
68 /* Enable decrementer interrupt */
69 mtspr(SPRN_TCR, TCR_DIE);
72 #ifdef CONFIG_SERIAL_8250
74 mpc85xx_early_serial_map(void)
76 struct uart_port serial_req;
77 bd_t *binfo = (bd_t *) __res;
78 phys_addr_t duart_paddr = binfo->bi_immr_base + MPC85xx_UART0_OFFSET;
80 /* Setup serial port access */
81 memset(&serial_req, 0, sizeof (serial_req));
82 serial_req.uartclk = binfo->bi_busfreq;
84 serial_req.irq = MPC85xx_IRQ_DUART;
85 serial_req.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
86 serial_req.iotype = SERIAL_IO_MEM;
87 serial_req.membase = ioremap(duart_paddr, MPC85xx_UART0_SIZE);
88 serial_req.mapbase = duart_paddr;
89 serial_req.regshift = 0;
91 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
92 gen550_init(0, &serial_req);
95 if (early_serial_setup(&serial_req) != 0)
96 printk("Early serial init of port 0 failed\n");
98 /* Assume early_serial_setup() doesn't modify serial_req */
99 duart_paddr = binfo->bi_immr_base + MPC85xx_UART1_OFFSET;
101 serial_req.mapbase = duart_paddr;
102 serial_req.membase = ioremap(duart_paddr, MPC85xx_UART1_SIZE);
104 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
105 gen550_init(1, &serial_req);
108 if (early_serial_setup(&serial_req) != 0)
109 printk("Early serial init of port 1 failed\n");
114 mpc85xx_restart(char *cmd)
121 mpc85xx_power_off(void)
136 mpc85xx_setup_pci1(struct pci_controller *hose)
138 volatile struct ccsr_pci *pci;
139 volatile struct ccsr_guts *guts;
140 unsigned short temps;
141 bd_t *binfo = (bd_t *) __res;
143 pci = ioremap(binfo->bi_immr_base + MPC85xx_PCI1_OFFSET,
146 guts = ioremap(binfo->bi_immr_base + MPC85xx_GUTS_OFFSET,
149 early_read_config_word(hose, 0, 0, PCI_COMMAND, &temps);
150 temps |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
151 early_write_config_word(hose, 0, 0, PCI_COMMAND, temps);
153 #define PORDEVSR_PCI (0x00800000) /* PCI Mode */
154 if (guts->pordevsr & PORDEVSR_PCI) {
155 early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
158 temps = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
159 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
160 early_write_config_word(hose, 0, 0, PCIX_COMMAND, temps);
163 /* Disable all windows (except powar0 since its ignored) */
172 /* Setup Phys:PCI 1:1 outbound mem window @ MPC85XX_PCI1_LOWER_MEM */
173 pci->potar1 = (MPC85XX_PCI1_LOWER_MEM >> 12) & 0x000fffff;
174 pci->potear1 = 0x00000000;
175 pci->powbar1 = (MPC85XX_PCI1_LOWER_MEM >> 12) & 0x000fffff;
176 /* Enable, Mem R/W */
177 pci->powar1 = 0x80044000 |
178 (__ilog2(MPC85XX_PCI1_UPPER_MEM - MPC85XX_PCI1_LOWER_MEM + 1) - 1);
180 /* Setup outboud IO windows @ MPC85XX_PCI1_IO_BASE */
181 pci->potar2 = 0x00000000;
182 pci->potear2 = 0x00000000;
183 pci->powbar2 = (MPC85XX_PCI1_IO_BASE >> 12) & 0x000fffff;
185 pci->powar2 = 0x80088000 | (__ilog2(MPC85XX_PCI1_IO_SIZE) - 1);
187 /* Setup 2G inbound Memory Window @ 0 */
188 pci->pitar1 = 0x00000000;
189 pci->piwbar1 = 0x00000000;
190 pci->piwar1 = 0xa0f5501e; /* Enable, Prefetch, Local
191 Mem, Snoop R/W, 2G */
195 extern int mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin);
196 extern int mpc85xx_exclude_device(u_char bus, u_char devfn);
198 #ifdef CONFIG_85xx_PCI2
200 mpc85xx_setup_pci2(struct pci_controller *hose)
202 volatile struct ccsr_pci *pci;
203 unsigned short temps;
204 bd_t *binfo = (bd_t *) __res;
206 pci = ioremap(binfo->bi_immr_base + MPC85xx_PCI2_OFFSET,
209 early_read_config_word(hose, hose->bus_offset, 0, PCI_COMMAND, &temps);
210 temps |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
211 early_write_config_word(hose, hose->bus_offset, 0, PCI_COMMAND, temps);
212 early_write_config_byte(hose, hose->bus_offset, 0, PCI_LATENCY_TIMER, 0x80);
214 /* Disable all windows (except powar0 since its ignored) */
223 /* Setup Phys:PCI 1:1 outbound mem window @ MPC85XX_PCI2_LOWER_MEM */
224 pci->potar1 = (MPC85XX_PCI2_LOWER_MEM >> 12) & 0x000fffff;
225 pci->potear1 = 0x00000000;
226 pci->powbar1 = (MPC85XX_PCI2_LOWER_MEM >> 12) & 0x000fffff;
227 /* Enable, Mem R/W */
228 pci->powar1 = 0x80044000 |
229 (__ilog2(MPC85XX_PCI1_UPPER_MEM - MPC85XX_PCI1_LOWER_MEM + 1) - 1);
231 /* Setup outboud IO windows @ MPC85XX_PCI2_IO_BASE */
232 pci->potar2 = 0x00000000;
233 pci->potear2 = 0x00000000;
234 pci->powbar2 = (MPC85XX_PCI2_IO_BASE >> 12) & 0x000fffff;
236 pci->powar2 = 0x80088000 | (__ilog2(MPC85XX_PCI1_IO_SIZE) - 1);
238 /* Setup 2G inbound Memory Window @ 0 */
239 pci->pitar1 = 0x00000000;
240 pci->piwbar1 = 0x00000000;
241 pci->piwar1 = 0xa0f5501e; /* Enable, Prefetch, Local
242 Mem, Snoop R/W, 2G */
244 #endif /* CONFIG_85xx_PCI2 */
247 mpc85xx_setup_hose(void)
249 struct pci_controller *hose_a;
250 #ifdef CONFIG_85xx_PCI2
251 struct pci_controller *hose_b;
253 bd_t *binfo = (bd_t *) __res;
255 hose_a = pcibios_alloc_controller();
260 ppc_md.pci_swizzle = common_swizzle;
261 ppc_md.pci_map_irq = mpc85xx_map_irq;
263 hose_a->first_busno = 0;
264 hose_a->bus_offset = 0;
265 hose_a->last_busno = 0xff;
267 setup_indirect_pci(hose_a, binfo->bi_immr_base + PCI1_CFG_ADDR_OFFSET,
268 binfo->bi_immr_base + PCI1_CFG_DATA_OFFSET);
269 hose_a->set_cfg_type = 1;
271 mpc85xx_setup_pci1(hose_a);
273 hose_a->pci_mem_offset = MPC85XX_PCI1_MEM_OFFSET;
274 hose_a->mem_space.start = MPC85XX_PCI1_LOWER_MEM;
275 hose_a->mem_space.end = MPC85XX_PCI1_UPPER_MEM;
277 hose_a->io_space.start = MPC85XX_PCI1_LOWER_IO;
278 hose_a->io_space.end = MPC85XX_PCI1_UPPER_IO;
279 hose_a->io_base_phys = MPC85XX_PCI1_IO_BASE;
280 #ifdef CONFIG_85xx_PCI2
282 (unsigned long) ioremap(MPC85XX_PCI1_IO_BASE,
283 MPC85XX_PCI1_IO_SIZE +
284 MPC85XX_PCI2_IO_SIZE);
287 (unsigned long) ioremap(MPC85XX_PCI1_IO_BASE,
288 MPC85XX_PCI1_IO_SIZE);
290 hose_a->io_base_virt = (void *) isa_io_base;
292 /* setup resources */
293 pci_init_resource(&hose_a->mem_resources[0],
294 MPC85XX_PCI1_LOWER_MEM,
295 MPC85XX_PCI1_UPPER_MEM,
296 IORESOURCE_MEM, "PCI1 host bridge");
298 pci_init_resource(&hose_a->io_resource,
299 MPC85XX_PCI1_LOWER_IO,
300 MPC85XX_PCI1_UPPER_IO,
301 IORESOURCE_IO, "PCI1 host bridge");
303 ppc_md.pci_exclude_device = mpc85xx_exclude_device;
305 hose_a->last_busno = pciauto_bus_scan(hose_a, hose_a->first_busno);
307 #ifdef CONFIG_85xx_PCI2
308 hose_b = pcibios_alloc_controller();
313 hose_b->bus_offset = hose_a->last_busno + 1;
314 hose_b->first_busno = hose_a->last_busno + 1;
315 hose_b->last_busno = 0xff;
317 setup_indirect_pci(hose_b, binfo->bi_immr_base + PCI2_CFG_ADDR_OFFSET,
318 binfo->bi_immr_base + PCI2_CFG_DATA_OFFSET);
319 hose_b->set_cfg_type = 1;
321 mpc85xx_setup_pci2(hose_b);
323 hose_b->pci_mem_offset = MPC85XX_PCI2_MEM_OFFSET;
324 hose_b->mem_space.start = MPC85XX_PCI2_LOWER_MEM;
325 hose_b->mem_space.end = MPC85XX_PCI2_UPPER_MEM;
327 hose_b->io_space.start = MPC85XX_PCI2_LOWER_IO;
328 hose_b->io_space.end = MPC85XX_PCI2_UPPER_IO;
329 hose_b->io_base_phys = MPC85XX_PCI2_IO_BASE;
330 hose_b->io_base_virt = (void *) isa_io_base + MPC85XX_PCI1_IO_SIZE;
332 /* setup resources */
333 pci_init_resource(&hose_b->mem_resources[0],
334 MPC85XX_PCI2_LOWER_MEM,
335 MPC85XX_PCI2_UPPER_MEM,
336 IORESOURCE_MEM, "PCI2 host bridge");
338 pci_init_resource(&hose_b->io_resource,
339 MPC85XX_PCI2_LOWER_IO,
340 MPC85XX_PCI2_UPPER_IO,
341 IORESOURCE_IO, "PCI2 host bridge");
343 hose_b->last_busno = pciauto_bus_scan(hose_b, hose_b->first_busno);
347 #endif /* CONFIG_PCI */