2 * Copyright 2001 Mike Corrigan, IBM Corp
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
9 #include <linux/config.h>
10 #include <linux/types.h>
11 #include <linux/threads.h>
12 #include <linux/module.h>
13 #include <linux/bitops.h>
14 #include <asm/processor.h>
15 #include <asm/ptrace.h>
17 #include <asm/abs_addr.h>
18 #include <asm/iSeries/ItLpNaca.h>
19 #include <asm/iSeries/ItLpPaca.h>
20 #include <asm/iSeries/ItLpRegSave.h>
22 #include <asm/iSeries/HvReleaseData.h>
23 #include <asm/iSeries/LparMap.h>
24 #include <asm/iSeries/ItVpdAreas.h>
25 #include <asm/iSeries/ItIplParmsReal.h>
26 #include <asm/iSeries/ItExtVpdPanel.h>
27 #include <asm/iSeries/ItLpQueue.h>
28 #include <asm/iSeries/IoHriProcessorVpd.h>
29 #include <asm/iSeries/ItSpCommArea.h>
31 /* The LpQueue is used to pass event data from the hypervisor to
32 * the partition. This is where I/O interrupt events are communicated.
35 /* May be filled in by the hypervisor so cannot end up in the BSS */
36 struct ItLpQueue xItLpQueue __attribute__((__section__(".data")));
39 /* The HvReleaseData is the root of the information shared between
40 * the hypervisor and Linux.
43 struct HvReleaseData hvReleaseData = {
44 0xc8a5d9c4, /* desc = "HvRD" ebcdic */
45 sizeof(struct HvReleaseData),
46 offsetof(struct naca_struct, xItVpdAreas),
47 (struct naca_struct *)(NACA_VIRT_ADDR), /* 64-bit Naca address */
48 0x6000, /* offset of LparMap within loadarea (see head.S) */
50 1, /* tags inactive */
52 0, /* shared processors */
54 6, /* TEMP: This allows non-GA driver */
55 4, /* We are v5r2m0 */
56 3, /* Min supported PLIC = v5r1m0 */
57 3, /* Min usable PLIC = v5r1m0 */
58 { 0xd3, 0x89, 0x95, 0xa4, /* "Linux 2.4 "*/
59 0xa7, 0x40, 0xf2, 0x4b,
60 0xf4, 0x4b, 0xf6, 0xf4 },
64 extern void SystemReset_Iseries(void);
65 extern void MachineCheck_Iseries(void);
66 extern void DataAccess_Iseries(void);
67 extern void InstructionAccess_Iseries(void);
68 extern void HardwareInterrupt_Iseries(void);
69 extern void Alignment_Iseries(void);
70 extern void ProgramCheck_Iseries(void);
71 extern void FPUnavailable_Iseries(void);
72 extern void Decrementer_Iseries(void);
73 extern void Trap_0a_Iseries(void);
74 extern void Trap_0b_Iseries(void);
75 extern void SystemCall_Iseries(void);
76 extern void SingleStep_Iseries(void);
77 extern void Trap_0e_Iseries(void);
78 extern void PerformanceMonitor_Iseries(void);
79 extern void DataAccessSLB_Iseries(void);
80 extern void InstructionAccessSLB_Iseries(void);
82 struct ItLpNaca itLpNaca = {
83 0xd397d581, /* desc = "LpNa" ebcdic */
84 0x0400, /* size of ItLpNaca */
85 0x0300, 19, /* offset to int array, # ents */
86 0, 0, 0, /* Part # of primary, serv, me */
87 0, 0x100, /* # of LP queues, offset */
88 0, 0, 0, /* Piranha stuff */
89 { 0,0,0,0,0 }, /* reserved */
90 0,0,0,0,0,0,0, /* stuff */
91 { 0,0,0,0,0 }, /* reserved */
93 0, /* VRM index of PLIC */
94 0, 0, /* min supported, compat SLIC */
95 0, /* 64-bit addr of load area */
96 0, /* chunks for load area */
97 0, 0, /* PASE mask, seg table */
98 { 0 }, /* 64 reserved bytes */
99 { 0 }, /* 128 reserved bytes */
100 { 0 }, /* Old LP Queue */
101 { 0 }, /* 384 reserved bytes */
103 (u64)SystemReset_Iseries, /* 0x100 System Reset */
104 (u64)MachineCheck_Iseries, /* 0x200 Machine Check */
105 (u64)DataAccess_Iseries, /* 0x300 Data Access */
106 (u64)InstructionAccess_Iseries, /* 0x400 Instruction Access */
107 (u64)HardwareInterrupt_Iseries, /* 0x500 External */
108 (u64)Alignment_Iseries, /* 0x600 Alignment */
109 (u64)ProgramCheck_Iseries, /* 0x700 Program Check */
110 (u64)FPUnavailable_Iseries, /* 0x800 FP Unavailable */
111 (u64)Decrementer_Iseries, /* 0x900 Decrementer */
112 (u64)Trap_0a_Iseries, /* 0xa00 Trap 0A */
113 (u64)Trap_0b_Iseries, /* 0xb00 Trap 0B */
114 (u64)SystemCall_Iseries, /* 0xc00 System Call */
115 (u64)SingleStep_Iseries, /* 0xd00 Single Step */
116 (u64)Trap_0e_Iseries, /* 0xe00 Trap 0E */
117 (u64)PerformanceMonitor_Iseries,/* 0xf00 Performance Monitor */
120 0, /* int 0x1020 CPU ctls */
121 (u64)HardwareInterrupt_Iseries, /* SC Ret Hdlr */
122 (u64)DataAccessSLB_Iseries, /* 0x380 D-SLB */
123 (u64)InstructionAccessSLB_Iseries /* 0x480 I-SLB */
126 EXPORT_SYMBOL(itLpNaca);
128 /* May be filled in by the hypervisor so cannot end up in the BSS */
129 struct ItIplParmsReal xItIplParmsReal __attribute__((__section__(".data")));
131 /* May be filled in by the hypervisor so cannot end up in the BSS */
132 struct ItExtVpdPanel xItExtVpdPanel __attribute__((__section__(".data")));
133 EXPORT_SYMBOL(xItExtVpdPanel);
135 #define maxPhysicalProcessors 32
137 struct IoHriProcessorVpd xIoHriProcessorVpd[maxPhysicalProcessors] = {
139 .xInstCacheOperandSize = 32,
140 .xDataCacheOperandSize = 32,
141 .xProcFreq = 50000000,
142 .xTimeBaseFreq = 50000000,
147 /* Space for Main Store Vpd 27,200 bytes */
148 /* May be filled in by the hypervisor so cannot end up in the BSS */
149 u64 xMsVpd[3400] __attribute__((__section__(".data")));
151 /* Space for Recovery Log Buffer */
152 /* May be filled in by the hypervisor so cannot end up in the BSS */
153 u64 xRecoveryLogBuffer[32] __attribute__((__section__(".data")));
155 struct SpCommArea xSpCommArea = {
162 /* The LparMap data is now located at offset 0x6000 in head.S
163 * It was put there so that the HvReleaseData could address it
164 * with a 32-bit offset as required by the iSeries hypervisor
166 * The Naca has a pointer to the ItVpdAreas. The hypervisor finds
167 * the Naca via the HvReleaseData area. The HvReleaseData has the
168 * offset into the Naca of the pointer to the ItVpdAreas.
170 struct ItVpdAreas itVpdAreas = {
171 0xc9a3e5c1, /* "ItVA" */
172 sizeof( struct ItVpdAreas ),
174 26, /* # VPD array entries */
175 10, /* # DMA array entries */
176 NR_CPUS*2, maxPhysicalProcessors, /* Max logical, physical procs */
177 offsetof(struct ItVpdAreas,xPlicDmaToks),/* offset to DMA toks */
178 offsetof(struct ItVpdAreas,xSlicVpdAdrs),/* offset to VPD addrs */
179 offsetof(struct ItVpdAreas,xPlicDmaLens),/* offset to DMA lens */
180 offsetof(struct ItVpdAreas,xSlicVpdLens),/* offset to VPD lens */
181 0, /* max slot labels */
182 1, /* max LP queues */
183 {0}, {0}, /* reserved */
184 {0}, /* DMA lengths */
185 {0}, /* DMA tokens */
188 sizeof(xItExtVpdPanel), /* 3 Extended VPD */
189 sizeof(struct paca_struct), /* 4 length of Paca */
191 sizeof(struct ItIplParmsReal),/* 6 length of IPL parms */
192 26992, /* 7 length of MS VPD */
194 sizeof(struct ItLpNaca),/* 9 length of LP Naca */
196 256, /* 11 length of Recovery Log Buf */
197 sizeof(struct SpCommArea), /* 12 length of SP Comm Area */
199 sizeof(struct IoHriProcessorVpd),/* 16 length of Proc Vpd */
200 0,0,0,0,0,0, /* 17 - 22 */
201 sizeof(struct ItLpQueue),/* 23 length of Lp Queue */
204 { /* VPD addresses */
206 &xItExtVpdPanel, /* 3 Extended VPD */
207 &paca[0], /* 4 first Paca */
209 &xItIplParmsReal, /* 6 IPL parms */
210 &xMsVpd, /* 7 MS Vpd */
212 &itLpNaca, /* 9 LpNaca */
214 &xRecoveryLogBuffer, /* 11 Recovery Log Buffer */
215 &xSpCommArea, /* 12 SP Comm Area */
217 &xIoHriProcessorVpd, /* 16 Proc Vpd */
218 0,0,0,0,0,0, /* 17 - 22 */
219 &xItLpQueue, /* 23 Lp Queue */
224 struct msChunks msChunks;
226 /* Depending on whether this is called from iSeries or pSeries setup
227 * code, the location of the msChunks struct may or may not have
228 * to be reloc'd, so we force the caller to do that for us by passing
229 * in a pointer to the structure.
232 msChunks_alloc(unsigned long mem, unsigned long num_chunks, unsigned long chunk_size)
234 unsigned long offset = reloc_offset();
235 struct msChunks *_msChunks = PTRRELOC(&msChunks);
237 _msChunks->num_chunks = num_chunks;
238 _msChunks->chunk_size = chunk_size;
239 _msChunks->chunk_shift = __ilog2(chunk_size);
240 _msChunks->chunk_mask = (1UL<<_msChunks->chunk_shift)-1;
242 mem = _ALIGN(mem, sizeof(msChunks_entry));
243 _msChunks->abs = (msChunks_entry *)(mem + offset);
244 mem += num_chunks * sizeof(msChunks_entry);