arch/ppc64/kernel/pSeries_iommu.c

   1 /*
   2  * arch/ppc64/kernel/pSeries_iommu.c
   3  *
   4  * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
   5  *
   6  * Rewrite, cleanup:
   7  *
   8  * Copyright (C) 2004 Olof Johansson <olof@austin.ibm.com>, IBM Corporation
   9  *
  10  * Dynamic DMA mapping support, pSeries-specific parts, both SMP and LPAR.
  11  *
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License as published by
  15  * the Free Software Foundation; either version 2 of the License, or
  16  * (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  26  */
  27
  28 #include <linux/config.h>
  29 #include <linux/init.h>
  30 #include <linux/types.h>
  31 #include <linux/slab.h>
  32 #include <linux/mm.h>
  33 #include <linux/spinlock.h>
  34 #include <linux/string.h>
  35 #include <linux/pci.h>
  36 #include <linux/dma-mapping.h>
  37 #include <asm/io.h>
  38 #include <asm/prom.h>
  39 #include <asm/rtas.h>
  40 #include <asm/ppcdebug.h>
  41 #include <asm/iommu.h>
  42 #include <asm/pci-bridge.h>
  43 #include <asm/machdep.h>
  44 #include <asm/abs_addr.h>
  45 #include <asm/plpar_wrappers.h>
  46 #include "pci.h"
  47
  48
  49 static void tce_build_pSeries(struct iommu_table *tbl, long index,
  50                               long npages, unsigned long uaddr,
  51                               enum dma_data_direction direction)
  52 {
  53         union tce_entry t;
  54         union tce_entry *tp;
  55
  56         t.te_word = 0;
  57         t.te_rdwr = 1; // Read allowed
  58
  59         if (direction != DMA_TO_DEVICE)
  60                 t.te_pciwr = 1;
  61
  62         tp = ((union tce_entry *)tbl->it_base) + index;
  63
  64         while (npages--) {
  65                 /* can't move this out since we might cross LMB boundary */
  66                 t.te_rpn = (virt_to_abs(uaddr)) >> PAGE_SHIFT;
  67
  68                 tp->te_word = t.te_word;
  69
  70                 uaddr += PAGE_SIZE;
  71                 tp++;
  72         }
  73 }
  74
  75
  76 static void tce_free_pSeries(struct iommu_table *tbl, long index, long npages)
  77 {
  78         union tce_entry t;
  79         union tce_entry *tp;
  80
  81         t.te_word = 0;
  82         tp  = ((union tce_entry *)tbl->it_base) + index;
  83
  84         while (npages--) {
  85                 tp->te_word = t.te_word;
  86
  87                 tp++;
  88         }
  89 }
  90
  91
  92 static void tce_build_pSeriesLP(struct iommu_table *tbl, long tcenum,
  93                                 long npages, unsigned long uaddr,
  94                                 enum dma_data_direction direction)
  95 {
  96         u64 rc;
  97         union tce_entry tce;
  98
  99         tce.te_word = 0;
 100         tce.te_rpn = (virt_to_abs(uaddr)) >> PAGE_SHIFT;
 101         tce.te_rdwr = 1;
 102         if (direction != DMA_TO_DEVICE)
 103                 tce.te_pciwr = 1;
 104
 105         while (npages--) {
 106                 rc = plpar_tce_put((u64)tbl->it_index,
 107                                    (u64)tcenum << 12,
 108                                    tce.te_word );
 109
 110                 if (rc && printk_ratelimit()) {
 111                         printk("tce_build_pSeriesLP: plpar_tce_put failed. rc=%ld\n", rc);
 112                         printk("\tindex   = 0x%lx\n", (u64)tbl->it_index);
 113                         printk("\ttcenum  = 0x%lx\n", (u64)tcenum);
 114                         printk("\ttce val = 0x%lx\n", tce.te_word );
 115                         show_stack(current, (unsigned long *)__get_SP());
 116                 }
 117
 118                 tcenum++;
 119                 tce.te_rpn++;
 120         }
 121 }
 122
 123 DEFINE_PER_CPU(void *, tce_page) = NULL;
 124
 125 static void tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum,
 126                                      long npages, unsigned long uaddr,
 127                                      enum dma_data_direction direction)
 128 {
 129         u64 rc;
 130         union tce_entry tce, *tcep;
 131         long l, limit;
 132
 133         if (npages == 1)
 134                 return tce_build_pSeriesLP(tbl, tcenum, npages, uaddr,
 135                                            direction);
 136
 137         tcep = __get_cpu_var(tce_page);
 138
 139         /* This is safe to do since interrupts are off when we're called
 140          * from iommu_alloc{,_sg}()
 141          */
 142         if (!tcep) {
 143                 tcep = (void *)__get_free_page(GFP_ATOMIC);
 144                 /* If allocation fails, fall back to the loop implementation */
 145                 if (!tcep)
 146                         return tce_build_pSeriesLP(tbl, tcenum, npages,
 147                                                    uaddr, direction);
 148                 __get_cpu_var(tce_page) = tcep;
 149         }
 150
 151         tce.te_word = 0;
 152         tce.te_rpn = (virt_to_abs(uaddr)) >> PAGE_SHIFT;
 153         tce.te_rdwr = 1;
 154         if (direction != DMA_TO_DEVICE)
 155                 tce.te_pciwr = 1;
 156
 157         /* We can map max one pageful of TCEs at a time */
 158         do {
 159                 /*
 160                  * Set up the page with TCE data, looping through and setting
 161                  * the values.
 162                  */
 163                 limit = min_t(long, npages, PAGE_SIZE/sizeof(union tce_entry));
 164
 165                 for (l = 0; l < limit; l++) {
 166                         tcep[l] = tce;
 167                         tce.te_rpn++;
 168                 }
 169
 170                 rc = plpar_tce_put_indirect((u64)tbl->it_index,
 171                                             (u64)tcenum << 12,
 172                                             (u64)virt_to_abs(tcep),
 173                                             limit);
 174
 175                 npages -= limit;
 176                 tcenum += limit;
 177         } while (npages > 0 && !rc);
 178
 179         if (rc && printk_ratelimit()) {
 180                 printk("tce_buildmulti_pSeriesLP: plpar_tce_put failed. rc=%ld\n", rc);
 181                 printk("\tindex   = 0x%lx\n", (u64)tbl->it_index);
 182                 printk("\tnpages  = 0x%lx\n", (u64)npages);
 183                 printk("\ttce[0] val = 0x%lx\n", tcep[0].te_word);
 184                 show_stack(current, (unsigned long *)__get_SP());
 185         }
 186 }
 187
 188 static void tce_free_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages)
 189 {
 190         u64 rc;
 191         union tce_entry tce;
 192
 193         tce.te_word = 0;
 194
 195         while (npages--) {
 196                 rc = plpar_tce_put((u64)tbl->it_index,
 197                                    (u64)tcenum << 12,
 198                                    tce.te_word);
 199
 200                 if (rc && printk_ratelimit()) {
 201                         printk("tce_free_pSeriesLP: plpar_tce_put failed. rc=%ld\n", rc);
 202                         printk("\tindex   = 0x%lx\n", (u64)tbl->it_index);
 203                         printk("\ttcenum  = 0x%lx\n", (u64)tcenum);
 204                         printk("\ttce val = 0x%lx\n", tce.te_word );
 205                         show_stack(current, (unsigned long *)__get_SP());
 206                 }
 207
 208                 tcenum++;
 209         }
 210 }
 211
 212
 213 static void tce_freemulti_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages)
 214 {
 215         u64 rc;
 216         union tce_entry tce;
 217
 218         tce.te_word = 0;
 219
 220         rc = plpar_tce_stuff((u64)tbl->it_index,
 221                            (u64)tcenum << 12,
 222                            tce.te_word,
 223                            npages);
 224
 225         if (rc && printk_ratelimit()) {
 226                 printk("tce_freemulti_pSeriesLP: plpar_tce_stuff failed\n");
 227                 printk("\trc      = %ld\n", rc);
 228                 printk("\tindex   = 0x%lx\n", (u64)tbl->it_index);
 229                 printk("\tnpages  = 0x%lx\n", (u64)npages);
 230                 printk("\ttce val = 0x%lx\n", tce.te_word );
 231                 show_stack(current, (unsigned long *)__get_SP());
 232         }
 233 }
 234
 235
 236 static void iommu_buses_init(void)
 237 {
 238         struct pci_controller *phb, *tmp;
 239         struct device_node *dn, *first_dn;
 240         int num_slots, num_slots_ilog2;
 241         int first_phb = 1;
 242         unsigned long tcetable_ilog2;
 243
 244         /*
 245          * We default to a TCE table that maps 2GB (4MB table, 22 bits),
 246          * however some machines have a 3GB IO hole and for these we
 247          * create a table that maps 1GB (2MB table, 21 bits)
 248          */
 249         if (io_hole_start < 0x80000000UL)
 250                 tcetable_ilog2 = 21;
 251         else
 252                 tcetable_ilog2 = 22;
 253
 254         /* XXX Should we be using pci_root_buses instead?  -ojn
 255          */
 256
 257         list_for_each_entry_safe(phb, tmp, &hose_list, list_node) {
 258                 first_dn = ((struct device_node *)phb->arch_data)->child;
 259
 260                 /* Carve 2GB into the largest dma_window_size possible */
 261                 for (dn = first_dn, num_slots = 0; dn != NULL; dn = dn->sibling)
 262                         num_slots++;
 263                 num_slots_ilog2 = __ilog2(num_slots);
 264
 265                 if ((1<<num_slots_ilog2) != num_slots)
 266                         num_slots_ilog2++;
 267
 268                 phb->dma_window_size = 1 << (tcetable_ilog2 - num_slots_ilog2);
 269
 270                 /* Reserve 16MB of DMA space on the first PHB.
 271                  * We should probably be more careful and use firmware props.
 272                  * In reality this space is remapped, not lost.  But we don't
 273                  * want to get that smart to handle it -- too much work.
 274                  */
 275                 phb->dma_window_base_cur = first_phb ? (1 << 12) : 0;
 276                 first_phb = 0;
 277
 278                 for (dn = first_dn; dn != NULL; dn = dn->sibling)
 279                         iommu_devnode_init_pSeries(dn);
 280         }
 281 }
 282
 283
 284 static void iommu_buses_init_lpar(struct list_head *bus_list)
 285 {
 286         struct list_head *ln;
 287         struct pci_bus *bus;
 288         struct device_node *busdn;
 289         unsigned int *dma_window;
 290
 291         for (ln=bus_list->next; ln != bus_list; ln=ln->next) {
 292                 bus = pci_bus_b(ln);
 293
 294                 if (bus->self)
 295                         busdn = pci_device_to_OF_node(bus->self);
 296                 else
 297                         busdn = bus->sysdata;   /* must be a phb */
 298
 299                 dma_window = (unsigned int *)get_property(busdn, "ibm,dma-window", NULL);
 300                 if (dma_window) {
 301                         /* Bussubno hasn't been copied yet.
 302                          * Do it now because iommu_table_setparms_lpar needs it.
 303                          */
 304                         busdn->bussubno = bus->number;
 305                         iommu_devnode_init_pSeries(busdn);
 306                 }
 307
 308                 /* look for a window on a bridge even if the PHB had one */
 309                 iommu_buses_init_lpar(&bus->children);
 310         }
 311 }
 312
 313
 314 static void iommu_table_setparms(struct pci_controller *phb,
 315                                  struct device_node *dn,
 316                                  struct iommu_table *tbl)
 317 {
 318         struct device_node *node;
 319         unsigned long *basep;
 320         unsigned int *sizep;
 321
 322         node = (struct device_node *)phb->arch_data;
 323
 324         basep = (unsigned long *)get_property(node, "linux,tce-base", NULL);
 325         sizep = (unsigned int *)get_property(node, "linux,tce-size", NULL);
 326         if (basep == NULL || sizep == NULL) {
 327                 printk(KERN_ERR "PCI_DMA: iommu_table_setparms: %s has "
 328                                 "missing tce entries !\n", dn->full_name);
 329                 return;
 330         }
 331
 332         tbl->it_base = (unsigned long)__va(*basep);
 333         memset((void *)tbl->it_base, 0, *sizep);
 334
 335         tbl->it_busno = phb->bus->number;
 336
 337         /* Units of tce entries */
 338         tbl->it_offset = phb->dma_window_base_cur;
 339
 340         /* Adjust the current table offset to the next
 341          * region.  Measured in TCE entries. Force an
 342          * alignment to the size allotted per IOA. This
 343          * makes it easier to remove the 1st 16MB.
 344          */
 345         phb->dma_window_base_cur += (phb->dma_window_size>>3);
 346         phb->dma_window_base_cur &=
 347                 ~((phb->dma_window_size>>3)-1);
 348
 349         /* Set the tce table size - measured in pages */
 350         tbl->it_size = ((phb->dma_window_base_cur -
 351                          tbl->it_offset) << 3) >> PAGE_SHIFT;
 352
 353         /* Test if we are going over 2GB of DMA space */
 354         if (phb->dma_window_base_cur > (1 << 19))
 355                 panic("PCI_DMA: Unexpected number of IOAs under this PHB.\n");
 356
 357         tbl->it_index = 0;
 358         tbl->it_entrysize = sizeof(union tce_entry);
 359         tbl->it_blocksize = 16;
 360         tbl->it_type = TCE_PCI;
 361 }
 362
 363 /*
 364  * iommu_table_setparms_lpar
 365  *
 366  * Function: On pSeries LPAR systems, return TCE table info, given a pci bus.
 367  *
 368  * ToDo: properly interpret the ibm,dma-window property.  The definition is:
 369  *      logical-bus-number      (1 word)
 370  *      phys-address            (#address-cells words)
 371  *      size                    (#cell-size words)
 372  *
 373  * Currently we hard code these sizes (more or less).
 374  */
 375 static void iommu_table_setparms_lpar(struct pci_controller *phb,
 376                                       struct device_node *dn,
 377                                       struct iommu_table *tbl)
 378 {
 379         unsigned int *dma_window;
 380
 381         dma_window = (unsigned int *)get_property(dn, "ibm,dma-window", NULL);
 382
 383         if (!dma_window)
 384                 panic("iommu_table_setparms_lpar: device %s has no"
 385                       " ibm,dma-window property!\n", dn->full_name);
 386
 387         tbl->it_busno  = dn->bussubno;
 388         tbl->it_size   = (((((unsigned long)dma_window[4] << 32) |
 389                            (unsigned long)dma_window[5]) >> PAGE_SHIFT) << 3) >> PAGE_SHIFT;
 390         tbl->it_offset = ((((unsigned long)dma_window[2] << 32) |
 391                            (unsigned long)dma_window[3]) >> 12);
 392         tbl->it_base   = 0;
 393         tbl->it_index  = dma_window[0];
 394         tbl->it_entrysize = sizeof(union tce_entry);
 395         tbl->it_blocksize  = 16;
 396         tbl->it_type = TCE_PCI;
 397 }
 398
 399
 400 void iommu_devnode_init_pSeries(struct device_node *dn)
 401 {
 402         struct iommu_table *tbl;
 403
 404         tbl = (struct iommu_table *)kmalloc(sizeof(struct iommu_table),
 405                                             GFP_KERNEL);
 406
 407         if (systemcfg->platform == PLATFORM_PSERIES_LPAR)
 408                 iommu_table_setparms_lpar(dn->phb, dn, tbl);
 409         else
 410                 iommu_table_setparms(dn->phb, dn, tbl);
 411
 412         dn->iommu_table = iommu_init_table(tbl);
 413 }
 414
 415 void iommu_setup_pSeries(void)
 416 {
 417         struct pci_dev *dev = NULL;
 418         struct device_node *dn, *mydn;
 419
 420         if (systemcfg->platform == PLATFORM_PSERIES_LPAR)
 421                 iommu_buses_init_lpar(&pci_root_buses);
 422         else
 423                 iommu_buses_init();
 424
 425         /* Now copy the iommu_table ptr from the bus devices down to every
 426          * pci device_node.  This means get_iommu_table() won't need to search
 427          * up the device tree to find it.
 428          */
 429         for_each_pci_dev(dev) {
 430                 mydn = dn = pci_device_to_OF_node(dev);
 431
 432                 while (dn && dn->iommu_table == NULL)
 433                         dn = dn->parent;
 434                 if (dn)
 435                         mydn->iommu_table = dn->iommu_table;
 436         }
 437 }
 438
 439 /* These are called very early. */
 440 void tce_init_pSeries(void)
 441 {
 442         if (!(systemcfg->platform & PLATFORM_LPAR)) {
 443                 ppc_md.tce_build = tce_build_pSeries;
 444                 ppc_md.tce_free  = tce_free_pSeries;
 445         } else if (cur_cpu_spec->firmware_features & FW_FEATURE_MULTITCE) {
 446                 ppc_md.tce_build = tce_buildmulti_pSeriesLP;
 447                 ppc_md.tce_free  = tce_freemulti_pSeriesLP;
 448         } else {
 449                 ppc_md.tce_build = tce_build_pSeriesLP;
 450                 ppc_md.tce_free  = tce_free_pSeriesLP;
 451         }
 452
 453         pci_iommu_init();
 454 }
 455