2 * Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
10 #include <linux/oprofile.h>
11 #include <linux/init.h>
12 #include <linux/smp.h>
13 #include <asm/ptrace.h>
14 #include <asm/system.h>
15 #include <asm/processor.h>
16 #include <asm/cputable.h>
22 static void ctrl_write(unsigned int i, unsigned int val)
25 unsigned long shift = 0, mask = 0;
27 dbg("ctrl_write %d %x\n", i, val);
31 tmp = mfspr(SPRN_MMCR0);
36 tmp = mfspr(SPRN_MMCR0);
41 tmp = mfspr(SPRN_MMCR1);
46 tmp = mfspr(SPRN_MMCR1);
51 tmp = mfspr(SPRN_MMCR1);
56 tmp = mfspr(SPRN_MMCR1);
61 tmp = mfspr(SPRN_MMCR1);
66 tmp = mfspr(SPRN_MMCR1);
72 tmp = tmp & ~(mask << shift);
78 mtspr(SPRN_MMCR0, tmp);
81 mtspr(SPRN_MMCR1, tmp);
84 dbg("ctrl_write mmcr0 %lx mmcr1 %lx\n", mfspr(SPRN_MMCR0),
88 static unsigned long reset_value[OP_MAX_COUNTER];
90 static int num_counters;
92 static void rs64_reg_setup(struct op_counter_config *ctr,
93 struct op_system_config *sys,
98 num_counters = num_ctrs;
100 for (i = 0; i < num_counters; ++i)
101 reset_value[i] = 0x80000000UL - ctr[i].count;
103 /* XXX setup user and kernel profiling */
106 static void rs64_cpu_setup(void *unused)
110 /* reset MMCR0 and set the freeze bit */
112 mtspr(SPRN_MMCR0, mmcr0);
114 /* reset MMCR1, MMCRA */
115 mtspr(SPRN_MMCR1, 0);
117 if (cur_cpu_spec->cpu_features & CPU_FTR_MMCRA)
118 mtspr(SPRN_MMCRA, 0);
120 mmcr0 |= MMCR0_FCM1|MMCR0_PMXE|MMCR0_FCECE;
121 /* Only applies to POWER3, but should be safe on RS64 */
122 mmcr0 |= MMCR0_PMC1INTCONTROL|MMCR0_PMCNINTCONTROL;
123 mtspr(SPRN_MMCR0, mmcr0);
125 dbg("setup on cpu %d, mmcr0 %lx\n", smp_processor_id(),
127 dbg("setup on cpu %d, mmcr1 %lx\n", smp_processor_id(),
131 static void rs64_start(struct op_counter_config *ctr)
136 /* set the PMM bit (see comment below) */
137 mtmsrd(mfmsr() | MSR_PMM);
139 for (i = 0; i < num_counters; ++i) {
140 if (ctr[i].enabled) {
141 ctr_write(i, reset_value[i]);
142 ctrl_write(i, ctr[i].event);
148 mmcr0 = mfspr(SPRN_MMCR0);
151 * now clear the freeze bit, counting will not start until we
152 * rfid from this excetion, because only at that point will
153 * the PMM bit be cleared
156 mtspr(SPRN_MMCR0, mmcr0);
158 dbg("start on cpu %d, mmcr0 %x\n", smp_processor_id(), mmcr0);
161 static void rs64_stop(void)
165 /* freeze counters */
166 mmcr0 = mfspr(SPRN_MMCR0);
168 mtspr(SPRN_MMCR0, mmcr0);
170 dbg("stop on cpu %d, mmcr0 %x\n", smp_processor_id(), mmcr0);
175 static void rs64_handle_interrupt(struct pt_regs *regs,
176 struct op_counter_config *ctr)
181 unsigned long pc = mfspr(SPRN_SIAR);
182 int is_kernel = (pc >= KERNELBASE);
183 unsigned int cpu = smp_processor_id();
185 /* set the PMM bit (see comment below) */
186 mtmsrd(mfmsr() | MSR_PMM);
188 for (i = 0; i < num_counters; ++i) {
191 if (ctr[i].enabled) {
192 oprofile_add_sample(pc, is_kernel, i, cpu);
193 ctr_write(i, reset_value[i]);
200 mmcr0 = mfspr(SPRN_MMCR0);
202 /* reset the perfmon trigger */
206 * now clear the freeze bit, counting will not start until we
207 * rfid from this exception, because only at that point will
208 * the PMM bit be cleared
211 mtspr(SPRN_MMCR0, mmcr0);
214 struct op_ppc64_model op_model_rs64 = {
215 .reg_setup = rs64_reg_setup,
216 .cpu_setup = rs64_cpu_setup,
219 .handle_interrupt = rs64_handle_interrupt,