2 * arch/s390/kernel/entry.S
3 * S390 low-level entry points.
6 * Copyright (C) 1999,2000 IBM Deutschland Entwicklung GmbH, IBM Corporation
7 * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
8 * Hartmut Penner (hp@de.ibm.com),
9 * Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com),
12 #include <linux/sys.h>
13 #include <linux/linkage.h>
14 #include <linux/config.h>
15 #include <asm/cache.h>
16 #include <asm/lowcore.h>
17 #include <asm/errno.h>
18 #include <asm/ptrace.h>
19 #include <asm/thread_info.h>
20 #include <asm/offsets.h>
21 #include <asm/unistd.h>
24 * Stack layout for the system_call stack entry.
25 * The first few entries are identical to the user_regs_struct.
27 SP_PTREGS = STACK_FRAME_OVERHEAD
28 SP_ARGS = STACK_FRAME_OVERHEAD + __PT_ARGS
29 SP_PSW = STACK_FRAME_OVERHEAD + __PT_PSW
30 SP_R0 = STACK_FRAME_OVERHEAD + __PT_GPRS
31 SP_R1 = STACK_FRAME_OVERHEAD + __PT_GPRS + 8
32 SP_R2 = STACK_FRAME_OVERHEAD + __PT_GPRS + 16
33 SP_R3 = STACK_FRAME_OVERHEAD + __PT_GPRS + 24
34 SP_R4 = STACK_FRAME_OVERHEAD + __PT_GPRS + 32
35 SP_R5 = STACK_FRAME_OVERHEAD + __PT_GPRS + 40
36 SP_R6 = STACK_FRAME_OVERHEAD + __PT_GPRS + 48
37 SP_R7 = STACK_FRAME_OVERHEAD + __PT_GPRS + 56
38 SP_R8 = STACK_FRAME_OVERHEAD + __PT_GPRS + 64
39 SP_R9 = STACK_FRAME_OVERHEAD + __PT_GPRS + 72
40 SP_R10 = STACK_FRAME_OVERHEAD + __PT_GPRS + 80
41 SP_R11 = STACK_FRAME_OVERHEAD + __PT_GPRS + 88
42 SP_R12 = STACK_FRAME_OVERHEAD + __PT_GPRS + 96
43 SP_R13 = STACK_FRAME_OVERHEAD + __PT_GPRS + 104
44 SP_R14 = STACK_FRAME_OVERHEAD + __PT_GPRS + 112
45 SP_R15 = STACK_FRAME_OVERHEAD + __PT_GPRS + 120
46 SP_ORIG_R2 = STACK_FRAME_OVERHEAD + __PT_ORIG_GPR2
47 SP_ILC = STACK_FRAME_OVERHEAD + __PT_ILC
48 SP_TRAP = STACK_FRAME_OVERHEAD + __PT_TRAP
49 SP_SIZE = STACK_FRAME_OVERHEAD + __PT_SIZE
51 _TIF_WORK_SVC = (_TIF_SIGPENDING | _TIF_NEED_RESCHED | \
52 _TIF_RESTART_SVC | _TIF_SINGLE_STEP )
53 _TIF_WORK_INT = (_TIF_SIGPENDING | _TIF_NEED_RESCHED)
56 * Register usage in interrupt handlers:
57 * R9 - pointer to current task structure
58 * R13 - pointer to literal pool
59 * R14 - return register for function calls
60 * R15 - kernel stack pointer
63 .macro SAVE_ALL psworg,savearea,sync
64 stmg %r13,%r15,\savearea
66 tm \psworg+1,0x01 # test problem state bit
67 jz 1f # skip stack setup save
68 lg %r15,__LC_KERNEL_STACK # problem state -> load ksp
70 tm \psworg+1,0x01 # test problem state bit
71 jnz 0f # from user -> load kernel stack
72 lg %r14,__LC_ASYNC_STACK # are we already on the async. stack ?
76 0: lg %r15,__LC_ASYNC_STACK # load async stack
78 1: aghi %r15,-SP_SIZE # make room for registers & psw
81 icm %r14,12,__LC_SVC_ILC
82 stmg %r0,%r12,SP_R0(%r15) # store gprs 0-13 to kernel stack
83 stg %r2,SP_ORIG_R2(%r15) # store original content of gpr 2
84 mvc SP_R13(24,%r15),\savearea # move r13, r14 and r15 to stack
85 mvc SP_PSW(16,%r15),\psworg # move user PSW to stack
90 .macro CLEANUP_SAVE_ALL psworg,savearea,sync
94 mvc \savearea(24),SP_R13(%r15)
95 2: lg %r1,\savearea+16
99 lg %r1,__LC_KERNEL_STACK
103 lg %r0,__LC_ASYNC_STACK
107 0: lg %r1,__LC_ASYNC_STACK
112 xc SP_R13(8,%r15),SP_R13(%r15)
113 icm %r0,12,__LC_SVC_ILC
115 mvc SP_R0(104,%r1),SP_R0(%r15)
116 mvc SP_ORIG_R2(8,%r1),SP_R2(%r15)
117 mvc SP_R13(24,%r1),\savearea
118 mvc SP_PSW(16,%r1),\psworg
123 .macro RESTORE_ALL # system exit macro
124 mvc __LC_RETURN_PSW(16),SP_PSW(%r15) # move user PSW to lowcore
125 ni __LC_RETURN_PSW+1,0xfd # clear wait state bit
126 lmg %r0,%r15,SP_R0(%r15) # load gprs 0-15 of user
127 lpswe __LC_RETURN_PSW # back to caller
130 .macro CLEANUP_RESTORE_ALL
131 lg %r1,SP_PSW+8(%r15)
134 mvc SP_PSW(16,%r15),__LC_RETURN_PSW
136 0: lg %r1,SP_R15(%r15)
137 mvc SP_PSW(16,%r15),SP_PSW(%r1)
138 mvc SP_R0(128,%r15),SP_R0(%r1)
142 .macro GET_THREAD_INFO
143 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
146 .macro CHECK_CRITICAL
147 tm SP_PSW+1(%r15),0x01 # test problem state bit
148 jnz 0f # from user -> not critical
149 larl %r1,.Lcritical_start
150 clc SP_PSW+8(8,%r15),8(%r1) # compare ip with __critical_end
152 clc SP_PSW+8(8,%r15),0(%r1) # compare ip with __critical_start
154 brasl %r14,cleanup_critical
159 * Scheduler resume function, called by switch_to
160 * gpr2 = (task_struct *) prev
161 * gpr3 = (task_struct *) next
167 tm __THREAD_per+4(%r3),0xe8 # is the new process using per ?
168 jz __switch_to_noper # if not we're fine
169 stctg %c9,%c11,48(%r15) # We are using per stuff
170 clc __THREAD_per(24,%r3),48(%r15)
171 je __switch_to_noper # we got away without bashing TLB's
172 lctlg %c9,%c11,__THREAD_per(%r3) # Nope we didn't
174 stmg %r6,%r15,48(%r15) # store __switch_to registers of prev task
175 stg %r15,__THREAD_ksp(%r2) # store kernel stack to prev->tss.ksp
176 lg %r15,__THREAD_ksp(%r3) # load kernel stack from next->tss.ksp
177 lmg %r6,%r15,48(%r15) # load __switch_to registers of next task
178 stg %r3,__LC_CURRENT # __LC_CURRENT = current task struct
179 lg %r3,__THREAD_info(%r3) # load thread_info from task struct
180 stg %r3,__LC_THREAD_INFO
182 stg %r3,__LC_KERNEL_STACK # __LC_KERNEL_STACK = new kernel stack
186 * do_softirq calling function. We want to run the softirq functions on the
187 * asynchronous interrupt stack.
189 .global do_call_softirq
192 stmg %r12,%r15,56(%r15)
194 lg %r0,__LC_ASYNC_STACK
198 lg %r15,__LC_ASYNC_STACK
199 0: aghi %r15,-STACK_FRAME_OVERHEAD
200 stg %r12,0(%r15) # store back chain
201 brasl %r14,do_softirq
202 lmg %r12,%r15,56(%r12)
208 * SVC interrupt handler routine. System calls are synchronous events and
209 * are executed with interrupts enabled.
214 SAVE_ALL __LC_SVC_OLD_PSW,__LC_SAVE_AREA,1
215 llgh %r7,__LC_SVC_INT_CODE # get svc number from lowcore
217 GET_THREAD_INFO # load pointer to task_struct to R9
219 slag %r7,%r7,2 # *4 and test for svc 0
221 # svc 0: system call number in %r1
225 lgfr %r7,%r1 # clear high word in r1
226 slag %r7,%r7,2 # svc 0: system call number in %r1
228 mvc SP_ARGS(8,%r15),SP_R7(%r15)
230 larl %r10,sys_call_table
231 #ifdef CONFIG_S390_SUPPORT
232 tm SP_PSW+3(%r15),0x01 # are we running in 31 bit mode ?
234 larl %r10,sys_call_table_emu # use 31 bit emulation system calls
237 tm __TI_flags+7(%r9),(_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT)
238 lgf %r8,0(%r7,%r10) # load address of system call routine
240 basr %r14,%r8 # call sys_xxxx
241 stg %r2,SP_R2(%r15) # store return value (change R2 on stack)
242 # ATTENTION: check sys_execve_glue before
243 # changing anything here !!
246 tm SP_PSW+1(%r15),0x01 # returning to user ?
248 tm __TI_flags+7(%r9),_TIF_WORK_SVC
249 jnz sysc_work # there is work to do (signals etc.)
254 # recheck if there is more work to do
257 GET_THREAD_INFO # load pointer to task_struct to R9
258 tm __TI_flags+7(%r9),_TIF_WORK_SVC
259 jz sysc_leave # there is no work to do
261 # One of the work bits is on. Find out which one.
264 tm __TI_flags+7(%r9),_TIF_NEED_RESCHED
266 tm __TI_flags+7(%r9),_TIF_SIGPENDING
268 tm __TI_flags+7(%r9),_TIF_RESTART_SVC
270 tm __TI_flags+7(%r9),_TIF_SINGLE_STEP
275 # _TIF_NEED_RESCHED is set, call schedule
278 larl %r14,sysc_work_loop
279 jg schedule # return point is sysc_return
282 # _TIF_SIGPENDING is set, call do_signal
285 ni __TI_flags+7(%r9),255-_TIF_SINGLE_STEP # clear TIF_SINGLE_STEP
286 la %r2,SP_PTREGS(%r15) # load pt_regs
287 sgr %r3,%r3 # clear *oldset
288 brasl %r14,do_signal # call do_signal
289 tm __TI_flags+7(%r9),_TIF_RESTART_SVC
291 j sysc_leave # out of here, do NOT recheck
294 # _TIF_RESTART_SVC is set, set up registers and restart svc
297 ni __TI_flags+7(%r9),255-_TIF_RESTART_SVC # clear TIF_RESTART_SVC
298 lg %r7,SP_R2(%r15) # load new svc number
300 mvc SP_R2(8,%r15),SP_ORIG_R2(%r15) # restore first argument
301 lmg %r2,%r6,SP_R2(%r15) # load svc arguments
302 j sysc_do_restart # restart svc
305 # _TIF_SINGLE_STEP is set, call do_single_step
308 ni __TI_flags+7(%r9),255-_TIF_SINGLE_STEP # clear TIF_SINGLE_STEP
309 lhi %r0,__LC_PGM_OLD_PSW
310 sth %r0,SP_TRAP(%r15) # set trap indication to pgm check
311 la %r2,SP_PTREGS(%r15) # address of register-save area
312 larl %r14,sysc_return # load adr. of system return
313 jg do_single_step # branch to do_sigtrap
319 # call syscall_trace before and after system call
320 # special linkage: %r12 contains the return address for trace_svc
323 la %r2,SP_PTREGS(%r15) # load pt_regs
327 brasl %r14,syscall_trace
331 lg %r7,SP_R2(%r15) # strace might have changed the
332 sll %r7,2 # system call
335 lmg %r3,%r6,SP_R3(%r15)
336 lg %r2,SP_ORIG_R2(%r15)
337 basr %r14,%r8 # call sys_xxx
338 stg %r2,SP_R2(%r15) # store return value
340 tm __TI_flags+7(%r9),(_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT)
342 la %r2,SP_PTREGS(%r15) # load pt_regs
344 larl %r14,sysc_return # return point is sysc_return
348 # a new process exits the kernel with ret_from_fork
352 GET_THREAD_INFO # load pointer to task_struct to R9
353 brasl %r14,schedule_tail
354 stosm 24(%r15),0x03 # reenable interrupts
358 # clone, fork, vfork, exec and sigreturn need glue,
359 # because they all expect pt_regs as parameter,
360 # but are called with different parameter.
361 # return-address is set up above
364 la %r2,SP_PTREGS(%r15) # load pt_regs
365 jg sys_clone # branch to sys_clone
367 #ifdef CONFIG_S390_SUPPORT
369 la %r2,SP_PTREGS(%r15) # load pt_regs
370 jg sys32_clone # branch to sys32_clone
374 la %r2,SP_PTREGS(%r15) # load pt_regs
375 jg sys_fork # branch to sys_fork
378 la %r2,SP_PTREGS(%r15) # load pt_regs
379 jg sys_vfork # branch to sys_vfork
382 la %r2,SP_PTREGS(%r15) # load pt_regs
383 lgr %r12,%r14 # save return address
384 brasl %r14,sys_execve # call sys_execve
385 ltgr %r2,%r2 # check if execve failed
386 bnz 0(%r12) # it did fail -> store result in gpr2
387 b 6(%r12) # SKIP STG 2,SP_R2(15) in
388 # system_call/sysc_tracesys
389 #ifdef CONFIG_S390_SUPPORT
391 la %r2,SP_PTREGS(%r15) # load pt_regs
392 lgr %r12,%r14 # save return address
393 brasl %r14,sys32_execve # call sys32_execve
394 ltgr %r2,%r2 # check if execve failed
395 bnz 0(%r12) # it did fail -> store result in gpr2
396 b 6(%r12) # SKIP STG 2,SP_R2(15) in
397 # system_call/sysc_tracesys
401 la %r2,SP_PTREGS(%r15) # load pt_regs as parameter
402 jg sys_sigreturn # branch to sys_sigreturn
404 #ifdef CONFIG_S390_SUPPORT
405 sys32_sigreturn_glue:
406 la %r2,SP_PTREGS(%r15) # load pt_regs as parameter
407 jg sys32_sigreturn # branch to sys32_sigreturn
410 sys_rt_sigreturn_glue:
411 la %r2,SP_PTREGS(%r15) # load pt_regs as parameter
412 jg sys_rt_sigreturn # branch to sys_sigreturn
414 #ifdef CONFIG_S390_SUPPORT
415 sys32_rt_sigreturn_glue:
416 la %r2,SP_PTREGS(%r15) # load pt_regs as parameter
417 jg sys32_rt_sigreturn # branch to sys32_sigreturn
421 # sigsuspend and rt_sigsuspend need pt_regs as an additional
422 # parameter and they have to skip the store of %r2 into the
423 # user register %r2 because the return value was set in
424 # sigsuspend and rt_sigsuspend already and must not be overwritten!
428 lgr %r5,%r4 # move mask back
429 lgr %r4,%r3 # move history1 parameter
430 lgr %r3,%r2 # move history0 parameter
431 la %r2,SP_PTREGS(%r15) # load pt_regs as first parameter
432 la %r14,6(%r14) # skip store of return value
433 jg sys_sigsuspend # branch to sys_sigsuspend
435 #ifdef CONFIG_S390_SUPPORT
436 sys32_sigsuspend_glue:
437 llgfr %r4,%r4 # unsigned long
438 lgr %r5,%r4 # move mask back
440 lgr %r4,%r3 # move history1 parameter
442 lgr %r3,%r2 # move history0 parameter
443 la %r2,SP_PTREGS(%r15) # load pt_regs as first parameter
444 la %r14,6(%r14) # skip store of return value
445 jg sys32_sigsuspend # branch to sys32_sigsuspend
448 sys_rt_sigsuspend_glue:
449 lgr %r4,%r3 # move sigsetsize parameter
450 lgr %r3,%r2 # move unewset parameter
451 la %r2,SP_PTREGS(%r15) # load pt_regs as first parameter
452 la %r14,6(%r14) # skip store of return value
453 jg sys_rt_sigsuspend # branch to sys_rt_sigsuspend
455 #ifdef CONFIG_S390_SUPPORT
456 sys32_rt_sigsuspend_glue:
457 llgfr %r3,%r3 # size_t
458 lgr %r4,%r3 # move sigsetsize parameter
459 llgtr %r2,%r2 # sigset_emu31_t *
460 lgr %r3,%r2 # move unewset parameter
461 la %r2,SP_PTREGS(%r15) # load pt_regs as first parameter
462 la %r14,6(%r14) # skip store of return value
463 jg sys32_rt_sigsuspend # branch to sys32_rt_sigsuspend
466 sys_sigaltstack_glue:
467 la %r4,SP_PTREGS(%r15) # load pt_regs as parameter
468 jg sys_sigaltstack # branch to sys_sigreturn
470 #ifdef CONFIG_S390_SUPPORT
471 sys32_sigaltstack_glue:
472 la %r4,SP_PTREGS(%r15) # load pt_regs as parameter
473 jg sys32_sigaltstack_wrapper # branch to sys_sigreturn
477 * Program check handler routine
480 .globl pgm_check_handler
483 * First we need to check for a special case:
484 * Single stepping an instruction that disables the PER event mask will
485 * cause a PER event AFTER the mask has been set. Example: SVC or LPSW.
486 * For a single stepped SVC the program check handler gets control after
487 * the SVC new PSW has been loaded. But we want to execute the SVC first and
488 * then handle the PER event. Therefore we update the SVC old PSW to point
489 * to the pgm_check_handler and branch to the SVC handler after we checked
490 * if we have to load the kernel stack register.
491 * For every other possible cause for PER event without the PER mask set
492 * we just ignore the PER event (FIXME: is there anything we have to do
495 tm __LC_PGM_INT_CODE+1,0x80 # check whether we got a per exception
496 jnz pgm_per # got per exception -> special case
497 SAVE_ALL __LC_PGM_OLD_PSW,__LC_SAVE_AREA,1
498 lgf %r3,__LC_PGM_ILC # load program interruption code
504 larl %r1,pgm_check_table
505 lg %r1,0(%r8,%r1) # load address of handler routine
506 la %r2,SP_PTREGS(%r15) # address of register-save area
507 larl %r14,sysc_return
508 br %r1 # branch to interrupt-handler
511 # handle per exception
514 tm __LC_PGM_OLD_PSW,0x40 # test if per event recording is on
515 jnz pgm_per_std # ok, normal per event from user space
516 # ok its one of the special cases, now we need to find out which one
517 clc __LC_PGM_OLD_PSW(16),__LC_SVC_NEW_PSW
519 # no interesting special case, ignore PER event
520 lpswe __LC_PGM_OLD_PSW
523 # Normal per exception
526 SAVE_ALL __LC_PGM_OLD_PSW,__LC_SAVE_AREA,1
528 lg %r1,__TI_task(%r9)
529 mvc __THREAD_per+__PER_atmid(2,%r1),__LC_PER_ATMID
530 mvc __THREAD_per+__PER_address(8,%r1),__LC_PER_ADDRESS
531 mvc __THREAD_per+__PER_access_id(1,%r1),__LC_PER_ACCESS_ID
532 oi __TI_flags+7(%r9),_TIF_SINGLE_STEP # set TIF_SINGLE_STEP
533 lgf %r3,__LC_PGM_ILC # load program interruption code
535 ngr %r8,%r3 # clear per-event-bit and ilc
540 # it was a single stepped SVC that is causing all the trouble
543 SAVE_ALL __LC_SVC_OLD_PSW,__LC_SAVE_AREA,1
544 llgh %r7,__LC_SVC_INT_CODE # get svc number from lowcore
545 GET_THREAD_INFO # load pointer to task_struct to R9
546 lg %r1,__TI_task(%r9)
547 mvc __THREAD_per+__PER_atmid(2,%r1),__LC_PER_ATMID
548 mvc __THREAD_per+__PER_address(8,%r1),__LC_PER_ADDRESS
549 mvc __THREAD_per+__PER_access_id(1,%r1),__LC_PER_ACCESS_ID
550 oi __TI_flags+7(%r9),_TIF_SINGLE_STEP # set TIF_SINGLE_STEP
551 stosm 48(%r15),0x03 # reenable interrupts
555 * IO interrupt handler routine
557 .globl io_int_handler
559 SAVE_ALL __LC_IO_OLD_PSW,__LC_SAVE_AREA+32,0
562 GET_THREAD_INFO # load pointer to task_struct to R9
563 la %r2,SP_PTREGS(%r15) # address of register-save area
564 brasl %r14,do_IRQ # call standard irq handler
567 tm SP_PSW+1(%r15),0x01 # returning to user ?
568 #ifdef CONFIG_PREEMPT
569 jno io_preempt # no -> check for preemptive scheduling
571 jno io_leave # no-> skip resched & signal
573 tm __TI_flags+7(%r9),_TIF_WORK_INT
574 jnz io_work # there is work to do (signals etc.)
578 #ifdef CONFIG_PREEMPT
580 icm %r0,15,__TI_precount(%r9)
582 # switch to kernel stack
585 mvc SP_PTREGS(__PT_SIZE,%r1),SP_PTREGS(%r15)
586 xc 0(8,%r1),0(%r1) # clear back chain
589 tm __TI_flags+7(%r9),_TIF_NEED_RESCHED
592 mvc __TI_precount(4,%r9),0(%r1)
593 stosm 48(%r15),0x03 # reenable interrupts
594 brasl %r14,schedule # call schedule
595 stnsm 48(%r15),0xfc # disable I/O and ext. interrupts
596 GET_THREAD_INFO # load pointer to task_struct to R9
597 xc __TI_precount(4,%r9),__TI_precount(%r9)
602 # switch to kernel stack, then check TIF bits
605 lg %r1,__LC_KERNEL_STACK
607 mvc SP_PTREGS(__PT_SIZE,%r1),SP_PTREGS(%r15)
608 xc 0(8,%r1),0(%r1) # clear back chain
611 # One of the work bits is on. Find out which one.
612 # Checked are: _TIF_SIGPENDING and _TIF_NEED_RESCHED
615 tm __TI_flags+7(%r9),_TIF_NEED_RESCHED
617 tm __TI_flags+7(%r9),_TIF_SIGPENDING
622 # _TIF_NEED_RESCHED is set, call schedule
625 stosm 48(%r15),0x03 # reenable interrupts
626 brasl %r14,schedule # call scheduler
627 stnsm 48(%r15),0xfc # disable I/O and ext. interrupts
628 GET_THREAD_INFO # load pointer to task_struct to R9
629 tm __TI_flags+7(%r9),_TIF_WORK_INT
630 jz io_leave # there is no work to do
634 # _TIF_SIGPENDING is set, call do_signal
637 stosm 48(%r15),0x03 # reenable interrupts
638 la %r2,SP_PTREGS(%r15) # load pt_regs
639 slgr %r3,%r3 # clear *oldset
640 brasl %r14,do_signal # call do_signal
641 stnsm 48(%r15),0xfc # disable I/O and ext. interrupts
642 j sysc_leave # out of here, do NOT recheck
645 * External interrupt handler routine
647 .globl ext_int_handler
649 SAVE_ALL __LC_EXT_OLD_PSW,__LC_SAVE_AREA+32,0
651 GET_THREAD_INFO # load pointer to task_struct to R9
653 la %r2,SP_PTREGS(%r15) # address of register-save area
654 llgh %r3,__LC_EXT_INT_CODE # get interruption code
659 * Machine check handler routines
661 .globl mcck_int_handler
663 SAVE_ALL __LC_MCK_OLD_PSW,__LC_SAVE_AREA+64,0
664 brasl %r14,s390_do_machine_check
670 * Restart interruption handler, kick starter for additional CPUs
672 .globl restart_int_handler
674 lg %r15,__LC_SAVE_AREA+120 # load ksp
675 lghi %r10,__LC_CREGS_SAVE_AREA
676 lctlg %c0,%c15,0(%r10) # get new ctl regs
677 lghi %r10,__LC_AREGS_SAVE_AREA
679 stosm 0(%r15),0x04 # now we can turn dat on
680 lmg %r6,%r15,48(%r15) # load registers from clone
684 * If we do not run with SMP enabled, let the new CPU crash ...
686 .globl restart_int_handler
690 lpswe restart_crash-restart_base(%r1)
693 .long 0x000a0000,0x00000000,0x00000000,0x00000000
698 .quad system_call, sysc_enter, cleanup_sysc_enter
699 .quad sysc_return, sysc_leave, cleanup_sysc_return
700 .quad sysc_leave, sysc_work_loop, cleanup_sysc_leave
701 .quad sysc_work_loop, sysc_reschedule, cleanup_sysc_return
702 cleanup_table_entries=(.-cleanup_table) / 24
705 lghi %r0,cleanup_table_entries
706 larl %r1,cleanup_table
707 lg %r2,SP_PSW+8(%r15)
715 brct %r0,cleanup_loop
722 CLEANUP_SAVE_ALL __LC_SVC_OLD_PSW,__LC_SAVE_AREA,1
726 stg %r1,SP_PSW+8(%r15)
731 stg %r1,SP_PSW+8(%r15)
743 .Lc_pactive: .long PREEMPT_ACTIVE
745 .quad __critical_start
749 #define SYSCALL(esa,esame,emu) .long esame
750 .globl sys_call_table
752 #include "syscalls.S"
755 #ifdef CONFIG_S390_SUPPORT
757 #define SYSCALL(esa,esame,emu) .long emu
758 .globl sys_call_table_emu
760 #include "syscalls.S"