3 * By Dustin McIntire (dustin@sensoria.com) (c)2001
5 * Setup and IRQ handling code for the HD64465 companion chip.
6 * by Greg Banks <gbanks@pocketpenguins.com>
7 * Copyright (c) 2000 PocketPenguins Inc
9 * Derived from setup_hd64465.c which bore the message:
10 * Greg Banks <gbanks@pocketpenguins.com>
11 * Copyright (c) 2000 PocketPenguins Inc and
12 * Copyright (C) 2000 YAEGASHI Takeshi
13 * and setup_cqreek.c which bore message:
14 * Copyright (C) 2000 Niibe Yutaka
16 * May be copied or modified under the terms of the GNU General Public
17 * License. See linux/COPYING for more information.
19 * IRQ functions for a Hitachi Big Sur Evaluation Board.
23 #include <linux/sched.h>
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/param.h>
27 #include <linux/ioport.h>
28 #include <linux/interrupt.h>
29 #include <linux/init.h>
30 #include <linux/irq.h>
31 #include <linux/bitops.h>
36 #include <asm/bigsur/io.h>
37 #include <asm/hd64465/hd64465.h>
38 #include <asm/bigsur/bigsur.h>
40 //#define BIGSUR_DEBUG 3
44 #define DPRINTK(args...) printk(args)
45 #define DIPRINTK(n, args...) if (BIGSUR_DEBUG>(n)) printk(args)
47 #define DPRINTK(args...)
48 #define DIPRINTK(n, args...)
49 #endif /* BIGSUR_DEBUG */
52 extern int hd64465_irq_demux(int irq);
53 #endif /* CONFIG_HD64465 */
56 /*===========================================================*/
57 // Big Sur CPLD IRQ Routines
58 /*===========================================================*/
60 /* Level 1 IRQ routines */
61 static void disable_bigsur_l1irq(unsigned int irq)
65 unsigned int mask_port = ((irq - BIGSUR_IRQ_LOW)/8) ? BIGSUR_IRLMR1 : BIGSUR_IRLMR0;
66 unsigned char bit = (1 << ((irq - MGATE_IRQ_LOW)%8) );
68 if(irq >= BIGSUR_IRQ_LOW && irq < BIGSUR_IRQ_HIGH) {
69 DPRINTK("Disable L1 IRQ %d\n", irq);
70 DIPRINTK(2,"disable_bigsur_l1irq: IMR=0x%08x mask=0x%x\n",
72 local_irq_save(flags);
74 /* Disable IRQ - set mask bit */
75 mask = inb(mask_port) | bit;
76 outb(mask, mask_port);
77 local_irq_restore(flags);
80 DPRINTK("disable_bigsur_l1irq: Invalid IRQ %d\n", irq);
83 static void enable_bigsur_l1irq(unsigned int irq)
87 unsigned int mask_port = ((irq - BIGSUR_IRQ_LOW)/8) ? BIGSUR_IRLMR1 : BIGSUR_IRLMR0;
88 unsigned char bit = (1 << ((irq - MGATE_IRQ_LOW)%8) );
90 if(irq >= BIGSUR_IRQ_LOW && irq < BIGSUR_IRQ_HIGH) {
91 DPRINTK("Enable L1 IRQ %d\n", irq);
92 DIPRINTK(2,"enable_bigsur_l1irq: IMR=0x%08x mask=0x%x\n",
94 local_irq_save(flags);
95 /* Enable L1 IRQ - clear mask bit */
96 mask = inb(mask_port) & ~bit;
97 outb(mask, mask_port);
98 local_irq_restore(flags);
101 DPRINTK("enable_bigsur_l1irq: Invalid IRQ %d\n", irq);
105 /* Level 2 irq masks and registers for L2 decoding */
106 /* Level2 bitmasks for each level 1 IRQ */
107 const u32 bigsur_l2irq_mask[] =
108 {0x40,0x80,0x08,0x01,0x01,0x3C,0x3E,0xFF,0x40,0x80,0x06,0x03};
109 /* Level2 to ISR[n] map for each level 1 IRQ */
110 const u32 bigsur_l2irq_reg[] =
111 { 2, 2, 3, 3, 1, 2, 1, 0, 1, 1, 3, 2};
112 /* Level2 to Level 1 IRQ map */
113 const u32 bigsur_l2_l1_map[] =
114 {7,7,7,7,7,7,7,7, 4,6,6,6,6,6,8,9, 11,11,5,5,5,5,0,1, 3,10,10,2,-1,-1,-1,-1};
115 /* IRQ inactive level (high or low) */
116 const u32 bigsur_l2_inactv_state[] = {0x00, 0xBE, 0xFC, 0xF7};
118 /* CPLD external status and mask registers base and offsets */
119 static const u32 isr_base = BIGSUR_IRQ0;
120 static const u32 isr_offset = BIGSUR_IRQ0 - BIGSUR_IRQ1;
121 static const u32 imr_base = BIGSUR_IMR0;
122 static const u32 imr_offset = BIGSUR_IMR0 - BIGSUR_IMR1;
124 #define REG_NUM(irq) ((irq-BIGSUR_2NDLVL_IRQ_LOW)/8 )
126 /* Level 2 IRQ routines */
127 static void disable_bigsur_l2irq(unsigned int irq)
131 unsigned char bit = 1 << ((irq-BIGSUR_2NDLVL_IRQ_LOW)%8);
132 unsigned int mask_port = imr_base - REG_NUM(irq)*imr_offset;
134 if(irq >= BIGSUR_2NDLVL_IRQ_LOW && irq < BIGSUR_2NDLVL_IRQ_HIGH) {
135 DPRINTK("Disable L2 IRQ %d\n", irq);
136 DIPRINTK(2,"disable_bigsur_l2irq: IMR=0x%08x mask=0x%x\n",
138 local_irq_save(flags);
140 /* Disable L2 IRQ - set mask bit */
141 mask = inb(mask_port) | bit;
142 outb(mask, mask_port);
143 local_irq_restore(flags);
146 DPRINTK("disable_bigsur_l2irq: Invalid IRQ %d\n", irq);
149 static void enable_bigsur_l2irq(unsigned int irq)
153 unsigned char bit = 1 << ((irq-BIGSUR_2NDLVL_IRQ_LOW)%8);
154 unsigned int mask_port = imr_base - REG_NUM(irq)*imr_offset;
156 if(irq >= BIGSUR_2NDLVL_IRQ_LOW && irq < BIGSUR_2NDLVL_IRQ_HIGH) {
157 DPRINTK("Enable L2 IRQ %d\n", irq);
158 DIPRINTK(2,"enable_bigsur_l2irq: IMR=0x%08x mask=0x%x\n",
160 local_irq_save(flags);
162 /* Enable L2 IRQ - clear mask bit */
163 mask = inb(mask_port) & ~bit;
164 outb(mask, mask_port);
165 local_irq_restore(flags);
168 DPRINTK("enable_bigsur_l2irq: Invalid IRQ %d\n", irq);
171 static void mask_and_ack_bigsur(unsigned int irq)
173 DPRINTK("mask_and_ack_bigsur IRQ %d\n", irq);
174 if(irq >= BIGSUR_IRQ_LOW && irq < BIGSUR_IRQ_HIGH)
175 disable_bigsur_l1irq(irq);
177 disable_bigsur_l2irq(irq);
180 static void end_bigsur_irq(unsigned int irq)
182 DPRINTK("end_bigsur_irq IRQ %d\n", irq);
183 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) {
184 if(irq >= BIGSUR_IRQ_LOW && irq < BIGSUR_IRQ_HIGH)
185 enable_bigsur_l1irq(irq);
187 enable_bigsur_l2irq(irq);
191 static unsigned int startup_bigsur_irq(unsigned int irq)
196 DPRINTK("startup_bigsur_irq IRQ %d\n", irq);
198 if(irq >= BIGSUR_IRQ_LOW && irq < BIGSUR_IRQ_HIGH) {
199 /* Enable the L1 IRQ */
200 enable_bigsur_l1irq(irq);
201 /* Enable all L2 IRQs in this L1 IRQ */
202 mask = ~(bigsur_l2irq_mask[irq-BIGSUR_IRQ_LOW]);
203 reg = imr_base - bigsur_l2irq_reg[irq-BIGSUR_IRQ_LOW] * imr_offset;
206 DIPRINTK(2,"startup_bigsur_irq: IMR=0x%08x mask=0x%x\n",reg,inb(reg));
209 /* Enable the L2 IRQ - clear mask bit */
210 enable_bigsur_l2irq(irq);
211 /* Enable the L1 bit masking this L2 IRQ */
212 enable_bigsur_l1irq(bigsur_l2_l1_map[irq-BIGSUR_2NDLVL_IRQ_LOW]);
213 DIPRINTK(2,"startup_bigsur_irq: L1=%d L2=%d\n",
214 bigsur_l2_l1_map[irq-BIGSUR_2NDLVL_IRQ_LOW],irq);
219 static void shutdown_bigsur_irq(unsigned int irq)
221 DPRINTK("shutdown_bigsur_irq IRQ %d\n", irq);
222 if(irq >= BIGSUR_IRQ_LOW && irq < BIGSUR_IRQ_HIGH)
223 disable_bigsur_l1irq(irq);
225 disable_bigsur_l2irq(irq);
228 /* Define the IRQ structures for the L1 and L2 IRQ types */
229 static struct hw_interrupt_type bigsur_l1irq_type = {
230 .typename = "BigSur-CPLD-Level1-IRQ",
231 .startup = startup_bigsur_irq,
232 .shutdown = shutdown_bigsur_irq,
233 .enable = enable_bigsur_l1irq,
234 .disable = disable_bigsur_l1irq,
235 .ack = mask_and_ack_bigsur,
236 .end = end_bigsur_irq
239 static struct hw_interrupt_type bigsur_l2irq_type = {
240 .typename = "BigSur-CPLD-Level2-IRQ",
241 .startup = startup_bigsur_irq,
242 .shutdown =shutdown_bigsur_irq,
243 .enable = enable_bigsur_l2irq,
244 .disable = disable_bigsur_l2irq,
245 .ack = mask_and_ack_bigsur,
246 .end = end_bigsur_irq
250 static void make_bigsur_l1isr(unsigned int irq) {
252 /* sanity check first */
253 if(irq >= BIGSUR_IRQ_LOW && irq < BIGSUR_IRQ_HIGH) {
254 /* save the handler in the main description table */
255 irq_desc[irq].chip = &bigsur_l1irq_type;
256 irq_desc[irq].status = IRQ_DISABLED;
257 irq_desc[irq].action = 0;
258 irq_desc[irq].depth = 1;
260 disable_bigsur_l1irq(irq);
263 DPRINTK("make_bigsur_l1isr: bad irq, %d\n", irq);
267 static void make_bigsur_l2isr(unsigned int irq) {
269 /* sanity check first */
270 if(irq >= BIGSUR_2NDLVL_IRQ_LOW && irq < BIGSUR_2NDLVL_IRQ_HIGH) {
271 /* save the handler in the main description table */
272 irq_desc[irq].chip = &bigsur_l2irq_type;
273 irq_desc[irq].status = IRQ_DISABLED;
274 irq_desc[irq].action = 0;
275 irq_desc[irq].depth = 1;
277 disable_bigsur_l2irq(irq);
280 DPRINTK("make_bigsur_l2isr: bad irq, %d\n", irq);
284 /* The IRQ's will be decoded as follows:
285 * If a level 2 handler exists and there is an unmasked active
286 * IRQ, the 2nd level handler will be called.
287 * If a level 2 handler does not exist for the active IRQ
288 * the 1st level handler will be called.
291 int bigsur_irq_demux(int irq)
297 DIPRINTK(3,"bigsur_irq_demux, irq=%d\n", irq);
298 /* decode the 1st level IRQ */
299 if(irq >= BIGSUR_IRQ_LOW && irq < BIGSUR_IRQ_HIGH) {
300 /* Get corresponding L2 ISR bitmask and ISR number */
301 mask = bigsur_l2irq_mask[irq-BIGSUR_IRQ_LOW];
302 reg_num = bigsur_l2irq_reg[irq-BIGSUR_IRQ_LOW];
303 /* find the active IRQ's (XOR with inactive level)*/
304 actv_irqs = inb(isr_base-reg_num*isr_offset) ^
305 bigsur_l2_inactv_state[reg_num];
306 /* decode active IRQ's */
307 actv_irqs = actv_irqs & mask & ~(inb(imr_base-reg_num*imr_offset));
308 /* if NEZ then we have an active L2 IRQ */
309 if(actv_irqs) dmux_irq = ffz(~actv_irqs) + reg_num*8+BIGSUR_2NDLVL_IRQ_LOW;
310 /* if no 2nd level IRQ action, but has 1st level, use 1st level handler */
311 if(!irq_desc[dmux_irq].action && irq_desc[irq].action)
313 DIPRINTK(1,"bigsur_irq_demux: irq=%d dmux_irq=%d mask=0x%04x reg=%d\n",
314 irq, dmux_irq, mask, reg_num);
316 #ifdef CONFIG_HD64465
317 dmux_irq = hd64465_irq_demux(dmux_irq);
318 #endif /* CONFIG_HD64465 */
319 DIPRINTK(3,"bigsur_irq_demux, demux_irq=%d\n", dmux_irq);
324 /*===========================================================*/
325 // Big Sur Init Routines
326 /*===========================================================*/
327 void __init init_bigsur_IRQ(void)
331 if (!MACH_BIGSUR) return;
333 /* Create ISR's for Big Sur CPLD IRQ's */
334 /*==============================================================*/
335 for(i=BIGSUR_IRQ_LOW;i<BIGSUR_IRQ_HIGH;i++)
336 make_bigsur_l1isr(i);
338 printk(KERN_INFO "Big Sur CPLD L1 interrupts %d to %d.\n",
339 BIGSUR_IRQ_LOW,BIGSUR_IRQ_HIGH);
341 for(i=BIGSUR_2NDLVL_IRQ_LOW;i<BIGSUR_2NDLVL_IRQ_HIGH;i++)
342 make_bigsur_l2isr(i);
344 printk(KERN_INFO "Big Sur CPLD L2 interrupts %d to %d.\n",
345 BIGSUR_2NDLVL_IRQ_LOW,BIGSUR_2NDLVL_IRQ_HIGH);