1 /* $Id: entry.S,v 1.144 2002/02/09 19:49:30 davem Exp $
2 * arch/sparc64/kernel/entry.S: Sparc64 trap low-level entry points.
4 * Copyright (C) 1995,1997 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1996 Eddie C. Dost (ecd@skynet.be)
6 * Copyright (C) 1996 Miguel de Icaza (miguel@nuclecu.unam.mx)
7 * Copyright (C) 1996,98,99 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
10 #include <linux/config.h>
11 #include <linux/errno.h>
16 #include <asm/ptrace.h>
18 #include <asm/signal.h>
19 #include <asm/pgtable.h>
20 #include <asm/processor.h>
21 #include <asm/visasm.h>
22 #include <asm/estate.h>
23 #include <asm/auxio.h>
25 /* #define SYSCALL_TRACING 1 */
29 #define NR_SYSCALLS 283 /* Each OS is different... */
34 .globl sparc64_vpte_patchme1
35 .globl sparc64_vpte_patchme2
37 * On a second level vpte miss, check whether the original fault is to the OBP
38 * range (note that this is only possible for instruction miss, data misses to
39 * obp range do not use vpte). If so, go back directly to the faulting address.
40 * This is because we want to read the tpc, otherwise we have no way of knowing
41 * the 8k aligned faulting address if we are using >8k kernel pagesize. This also
42 * ensures no vpte range addresses are dropped into tlb while obp is executing
43 * (see inherit_locked_prom_mappings() rant).
47 sllx %g5, 28, %g5 ! Load 0xf0000000
48 cmp %g4, %g5 ! Is addr >= LOW_OBP_ADDRESS?
49 blu,pn %xcc, sparc64_vpte_patchme1
51 sllx %g5, 32, %g5 ! Load 0x100000000
52 cmp %g4, %g5 ! Is addr < HI_OBP_ADDRESS?
53 blu,pn %xcc, obp_iaddr_patch
55 sparc64_vpte_patchme1:
56 sethi %hi(0), %g5 ! This has to be patched
57 sparc64_vpte_patchme2:
58 or %g5, %lo(0), %g5 ! This is patched too
59 ba,pt %xcc, sparc64_kpte_continue ! Part of dtlb_backend
60 add %g1, %g1, %g1 ! Finish PMD offset adjustment
63 mov TLB_SFSR, %g1 ! Restore %g1 value
64 stxa %g4, [%g1 + %g1] ASI_DMMU ! Restore previous TAG_ACCESS
67 .globl obp_iaddr_patch
68 .globl obp_daddr_patch
71 sethi %hi(0), %g5 ! This and following is patched
72 or %g5, %lo(0), %g5 ! g5 now holds obp pmd base physaddr
73 wrpr %g0, 1, %tl ! Behave as if we are at TL0
74 rdpr %tpc, %g4 ! Find original faulting iaddr
75 srlx %g4, 13, %g4 ! Throw out context bits
76 sllx %g4, 13, %g4 ! g4 has vpn + ctx0 now
77 mov TLB_SFSR, %g1 ! Restore %g1 value
78 stxa %g4, [%g1 + %g1] ASI_IMMU ! Restore previous TAG_ACCESS
79 srlx %g4, 23, %g6 ! Find pmd number
80 and %g6, 0x7ff, %g6 ! Find pmd number
81 sllx %g6, 2, %g6 ! Find pmd offset
82 lduwa [%g5 + %g6] ASI_PHYS_USE_EC, %g5! Load pmd, ie pagetable physaddr
83 brz,pn %g5, longpath ! Kill the PROM ? :-)
84 sllx %g5, 11, %g5 ! Shift into place
85 srlx %g4, 13, %g6 ! find pte number in pagetable
86 and %g6, 0x3ff, %g6 ! find pte number in pagetable
87 sllx %g6, 3, %g6 ! find pte offset in pagetable
88 ldxa [%g5 + %g6] ASI_PHYS_USE_EC, %g5! Load pte
89 brgez,pn %g5, longpath ! Kill the PROM ? :-)
91 stxa %g5, [%g0] ASI_ITLB_DATA_IN ! put into tlb
92 retry ! go back to original fault
95 sethi %hi(0), %g5 ! This and following is patched
96 or %g5, %lo(0), %g5 ! g5 now holds obp pmd base physaddr
97 srlx %g4, 23, %g6 ! Find pmd number
98 and %g6, 0x7ff, %g6 ! Find pmd number
99 sllx %g6, 2, %g6 ! Find pmd offset
100 lduwa [%g5 + %g6] ASI_PHYS_USE_EC, %g5! Load pmd, ie pagetable physaddr
102 sllx %g5, 11, %g5 ! Shift into place
103 srlx %g4, 13, %g6 ! find pte number in pagetable
104 and %g6, 0x3ff, %g6 ! find pte number in pagetable
105 sllx %g6, 3, %g6 ! find pte offset in pagetable
106 ldxa [%g5 + %g6] ASI_PHYS_USE_EC, %g5! Load pte
107 brgez,pn %g5, longpath
109 stxa %g5, [%g0] ASI_DTLB_DATA_IN ! put into tlb
113 * On a first level data miss, check whether this is to the OBP range (note that
114 * such accesses can be made by prom, as well as by kernel using prom_getproperty
115 * on "address"), and if so, do not use vpte access ... rather, use information
116 * saved during inherit_prom_mappings() using 8k pagesize.
120 sllx %g5, 28, %g5 ! Load 0xf0000000
121 cmp %g4, %g5 ! Is addr >= LOW_OBP_ADDRESS?
122 blu,pn %xcc, vmalloc_addr
124 sllx %g5, 32, %g5 ! Load 0x100000000
125 cmp %g4, %g5 ! Is addr < HI_OBP_ADDRESS?
126 blu,pn %xcc, obp_daddr_patch
128 vmalloc_addr: ! vmalloc addr accessed
129 ldxa [%g3 + %g6] ASI_N, %g5 ! Yep, load k-vpte
130 brgez,pn %g5, longpath ! Valid, load into TLB
132 stxa %g5, [%g0] ASI_DTLB_DATA_IN ! Reload TLB
135 /* This is trivial with the new code... */
138 sethi %hi(TSTATE_PEF), %g4 ! IEU0
144 andcc %g5, FPRS_FEF, %g0
148 /* Legal state when DCR_IFPOE is set in Cheetah %dcr. */
151 109: or %g7, %lo(109b), %g7
153 ba,a,pt %xcc, rtrap_clr_l6
155 1: ldub [%g6 + TI_FPSAVED], %g5 ! Load Group
156 wr %g0, FPRS_FEF, %fprs ! LSU Group+4bubbles
157 andcc %g5, FPRS_FEF, %g0 ! IEU1 Group
158 be,a,pt %icc, 1f ! CTI
160 ldx [%g6 + TI_GSR], %g7 ! Load Group
161 1: andcc %g5, FPRS_DL, %g0 ! IEU1
162 bne,pn %icc, 2f ! CTI
164 andcc %g5, FPRS_DU, %g0 ! IEU1 Group
165 bne,pn %icc, 1f ! CTI
195 b,pt %xcc, fpdis_exit2
197 1: mov SECONDARY_CONTEXT, %g3
198 add %g6, TI_FPREGS + 0x80, %g1
201 ldxa [%g3] ASI_DMMU, %g5
202 add %g6, TI_FPREGS + 0xc0, %g2
203 stxa %g0, [%g3] ASI_DMMU
207 ldda [%g1] ASI_BLK_S, %f32 ! grrr, where is ASI_BLK_NUCLEUS 8-(
208 ldda [%g2] ASI_BLK_S, %f48
219 b,pt %xcc, fpdis_exit
221 2: andcc %g5, FPRS_DU, %g0
224 mov SECONDARY_CONTEXT, %g3
226 ldxa [%g3] ASI_DMMU, %g5
227 add %g6, TI_FPREGS, %g1
228 stxa %g0, [%g3] ASI_DMMU
230 add %g6, TI_FPREGS + 0x40, %g2
231 faddd %f32, %f34, %f36
232 fmuld %f32, %f34, %f38
233 ldda [%g1] ASI_BLK_S, %f0 ! grrr, where is ASI_BLK_NUCLEUS 8-(
234 ldda [%g2] ASI_BLK_S, %f16
235 faddd %f32, %f34, %f40
236 fmuld %f32, %f34, %f42
237 faddd %f32, %f34, %f44
238 fmuld %f32, %f34, %f46
239 faddd %f32, %f34, %f48
240 fmuld %f32, %f34, %f50
241 faddd %f32, %f34, %f52
242 fmuld %f32, %f34, %f54
243 faddd %f32, %f34, %f56
244 fmuld %f32, %f34, %f58
245 faddd %f32, %f34, %f60
246 fmuld %f32, %f34, %f62
247 ba,pt %xcc, fpdis_exit
249 3: mov SECONDARY_CONTEXT, %g3
250 add %g6, TI_FPREGS, %g1
251 ldxa [%g3] ASI_DMMU, %g5
253 stxa %g0, [%g3] ASI_DMMU
255 ldda [%g1] ASI_BLK_S, %f0 ! grrr, where is ASI_BLK_NUCLEUS 8-(
256 ldda [%g1 + %g2] ASI_BLK_S, %f16
258 ldda [%g1] ASI_BLK_S, %f32
259 ldda [%g1 + %g2] ASI_BLK_S, %f48
262 stxa %g5, [%g3] ASI_DMMU
266 ldx [%g6 + TI_XFSR], %fsr
268 or %g3, %g4, %g3 ! anal...
270 wr %g0, FPRS_FEF, %fprs ! clean DU/DL bits
276 add %sp, PTREGS_OFF, %o0
280 .globl do_fpother_check_fitos
282 do_fpother_check_fitos:
283 sethi %hi(fp_other_bounce - 4), %g7
284 or %g7, %lo(fp_other_bounce - 4), %g7
286 /* NOTE: Need to preserve %g7 until we fully commit
287 * to the fitos fixup.
289 stx %fsr, [%g6 + TI_XFSR]
291 andcc %g3, TSTATE_PRIV, %g0
292 bne,pn %xcc, do_fptrap_after_fsr
294 ldx [%g6 + TI_XFSR], %g3
297 cmp %g1, 2 ! Unfinished FP-OP
298 bne,pn %xcc, do_fptrap_after_fsr
299 sethi %hi(1 << 23), %g1 ! Inexact
301 bne,pn %xcc, do_fptrap_after_fsr
303 lduwa [%g1] ASI_AIUP, %g3 ! This cannot ever fail
304 #define FITOS_MASK 0xc1f83fe0
305 #define FITOS_COMPARE 0x81a01880
306 sethi %hi(FITOS_MASK), %g1
307 or %g1, %lo(FITOS_MASK), %g1
309 sethi %hi(FITOS_COMPARE), %g2
310 or %g2, %lo(FITOS_COMPARE), %g2
312 bne,pn %xcc, do_fptrap_after_fsr
314 std %f62, [%g6 + TI_FPREGS + (62 * 4)]
315 sethi %hi(fitos_table_1), %g1
317 or %g1, %lo(fitos_table_1), %g1
320 ba,pt %xcc, fitos_emul_continue
357 sethi %hi(fitos_table_2), %g1
359 or %g1, %lo(fitos_table_2), %g1
363 ba,pt %xcc, fitos_emul_fini
400 ldd [%g6 + TI_FPREGS + (62 * 4)], %f62
406 stx %fsr, [%g6 + TI_XFSR]
408 ldub [%g6 + TI_FPSAVED], %g3
411 stb %g3, [%g6 + TI_FPSAVED]
413 stx %g3, [%g6 + TI_GSR]
414 mov SECONDARY_CONTEXT, %g3
415 add %g6, TI_FPREGS, %g2
416 ldxa [%g3] ASI_DMMU, %g5
417 stxa %g0, [%g3] ASI_DMMU
419 andcc %g1, FPRS_DL, %g0
422 stda %f0, [%g2] ASI_BLK_S
423 stda %f16, [%g2 + %g3] ASI_BLK_S
424 andcc %g1, FPRS_DU, %g0
427 stda %f32, [%g2] ASI_BLK_S
428 stda %f48, [%g2 + %g3] ASI_BLK_S
429 5: mov SECONDARY_CONTEXT, %g1
431 stxa %g5, [%g1] ASI_DMMU
436 /* The registers for cross calls will be:
438 * DATA 0: [low 32-bits] Address of function to call, jmp to this
439 * [high 32-bits] MMU Context Argument 0, place in %g5
440 * DATA 1: Address Argument 1, place in %g6
441 * DATA 2: Address Argument 2, place in %g7
443 * With this method we can do most of the cross-call tlb/cache
444 * flushing very quickly.
446 * Current CPU's IRQ worklist table is locked into %g1,
454 ldxa [%g3 + %g0] ASI_INTR_R, %g3
455 sethi %hi(KERNBASE), %g4
457 bgeu,pn %xcc, do_ivec_xcall
459 stxa %g0, [%g0] ASI_INTR_RECEIVE
462 sethi %hi(ivector_table), %g2
464 or %g2, %lo(ivector_table), %g2
466 ldx [%g3 + 0x08], %g2 /* irq_info */
467 ldub [%g3 + 0x04], %g4 /* pil */
468 brz,pn %g2, do_ivec_spurious
473 lduw [%g6 + %g4], %g5 /* g5 = irq_work(cpu, pil) */
474 stw %g5, [%g3 + 0x00] /* bucket->irq_chain = g5 */
475 stw %g3, [%g6 + %g4] /* irq_work(cpu, pil) = bucket */
476 wr %g2, 0x0, %set_softint
481 ldxa [%g1 + %g0] ASI_INTR_R, %g1
484 ldxa [%g7 + %g0] ASI_INTR_R, %g7
485 stxa %g0, [%g0] ASI_INTR_RECEIVE
495 stw %g3, [%g6 + 0x00] /* irq_work(cpu, 0) = bucket */
498 wrpr %g5, PSTATE_IG | PSTATE_AG, %pstate
501 109: or %g7, %lo(109b), %g7
502 call catch_disabled_ivec
503 add %sp, PTREGS_OFF, %o0
507 .globl save_alternate_globals
508 save_alternate_globals: /* %o0 = save_area */
510 andn %o5, PSTATE_IE, %o1
511 wrpr %o1, PSTATE_AG, %pstate
512 stx %g0, [%o0 + 0x00]
513 stx %g1, [%o0 + 0x08]
514 stx %g2, [%o0 + 0x10]
515 stx %g3, [%o0 + 0x18]
516 stx %g4, [%o0 + 0x20]
517 stx %g5, [%o0 + 0x28]
518 stx %g6, [%o0 + 0x30]
519 stx %g7, [%o0 + 0x38]
520 wrpr %o1, PSTATE_IG, %pstate
521 stx %g0, [%o0 + 0x40]
522 stx %g1, [%o0 + 0x48]
523 stx %g2, [%o0 + 0x50]
524 stx %g3, [%o0 + 0x58]
525 stx %g4, [%o0 + 0x60]
526 stx %g5, [%o0 + 0x68]
527 stx %g6, [%o0 + 0x70]
528 stx %g7, [%o0 + 0x78]
529 wrpr %o1, PSTATE_MG, %pstate
530 stx %g0, [%o0 + 0x80]
531 stx %g1, [%o0 + 0x88]
532 stx %g2, [%o0 + 0x90]
533 stx %g3, [%o0 + 0x98]
534 stx %g4, [%o0 + 0xa0]
535 stx %g5, [%o0 + 0xa8]
536 stx %g6, [%o0 + 0xb0]
537 stx %g7, [%o0 + 0xb8]
538 wrpr %o5, 0x0, %pstate
542 .globl restore_alternate_globals
543 restore_alternate_globals: /* %o0 = save_area */
545 andn %o5, PSTATE_IE, %o1
546 wrpr %o1, PSTATE_AG, %pstate
547 ldx [%o0 + 0x00], %g0
548 ldx [%o0 + 0x08], %g1
549 ldx [%o0 + 0x10], %g2
550 ldx [%o0 + 0x18], %g3
551 ldx [%o0 + 0x20], %g4
552 ldx [%o0 + 0x28], %g5
553 ldx [%o0 + 0x30], %g6
554 ldx [%o0 + 0x38], %g7
555 wrpr %o1, PSTATE_IG, %pstate
556 ldx [%o0 + 0x40], %g0
557 ldx [%o0 + 0x48], %g1
558 ldx [%o0 + 0x50], %g2
559 ldx [%o0 + 0x58], %g3
560 ldx [%o0 + 0x60], %g4
561 ldx [%o0 + 0x68], %g5
562 ldx [%o0 + 0x70], %g6
563 ldx [%o0 + 0x78], %g7
564 wrpr %o1, PSTATE_MG, %pstate
565 ldx [%o0 + 0x80], %g0
566 ldx [%o0 + 0x88], %g1
567 ldx [%o0 + 0x90], %g2
568 ldx [%o0 + 0x98], %g3
569 ldx [%o0 + 0xa0], %g4
570 ldx [%o0 + 0xa8], %g5
571 ldx [%o0 + 0xb0], %g6
572 ldx [%o0 + 0xb8], %g7
573 wrpr %o5, 0x0, %pstate
579 ldx [%o0 + PT_V9_TSTATE], %o1
583 stx %o1, [%o0 + PT_V9_G1]
585 ldx [%o0 + PT_V9_TSTATE], %o1
586 ldx [%o0 + PT_V9_G1], %o2
587 or %g0, %ulo(TSTATE_ICC), %o3
594 stx %o1, [%o0 + PT_V9_TSTATE]
596 .globl utrap, utrap_ill
597 utrap: brz,pn %g1, etrap
602 andn %l6, TSTATE_CWP, %l6
603 wrpr %l6, %l7, %tstate
610 add %sp, PTREGS_OFF, %o0
614 #ifdef CONFIG_BLK_DEV_FD
615 .globl floppy_hardint
617 wr %g0, (1 << 11), %clear_softint
618 sethi %hi(doing_pdma), %g1
619 ld [%g1 + %lo(doing_pdma)], %g2
620 brz,pn %g2, floppy_dosoftint
621 sethi %hi(fdc_status), %g3
622 ldx [%g3 + %lo(fdc_status)], %g3
623 sethi %hi(pdma_vaddr), %g5
624 ldx [%g5 + %lo(pdma_vaddr)], %g4
625 sethi %hi(pdma_size), %g5
626 ldx [%g5 + %lo(pdma_size)], %g5
629 lduba [%g3] ASI_PHYS_BYPASS_EC_E, %g7
631 be,pn %icc, floppy_fifo_emptied
633 be,pn %icc, floppy_overrun
635 be,pn %icc, floppy_write
639 lduba [%g3] ASI_PHYS_BYPASS_EC_E, %g7
643 bne,pn %xcc, next_byte
646 b,pt %xcc, floppy_tdone
653 stba %g7, [%g3] ASI_PHYS_BYPASS_EC_E
655 bne,pn %xcc, next_byte
659 sethi %hi(pdma_vaddr), %g1
660 stx %g4, [%g1 + %lo(pdma_vaddr)]
661 sethi %hi(pdma_size), %g1
662 stx %g5, [%g1 + %lo(pdma_size)]
663 sethi %hi(auxio_register), %g1
664 ldx [%g1 + %lo(auxio_register)], %g7
665 lduba [%g7] ASI_PHYS_BYPASS_EC_E, %g5
666 or %g5, AUXIO_AUX1_FTCNT, %g5
667 /* andn %g5, AUXIO_AUX1_MASK, %g5 */
668 stba %g5, [%g7] ASI_PHYS_BYPASS_EC_E
669 andn %g5, AUXIO_AUX1_FTCNT, %g5
670 /* andn %g5, AUXIO_AUX1_MASK, %g5 */
672 nop; nop; nop; nop; nop; nop;
673 nop; nop; nop; nop; nop; nop;
675 stba %g5, [%g7] ASI_PHYS_BYPASS_EC_E
676 sethi %hi(doing_pdma), %g1
677 b,pt %xcc, floppy_dosoftint
678 st %g0, [%g1 + %lo(doing_pdma)]
681 sethi %hi(pdma_vaddr), %g1
682 stx %g4, [%g1 + %lo(pdma_vaddr)]
683 sethi %hi(pdma_size), %g1
684 stx %g5, [%g1 + %lo(pdma_size)]
685 sethi %hi(irq_action), %g1
686 or %g1, %lo(irq_action), %g1
687 ldx [%g1 + (11 << 3)], %g3 ! irqaction[floppy_irq]
688 ldx [%g3 + 0x08], %g4 ! action->flags>>48==ino
689 sethi %hi(ivector_table), %g3
691 or %g3, %lo(ivector_table), %g3
693 ldx [%g3 + %g4], %g4 ! &ivector_table[ino]
694 ldx [%g4 + 0x10], %g4 ! bucket->iclr
695 stwa %g0, [%g4] ASI_PHYS_BYPASS_EC_E ! ICLR_IDLE
696 membar #Sync ! probably not needed...
700 sethi %hi(pdma_vaddr), %g1
701 stx %g4, [%g1 + %lo(pdma_vaddr)]
702 sethi %hi(pdma_size), %g1
703 stx %g5, [%g1 + %lo(pdma_size)]
704 sethi %hi(doing_pdma), %g1
705 st %g0, [%g1 + %lo(doing_pdma)]
712 109: or %g7, %lo(109b), %g7
716 call sparc_floppy_irq
717 add %sp, PTREGS_OFF, %o2
722 #endif /* CONFIG_BLK_DEV_FD */
724 /* XXX Here is stuff we still need to write... -DaveM XXX */
725 .globl netbsd_syscall
730 /* These next few routines must be sure to clear the
731 * SFSR FaultValid bit so that the fast tlb data protection
732 * handler does not flush the wrong context and lock up the
735 .globl __do_data_access_exception
736 .globl __do_data_access_exception_tl1
737 __do_data_access_exception_tl1:
739 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
742 ldxa [%g3] ASI_DMMU, %g4 ! Get SFSR
743 ldxa [%g5] ASI_DMMU, %g5 ! Get SFAR
744 stxa %g0, [%g3] ASI_DMMU ! Clear SFSR.FaultValid bit
746 ba,pt %xcc, winfix_dax
748 __do_data_access_exception:
750 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
753 ldxa [%g3] ASI_DMMU, %g4 ! Get SFSR
754 ldxa [%g5] ASI_DMMU, %g5 ! Get SFAR
755 stxa %g0, [%g3] ASI_DMMU ! Clear SFSR.FaultValid bit
759 109: or %g7, %lo(109b), %g7
762 call data_access_exception
763 add %sp, PTREGS_OFF, %o0
767 .globl __do_instruction_access_exception
768 .globl __do_instruction_access_exception_tl1
769 __do_instruction_access_exception_tl1:
771 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
774 ldxa [%g3] ASI_DMMU, %g4 ! Get SFSR
775 ldxa [%g5] ASI_DMMU, %g5 ! Get SFAR
776 stxa %g0, [%g3] ASI_IMMU ! Clear FaultValid bit
780 109: or %g7, %lo(109b), %g7
783 call instruction_access_exception_tl1
784 add %sp, PTREGS_OFF, %o0
788 __do_instruction_access_exception:
790 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
793 ldxa [%g3] ASI_DMMU, %g4 ! Get SFSR
794 ldxa [%g5] ASI_DMMU, %g5 ! Get SFAR
795 stxa %g0, [%g3] ASI_IMMU ! Clear FaultValid bit
799 109: or %g7, %lo(109b), %g7
802 call instruction_access_exception
803 add %sp, PTREGS_OFF, %o0
807 /* This is the trap handler entry point for ECC correctable
808 * errors. They are corrected, but we listen for the trap
809 * so that the event can be logged.
811 * Disrupting errors are either:
812 * 1) single-bit ECC errors during UDB reads to system
814 * 2) data parity errors during write-back events
816 * As far as I can make out from the manual, the CEE trap
817 * is only for correctable errors during memory read
818 * accesses by the front-end of the processor.
820 * The code below is only for trap level 1 CEE events,
821 * as it is the only situation where we can safely record
822 * and log. For trap level >1 we just clear the CE bit
823 * in the AFSR and return.
826 /* Our trap handling infrastructure allows us to preserve
827 * two 64-bit values during etrap for arguments to
828 * subsequent C code. Therefore we encode the information
831 * value 1) Full 64-bits of AFAR
832 * value 2) Low 33-bits of AFSR, then bits 33-->42
833 * are UDBL error status and bits 43-->52
834 * are UDBH error status
839 ldxa [%g0] ASI_AFSR, %g1 ! Read AFSR
840 ldxa [%g0] ASI_AFAR, %g2 ! Read AFAR
841 sllx %g1, 31, %g1 ! Clear reserved bits
842 srlx %g1, 31, %g1 ! in AFSR
844 /* NOTE: UltraSparc-I/II have high and low UDB error
845 * registers, corresponding to the two UDB units
846 * present on those chips. UltraSparc-IIi only
847 * has a single UDB, called "SDB" in the manual.
848 * For IIi the upper UDB register always reads
849 * as zero so for our purposes things will just
850 * work with the checks below.
852 ldxa [%g0] ASI_UDBL_ERROR_R, %g3 ! Read UDB-Low error status
853 andcc %g3, (1 << 8), %g4 ! Check CE bit
854 sllx %g3, (64 - 10), %g3 ! Clear reserved bits
855 srlx %g3, (64 - 10), %g3 ! in UDB-Low error status
857 sllx %g3, (33 + 0), %g3 ! Shift up to encoding area
858 or %g1, %g3, %g1 ! Or it in
859 be,pn %xcc, 1f ! Branch if CE bit was clear
861 stxa %g4, [%g0] ASI_UDB_ERROR_W ! Clear CE sticky bit in UDBL
862 membar #Sync ! Synchronize ASI stores
863 1: mov 0x18, %g5 ! Addr of UDB-High error status
864 ldxa [%g5] ASI_UDBH_ERROR_R, %g3 ! Read it
866 andcc %g3, (1 << 8), %g4 ! Check CE bit
867 sllx %g3, (64 - 10), %g3 ! Clear reserved bits
868 srlx %g3, (64 - 10), %g3 ! in UDB-High error status
869 sllx %g3, (33 + 10), %g3 ! Shift up to encoding area
870 or %g1, %g3, %g1 ! Or it in
871 be,pn %xcc, 1f ! Branch if CE bit was clear
875 stxa %g4, [%g5] ASI_UDB_ERROR_W ! Clear CE sticky bit in UDBH
876 membar #Sync ! Synchronize ASI stores
877 1: mov 1, %g5 ! AFSR CE bit is
878 sllx %g5, 20, %g5 ! bit 20
879 stxa %g5, [%g0] ASI_AFSR ! Clear CE sticky bit in AFSR
880 membar #Sync ! Synchronize ASI stores
881 sllx %g2, (64 - 41), %g2 ! Clear reserved bits
882 srlx %g2, (64 - 41), %g2 ! in latched AFAR
884 andn %g2, 0x0f, %g2 ! Finish resv bit clearing
885 mov %g1, %g4 ! Move AFSR+UDB* into save reg
886 mov %g2, %g5 ! Move AFAR into save reg
889 ba,pt %xcc, etrap_irq
895 add %sp, PTREGS_OFF, %o2
896 ba,a,pt %xcc, rtrap_irq
898 /* Capture I/D/E-cache state into per-cpu error scoreboard.
900 * %g1: (TL>=0) ? 1 : 0
905 * %g6: current thread ptr
908 #define CHEETAH_LOG_ERROR \
909 /* Put "TL1" software bit into AFSR. */ \
913 /* Get log entry pointer for this cpu at this trap level. */ \
914 BRANCH_IF_JALAPENO(g2,g3,50f) \
915 ldxa [%g0] ASI_SAFARI_CONFIG, %g2; \
918 and %g2, 0x3ff, %g2; \
919 50: ldxa [%g0] ASI_JBUS_CONFIG, %g2; \
921 and %g2, 0x1f, %g2; \
922 60: sllx %g2, 9, %g2; \
923 sethi %hi(cheetah_error_log), %g3; \
924 ldx [%g3 + %lo(cheetah_error_log)], %g3; \
930 /* %g1 holds pointer to the top of the logging scoreboard */ \
931 ldx [%g1 + 0x0], %g7; \
935 stx %g4, [%g1 + 0x0]; \
936 stx %g5, [%g1 + 0x8]; \
937 add %g1, 0x10, %g1; \
938 /* %g1 now points to D-cache logging area */ \
939 set 0x3ff8, %g2; /* DC_addr mask */ \
940 and %g5, %g2, %g2; /* DC_addr bits of AFAR */ \
942 or %g3, 1, %g3; /* PHYS tag + valid */ \
943 10: ldxa [%g2] ASI_DCACHE_TAG, %g7; \
944 cmp %g3, %g7; /* TAG match? */ \
947 /* Yep, what we want, capture state. */ \
948 stx %g2, [%g1 + 0x20]; \
949 stx %g7, [%g1 + 0x28]; \
950 /* A membar Sync is required before and after utag access. */ \
952 ldxa [%g2] ASI_DCACHE_UTAG, %g7; \
954 stx %g7, [%g1 + 0x30]; \
955 ldxa [%g2] ASI_DCACHE_SNOOP_TAG, %g7; \
956 stx %g7, [%g1 + 0x38]; \
958 12: ldxa [%g2 + %g3] ASI_DCACHE_DATA, %g7; \
960 add %g3, (1 << 5), %g3; \
965 add %g1, 0x20, %g1; \
966 13: sethi %hi(1 << 14), %g7; \
972 add %g1, 0x40, %g1; \
973 20: /* %g1 now points to I-cache logging area */ \
974 set 0x1fe0, %g2; /* IC_addr mask */ \
975 and %g5, %g2, %g2; /* IC_addr bits of AFAR */ \
976 sllx %g2, 1, %g2; /* IC_addr[13:6]==VA[12:5] */ \
977 srlx %g5, (13 - 8), %g3; /* Make PTAG */ \
978 andn %g3, 0xff, %g3; /* Mask off undefined bits */ \
979 21: ldxa [%g2] ASI_IC_TAG, %g7; \
980 andn %g7, 0xff, %g7; \
984 /* Yep, what we want, capture state. */ \
985 stx %g2, [%g1 + 0x40]; \
986 stx %g7, [%g1 + 0x48]; \
987 add %g2, (1 << 3), %g2; \
988 ldxa [%g2] ASI_IC_TAG, %g7; \
989 add %g2, (1 << 3), %g2; \
990 stx %g7, [%g1 + 0x50]; \
991 ldxa [%g2] ASI_IC_TAG, %g7; \
992 add %g2, (1 << 3), %g2; \
993 stx %g7, [%g1 + 0x60]; \
994 ldxa [%g2] ASI_IC_TAG, %g7; \
995 stx %g7, [%g1 + 0x68]; \
996 sub %g2, (3 << 3), %g2; \
997 ldxa [%g2] ASI_IC_STAG, %g7; \
998 stx %g7, [%g1 + 0x58]; \
1001 22: ldxa [%g2 + %g3] ASI_IC_INSTR, %g7; \
1003 add %g3, (1 << 3), %g3; \
1004 cmp %g3, (8 << 3); \
1006 add %g1, 0x8, %g1; \
1008 add %g1, 0x30, %g1; \
1009 23: sethi %hi(1 << 14), %g7; \
1010 add %g2, %g7, %g2; \
1011 srlx %g2, 14, %g7; \
1015 add %g1, 0x70, %g1; \
1016 30: /* %g1 now points to E-cache logging area */ \
1017 andn %g5, (32 - 1), %g2; /* E-cache subblock */ \
1018 stx %g2, [%g1 + 0x20]; \
1019 ldxa [%g2] ASI_EC_TAG_DATA, %g7; \
1020 stx %g7, [%g1 + 0x28]; \
1021 ldxa [%g2] ASI_EC_R, %g0; \
1023 31: ldxa [%g3] ASI_EC_DATA, %g7; \
1024 stx %g7, [%g1 + %g3]; \
1025 add %g3, 0x8, %g3; \
1031 /* These get patched into the trap table at boot time
1032 * once we know we have a cheetah processor.
1034 .globl cheetah_fecc_trap_vector, cheetah_fecc_trap_vector_tl1
1035 cheetah_fecc_trap_vector:
1037 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
1038 andn %g1, DCU_DC | DCU_IC, %g1
1039 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
1041 sethi %hi(cheetah_fast_ecc), %g2
1042 jmpl %g2 + %lo(cheetah_fast_ecc), %g0
1044 cheetah_fecc_trap_vector_tl1:
1046 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
1047 andn %g1, DCU_DC | DCU_IC, %g1
1048 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
1050 sethi %hi(cheetah_fast_ecc), %g2
1051 jmpl %g2 + %lo(cheetah_fast_ecc), %g0
1053 .globl cheetah_cee_trap_vector, cheetah_cee_trap_vector_tl1
1054 cheetah_cee_trap_vector:
1056 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
1057 andn %g1, DCU_IC, %g1
1058 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
1060 sethi %hi(cheetah_cee), %g2
1061 jmpl %g2 + %lo(cheetah_cee), %g0
1063 cheetah_cee_trap_vector_tl1:
1065 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
1066 andn %g1, DCU_IC, %g1
1067 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
1069 sethi %hi(cheetah_cee), %g2
1070 jmpl %g2 + %lo(cheetah_cee), %g0
1072 .globl cheetah_deferred_trap_vector, cheetah_deferred_trap_vector_tl1
1073 cheetah_deferred_trap_vector:
1075 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1;
1076 andn %g1, DCU_DC | DCU_IC, %g1;
1077 stxa %g1, [%g0] ASI_DCU_CONTROL_REG;
1079 sethi %hi(cheetah_deferred_trap), %g2
1080 jmpl %g2 + %lo(cheetah_deferred_trap), %g0
1082 cheetah_deferred_trap_vector_tl1:
1084 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1;
1085 andn %g1, DCU_DC | DCU_IC, %g1;
1086 stxa %g1, [%g0] ASI_DCU_CONTROL_REG;
1088 sethi %hi(cheetah_deferred_trap), %g2
1089 jmpl %g2 + %lo(cheetah_deferred_trap), %g0
1092 /* Cheetah+ specific traps. These are for the new I/D cache parity
1093 * error traps. The first argument to cheetah_plus_parity_handler
1094 * is encoded as follows:
1096 * Bit0: 0=dcache,1=icache
1097 * Bit1: 0=recoverable,1=unrecoverable
1099 .globl cheetah_plus_dcpe_trap_vector, cheetah_plus_dcpe_trap_vector_tl1
1100 cheetah_plus_dcpe_trap_vector:
1102 sethi %hi(do_cheetah_plus_data_parity), %g7
1103 jmpl %g7 + %lo(do_cheetah_plus_data_parity), %g0
1110 do_cheetah_plus_data_parity:
1114 call cheetah_plus_parity_error
1115 add %sp, PTREGS_OFF, %o1
1119 cheetah_plus_dcpe_trap_vector_tl1:
1121 wrpr PSTATE_IG | PSTATE_PEF | PSTATE_PRIV, %pstate
1122 sethi %hi(do_dcpe_tl1), %g3
1123 jmpl %g3 + %lo(do_dcpe_tl1), %g0
1129 .globl cheetah_plus_icpe_trap_vector, cheetah_plus_icpe_trap_vector_tl1
1130 cheetah_plus_icpe_trap_vector:
1132 sethi %hi(do_cheetah_plus_insn_parity), %g7
1133 jmpl %g7 + %lo(do_cheetah_plus_insn_parity), %g0
1140 do_cheetah_plus_insn_parity:
1144 call cheetah_plus_parity_error
1145 add %sp, PTREGS_OFF, %o1
1149 cheetah_plus_icpe_trap_vector_tl1:
1151 wrpr PSTATE_IG | PSTATE_PEF | PSTATE_PRIV, %pstate
1152 sethi %hi(do_icpe_tl1), %g3
1153 jmpl %g3 + %lo(do_icpe_tl1), %g0
1159 /* If we take one of these traps when tl >= 1, then we
1160 * jump to interrupt globals. If some trap level above us
1161 * was also using interrupt globals, we cannot recover.
1162 * We may use all interrupt global registers except %g6.
1164 .globl do_dcpe_tl1, do_icpe_tl1
1166 rdpr %tl, %g1 ! Save original trap level
1167 mov 1, %g2 ! Setup TSTATE checking loop
1168 sethi %hi(TSTATE_IG), %g3 ! TSTATE mask bit
1169 1: wrpr %g2, %tl ! Set trap level to check
1170 rdpr %tstate, %g4 ! Read TSTATE for this level
1171 andcc %g4, %g3, %g0 ! Interrupt globals in use?
1172 bne,a,pn %xcc, do_dcpe_tl1_fatal ! Yep, irrecoverable
1173 wrpr %g1, %tl ! Restore original trap level
1174 add %g2, 1, %g2 ! Next trap level
1175 cmp %g2, %g1 ! Hit them all yet?
1176 ble,pt %icc, 1b ! Not yet
1178 wrpr %g1, %tl ! Restore original trap level
1179 do_dcpe_tl1_nonfatal: /* Ok we may use interrupt globals safely. */
1180 /* Reset D-cache parity */
1181 sethi %hi(1 << 16), %g1 ! D-cache size
1182 mov (1 << 5), %g2 ! D-cache line size
1183 sub %g1, %g2, %g1 ! Move down 1 cacheline
1184 1: srl %g1, 14, %g3 ! Compute UTAG
1186 stxa %g3, [%g1] ASI_DCACHE_UTAG
1188 sub %g2, 8, %g3 ! 64-bit data word within line
1190 stxa %g0, [%g1 + %g3] ASI_DCACHE_DATA
1192 subcc %g3, 8, %g3 ! Next 64-bit data word
1195 subcc %g1, %g2, %g1 ! Next cacheline
1198 ba,pt %xcc, dcpe_icpe_tl1_common
1203 ba,pt %xcc, etraptl1
1204 1: or %g7, %lo(1b), %g7
1206 call cheetah_plus_parity_error
1207 add %sp, PTREGS_OFF, %o1
1212 rdpr %tl, %g1 ! Save original trap level
1213 mov 1, %g2 ! Setup TSTATE checking loop
1214 sethi %hi(TSTATE_IG), %g3 ! TSTATE mask bit
1215 1: wrpr %g2, %tl ! Set trap level to check
1216 rdpr %tstate, %g4 ! Read TSTATE for this level
1217 andcc %g4, %g3, %g0 ! Interrupt globals in use?
1218 bne,a,pn %xcc, do_icpe_tl1_fatal ! Yep, irrecoverable
1219 wrpr %g1, %tl ! Restore original trap level
1220 add %g2, 1, %g2 ! Next trap level
1221 cmp %g2, %g1 ! Hit them all yet?
1222 ble,pt %icc, 1b ! Not yet
1224 wrpr %g1, %tl ! Restore original trap level
1225 do_icpe_tl1_nonfatal: /* Ok we may use interrupt globals safely. */
1227 sethi %hi(1 << 15), %g1 ! I-cache size
1228 mov (1 << 5), %g2 ! I-cache line size
1230 1: or %g1, (2 << 3), %g3
1231 stxa %g0, [%g3] ASI_IC_TAG
1236 ba,pt %xcc, dcpe_icpe_tl1_common
1241 ba,pt %xcc, etraptl1
1242 1: or %g7, %lo(1b), %g7
1244 call cheetah_plus_parity_error
1245 add %sp, PTREGS_OFF, %o1
1249 dcpe_icpe_tl1_common:
1250 /* Flush D-cache, re-enable D/I caches in DCU and finally
1251 * retry the trapping instruction.
1253 sethi %hi(1 << 16), %g1 ! D-cache size
1254 mov (1 << 5), %g2 ! D-cache line size
1256 1: stxa %g0, [%g1] ASI_DCACHE_TAG
1261 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
1262 or %g1, (DCU_DC | DCU_IC), %g1
1263 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
1267 /* Cheetah FECC trap handling, we get here from tl{0,1}_fecc
1268 * in the trap table. That code has done a memory barrier
1269 * and has disabled both the I-cache and D-cache in the DCU
1270 * control register. The I-cache is disabled so that we may
1271 * capture the corrupted cache line, and the D-cache is disabled
1272 * because corrupt data may have been placed there and we don't
1273 * want to reference it.
1275 * %g1 is one if this trap occurred at %tl >= 1.
1277 * Next, we turn off error reporting so that we don't recurse.
1279 .globl cheetah_fast_ecc
1281 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2
1282 andn %g2, ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN, %g2
1283 stxa %g2, [%g0] ASI_ESTATE_ERROR_EN
1286 /* Fetch and clear AFSR/AFAR */
1287 ldxa [%g0] ASI_AFSR, %g4
1288 ldxa [%g0] ASI_AFAR, %g5
1289 stxa %g4, [%g0] ASI_AFSR
1296 ba,pt %xcc, etrap_irq
1300 call cheetah_fecc_handler
1301 add %sp, PTREGS_OFF, %o0
1302 ba,a,pt %xcc, rtrap_irq
1304 /* Our caller has disabled I-cache and performed membar Sync. */
1307 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2
1308 andn %g2, ESTATE_ERROR_CEEN, %g2
1309 stxa %g2, [%g0] ASI_ESTATE_ERROR_EN
1312 /* Fetch and clear AFSR/AFAR */
1313 ldxa [%g0] ASI_AFSR, %g4
1314 ldxa [%g0] ASI_AFAR, %g5
1315 stxa %g4, [%g0] ASI_AFSR
1322 ba,pt %xcc, etrap_irq
1326 call cheetah_cee_handler
1327 add %sp, PTREGS_OFF, %o0
1328 ba,a,pt %xcc, rtrap_irq
1330 /* Our caller has disabled I-cache+D-cache and performed membar Sync. */
1331 .globl cheetah_deferred_trap
1332 cheetah_deferred_trap:
1333 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2
1334 andn %g2, ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN, %g2
1335 stxa %g2, [%g0] ASI_ESTATE_ERROR_EN
1338 /* Fetch and clear AFSR/AFAR */
1339 ldxa [%g0] ASI_AFSR, %g4
1340 ldxa [%g0] ASI_AFAR, %g5
1341 stxa %g4, [%g0] ASI_AFSR
1348 ba,pt %xcc, etrap_irq
1352 call cheetah_deferred_handler
1353 add %sp, PTREGS_OFF, %o0
1354 ba,a,pt %xcc, rtrap_irq
1359 stxa %g0, [%g3] ASI_DMMU ! Clear FaultValid bit
1361 sethi %hi(109f), %g7
1363 109: or %g7, %lo(109b), %g7
1365 add %sp, PTREGS_OFF, %o0
1374 /* Setup %g4/%g5 now as they are used in the
1379 ldxa [%g4] ASI_DMMU, %g4
1380 ldxa [%g3] ASI_DMMU, %g5
1381 stxa %g0, [%g3] ASI_DMMU ! Clear FaultValid bit
1383 bgu,pn %icc, winfix_mna
1386 1: sethi %hi(109f), %g7
1388 109: or %g7, %lo(109b), %g7
1391 call mem_address_unaligned
1392 add %sp, PTREGS_OFF, %o0
1398 sethi %hi(109f), %g7
1400 ldxa [%g4] ASI_DMMU, %g5
1401 stxa %g0, [%g4] ASI_DMMU ! Clear FaultValid bit
1404 ldxa [%g4] ASI_DMMU, %g4
1406 109: or %g7, %lo(109b), %g7
1410 add %sp, PTREGS_OFF, %o0
1416 sethi %hi(109f), %g7
1418 ldxa [%g4] ASI_DMMU, %g5
1419 stxa %g0, [%g4] ASI_DMMU ! Clear FaultValid bit
1422 ldxa [%g4] ASI_DMMU, %g4
1424 109: or %g7, %lo(109b), %g7
1428 add %sp, PTREGS_OFF, %o0
1432 .globl breakpoint_trap
1434 call sparc_breakpoint
1435 add %sp, PTREGS_OFF, %o0
1439 #if defined(CONFIG_SUNOS_EMUL) || defined(CONFIG_SOLARIS_EMUL) || \
1440 defined(CONFIG_SOLARIS_EMUL_MODULE)
1441 /* SunOS uses syscall zero as the 'indirect syscall' it looks
1442 * like indir_syscall(scall_num, arg0, arg1, arg2...); etc.
1443 * This is complete brain damage.
1449 cmp %o0, NR_SYSCALLS
1452 sethi %hi(sunos_nosys), %l6
1454 or %l6, %lo(sunos_nosys), %l6
1455 1: sethi %hi(sunos_sys_table), %l7
1456 or %l7, %lo(sunos_sys_table), %l7
1457 lduw [%l7 + %o0], %l6
1471 stx %o0, [%sp + PTREGS_OFF + PT_V9_I1]
1472 b,pt %xcc, ret_sys_call
1473 stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
1475 /* SunOS getuid() returns uid in %o0 and euid in %o1 */
1478 call sys32_geteuid16
1481 stx %o0, [%sp + PTREGS_OFF + PT_V9_I1]
1482 b,pt %xcc, ret_sys_call
1483 stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
1485 /* SunOS getgid() returns gid in %o0 and egid in %o1 */
1488 call sys32_getegid16
1491 stx %o0, [%sp + PTREGS_OFF + PT_V9_I1]
1492 b,pt %xcc, ret_sys_call
1493 stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
1496 /* SunOS's execv() call only specifies the argv argument, the
1497 * environment settings are the same as the calling processes.
1499 .globl sunos_execv, sys_execve, sys32_execve
1501 sethi %hi(sparc_execve), %g1
1502 ba,pt %xcc, execve_merge
1503 or %g1, %lo(sparc_execve), %g1
1505 stx %g0, [%sp + PTREGS_OFF + PT_V9_I2]
1507 sethi %hi(sparc32_execve), %g1
1508 or %g1, %lo(sparc32_execve), %g1
1512 add %sp, PTREGS_OFF, %o0
1514 .globl sys_pipe, sys_sigpause, sys_nis_syscall
1515 .globl sys_sigsuspend, sys_rt_sigsuspend, sys32_rt_sigsuspend
1516 .globl sys_rt_sigreturn
1517 .globl sys32_sigreturn, sys32_rt_sigreturn
1518 .globl sys32_execve, sys_ptrace
1519 .globl sys_sigaltstack, sys32_sigaltstack
1520 .globl sys32_sigstack
1522 sys_pipe: ba,pt %xcc, sparc_pipe
1523 add %sp, PTREGS_OFF, %o0
1524 sys_nis_syscall:ba,pt %xcc, c_sys_nis_syscall
1525 add %sp, PTREGS_OFF, %o0
1526 sys_memory_ordering:
1527 ba,pt %xcc, sparc_memory_ordering
1528 add %sp, PTREGS_OFF, %o1
1529 sys_sigaltstack:ba,pt %xcc, do_sigaltstack
1530 add %i6, STACK_BIAS, %o2
1531 sys32_sigstack: ba,pt %xcc, do_sys32_sigstack
1534 ba,pt %xcc, do_sys32_sigaltstack
1538 sys_sigsuspend: add %sp, PTREGS_OFF, %o0
1540 add %o7, 1f-.-4, %o7
1542 sys_rt_sigsuspend: /* NOTE: %o0,%o1 have a correct value already */
1543 add %sp, PTREGS_OFF, %o2
1544 call do_rt_sigsuspend
1545 add %o7, 1f-.-4, %o7
1547 sys32_rt_sigsuspend: /* NOTE: %o0,%o1 have a correct value already */
1549 add %sp, PTREGS_OFF, %o2
1550 call do_rt_sigsuspend32
1551 add %o7, 1f-.-4, %o7
1552 /* NOTE: %o0 has a correct value already */
1553 sys_sigpause: add %sp, PTREGS_OFF, %o1
1555 add %o7, 1f-.-4, %o7
1558 add %sp, PTREGS_OFF, %o0
1560 add %o7, 1f-.-4, %o7
1563 add %sp, PTREGS_OFF, %o0
1564 call do_rt_sigreturn
1565 add %o7, 1f-.-4, %o7
1568 add %sp, PTREGS_OFF, %o0
1569 call do_rt_sigreturn32
1570 add %o7, 1f-.-4, %o7
1572 sys_ptrace: add %sp, PTREGS_OFF, %o0
1574 add %o7, 1f-.-4, %o7
1577 1: ldx [%curptr + TI_FLAGS], %l5
1578 andcc %l5, _TIF_SYSCALL_TRACE, %g0
1587 /* This is how fork() was meant to be done, 8 instruction entry.
1589 * I questioned the following code briefly, let me clear things
1590 * up so you must not reason on it like I did.
1592 * Know the fork_kpsr etc. we use in the sparc32 port? We don't
1593 * need it here because the only piece of window state we copy to
1594 * the child is the CWP register. Even if the parent sleeps,
1595 * we are safe because we stuck it into pt_regs of the parent
1596 * so it will not change.
1598 * XXX This raises the question, whether we can do the same on
1599 * XXX sparc32 to get rid of fork_kpsr _and_ fork_kwim. The
1600 * XXX answer is yes. We stick fork_kpsr in UREG_G0 and
1601 * XXX fork_kwim in UREG_G1 (global registers are considered
1602 * XXX volatile across a system call in the sparc ABI I think
1603 * XXX if it isn't we can use regs->y instead, anyone who depends
1604 * XXX upon the Y register being preserved across a fork deserves
1607 * In fact we should take advantage of that fact for other things
1608 * during system calls...
1610 .globl sys_fork, sys_vfork, sys_clone, sparc_exit
1611 .globl ret_from_syscall
1613 sys_vfork: /* Under Linux, vfork and fork are just special cases of clone. */
1614 sethi %hi(0x4000 | 0x0100 | SIGCHLD), %o0
1615 or %o0, %lo(0x4000 | 0x0100 | SIGCHLD), %o0
1616 ba,pt %xcc, sys_clone
1622 ba,pt %xcc, sparc_do_fork
1623 add %sp, PTREGS_OFF, %o2
1625 /* Clear SPARC_FLAG_NEWCHILD, switch_to leaves thread.flags in
1626 * %o7 for us. Check performance counter stuff too.
1628 andn %o7, _TIF_NEWCHILD, %l0
1629 stx %l0, [%g6 + TI_FLAGS]
1632 andcc %l0, _TIF_PERFCTR, %g0
1635 ldx [%g6 + TI_PCR], %o7
1638 /* Blackbird errata workaround. See commentary in
1639 * smp.c:smp_percpu_timer_interrupt() for more
1645 99: wr %g0, %g0, %pic
1648 1: b,pt %xcc, ret_sys_call
1649 ldx [%sp + PTREGS_OFF + PT_V9_I0], %o0
1650 sparc_exit: wrpr %g0, (PSTATE_RMO | PSTATE_PEF | PSTATE_PRIV), %pstate
1654 wrpr %g3, 0x0, %cansave
1655 wrpr %g0, 0x0, %otherwin
1656 wrpr %g0, (PSTATE_RMO | PSTATE_PEF | PSTATE_PRIV | PSTATE_IE), %pstate
1657 ba,pt %xcc, sys_exit
1658 stb %g0, [%g6 + TI_WSAVED]
1660 linux_sparc_ni_syscall:
1661 sethi %hi(sys_ni_syscall), %l7
1663 or %l7, %lo(sys_ni_syscall), %l7
1665 linux_syscall_trace32:
1675 linux_syscall_trace:
1686 /* Linux 32-bit and SunOS system calls enter here... */
1688 .globl linux_sparc_syscall32
1689 linux_sparc_syscall32:
1690 /* Direct access to user regs, much faster. */
1691 cmp %g1, NR_SYSCALLS ! IEU1 Group
1692 bgeu,pn %xcc, linux_sparc_ni_syscall ! CTI
1693 srl %i0, 0, %o0 ! IEU0
1694 sll %g1, 2, %l4 ! IEU0 Group
1695 #ifdef SYSCALL_TRACING
1696 call syscall_trace_entry
1697 add %sp, PTREGS_OFF, %o0
1700 srl %i4, 0, %o4 ! IEU1
1701 lduw [%l7 + %l4], %l7 ! Load
1702 srl %i1, 0, %o1 ! IEU0 Group
1703 ldx [%curptr + TI_FLAGS], %l0 ! Load
1705 srl %i5, 0, %o5 ! IEU1
1706 srl %i2, 0, %o2 ! IEU0 Group
1707 andcc %l0, _TIF_SYSCALL_TRACE, %g0 ! IEU0 Group
1708 bne,pn %icc, linux_syscall_trace32 ! CTI
1710 call %l7 ! CTI Group brk forced
1711 srl %i3, 0, %o3 ! IEU0
1714 /* Linux native and SunOS system calls enter here... */
1716 .globl linux_sparc_syscall, ret_sys_call
1717 linux_sparc_syscall:
1718 /* Direct access to user regs, much faster. */
1719 cmp %g1, NR_SYSCALLS ! IEU1 Group
1720 bgeu,pn %xcc, linux_sparc_ni_syscall ! CTI
1722 sll %g1, 2, %l4 ! IEU0 Group
1723 #ifdef SYSCALL_TRACING
1724 call syscall_trace_entry
1725 add %sp, PTREGS_OFF, %o0
1729 lduw [%l7 + %l4], %l7 ! Load
1730 4: mov %i2, %o2 ! IEU0 Group
1731 ldx [%curptr + TI_FLAGS], %l0 ! Load
1734 mov %i4, %o4 ! IEU0 Group
1735 andcc %l0, _TIF_SYSCALL_TRACE, %g0 ! IEU1 Group+1 bubble
1736 bne,pn %icc, linux_syscall_trace ! CTI Group
1738 2: call %l7 ! CTI Group brk forced
1742 3: stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
1744 #ifdef SYSCALL_TRACING
1746 call syscall_trace_exit
1747 add %sp, PTREGS_OFF, %o0
1750 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %g3
1751 ldx [%sp + PTREGS_OFF + PT_V9_TNPC], %l1 ! pc = npc
1753 mov %ulo(TSTATE_XCARRY | TSTATE_ICARRY), %g2
1754 cmp %o0, -ENOIOCTLCMD
1757 andcc %l0, _TIF_SYSCALL_TRACE, %l6
1759 andn %g3, %g2, %g3 /* System call success, clear Carry condition code. */
1760 stx %g3, [%sp + PTREGS_OFF + PT_V9_TSTATE]
1761 bne,pn %icc, linux_syscall_trace2
1762 add %l1, 0x4, %l2 ! npc = npc+4
1763 stx %l1, [%sp + PTREGS_OFF + PT_V9_TPC]
1764 ba,pt %xcc, rtrap_clr_l6
1765 stx %l2, [%sp + PTREGS_OFF + PT_V9_TNPC]
1768 /* Really a failure? Check if force_successful_syscall_return()
1771 ldx [%curptr + TI_FLAGS], %l0 ! Load
1772 andcc %l0, _TIF_SYSCALL_SUCCESS, %g0
1774 andcc %l0, _TIF_SYSCALL_TRACE, %l6
1775 andn %l0, _TIF_SYSCALL_SUCCESS, %l0
1777 stx %l0, [%curptr + TI_FLAGS]
1779 /* System call failure, set Carry condition code.
1780 * Also, get abs(errno) to return to the process.
1785 stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
1787 stx %g3, [%sp + PTREGS_OFF + PT_V9_TSTATE]
1788 bne,pn %icc, linux_syscall_trace2
1789 add %l1, 0x4, %l2 !npc = npc+4
1790 stx %l1, [%sp + PTREGS_OFF + PT_V9_TPC]
1793 stx %l2, [%sp + PTREGS_OFF + PT_V9_TNPC]
1794 linux_syscall_trace2:
1797 stx %l1, [%sp + PTREGS_OFF + PT_V9_TPC]
1799 stx %l2, [%sp + PTREGS_OFF + PT_V9_TNPC]
1802 .globl __flushw_user
1807 1: save %sp, -128, %sp
1813 restore %g0, %g0, %g0