2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/irq.h>
25 #include <linux/interrupt.h>
26 #include <linux/init.h>
27 #include <linux/delay.h>
28 #include <linux/sched.h>
29 #include <linux/config.h>
30 #include <linux/smp_lock.h>
31 #include <linux/mc146818rtc.h>
32 #include <linux/acpi.h>
37 #include <asm/proto.h>
39 int sis_apic_bug; /* not actually supported, dummy for compile */
41 #undef APIC_LOCKUP_DEBUG
43 #define APIC_LOCKUP_DEBUG
45 static spinlock_t ioapic_lock = SPIN_LOCK_UNLOCKED;
48 * # of IRQ routing registers
50 int nr_ioapic_registers[MAX_IO_APICS];
53 * Rough estimation of how many shared IRQs there are, can
56 #define MAX_PLUS_SHARED_IRQS NR_IRQS
57 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
60 * This is performance-critical, we want to do it O(1)
62 * the indexing order of this array favors 1:1 mappings
63 * between pins and IRQs.
66 static struct irq_pin_list {
67 short apic, pin, next;
68 } irq_2_pin[PIN_MAP_SIZE];
70 int vector_irq[NR_VECTORS] = { [0 ... NR_VECTORS - 1] = -1};
72 #define vector_to_irq(vector) \
73 (platform_legacy_irq(vector) ? vector : vector_irq[vector])
75 #define vector_to_irq(vector) (vector)
79 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
80 * shared ISA-space IRQs, so we have to support them. We are super
81 * fast in the common case, and fast for shared ISA-space IRQs.
83 static void __init add_pin_to_irq(unsigned int irq, int apic, int pin)
85 static int first_free_entry = NR_IRQS;
86 struct irq_pin_list *entry = irq_2_pin + irq;
89 entry = irq_2_pin + entry->next;
91 if (entry->pin != -1) {
92 entry->next = first_free_entry;
93 entry = irq_2_pin + entry->next;
94 if (++first_free_entry >= PIN_MAP_SIZE)
95 panic("io_apic.c: whoops");
101 #define __DO_ACTION(R, ACTION, FINAL) \
105 struct irq_pin_list *entry = irq_2_pin + irq; \
112 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
114 io_apic_modify(entry->apic, reg); \
117 entry = irq_2_pin + entry->next; \
122 #define DO_ACTION(name,R,ACTION, FINAL) \
124 static void name##_IO_APIC_irq (unsigned int irq) \
125 __DO_ACTION(R, ACTION, FINAL)
127 DO_ACTION( __mask, 0, |= 0x00010000, io_apic_sync(entry->apic) )
129 DO_ACTION( __unmask, 0, &= 0xfffeffff, )
131 DO_ACTION( __mask_and_edge, 0, = (reg & 0xffff7fff) | 0x00010000, )
132 /* mask = 1, trigger = 0 */
133 DO_ACTION( __unmask_and_level, 0, = (reg & 0xfffeffff) | 0x00008000, )
134 /* mask = 0, trigger = 1 */
136 static void mask_IO_APIC_irq (unsigned int irq)
140 spin_lock_irqsave(&ioapic_lock, flags);
141 __mask_IO_APIC_irq(irq);
142 spin_unlock_irqrestore(&ioapic_lock, flags);
145 static void unmask_IO_APIC_irq (unsigned int irq)
149 spin_lock_irqsave(&ioapic_lock, flags);
150 __unmask_IO_APIC_irq(irq);
151 spin_unlock_irqrestore(&ioapic_lock, flags);
154 void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
156 struct IO_APIC_route_entry entry;
159 /* Check delivery_mode to be sure we're not clearing an SMI pin */
160 spin_lock_irqsave(&ioapic_lock, flags);
161 *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
162 *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
163 spin_unlock_irqrestore(&ioapic_lock, flags);
164 if (entry.delivery_mode == dest_SMI)
167 * Disable it in the IO-APIC irq-routing table:
169 memset(&entry, 0, sizeof(entry));
171 spin_lock_irqsave(&ioapic_lock, flags);
172 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
173 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
174 spin_unlock_irqrestore(&ioapic_lock, flags);
177 static void clear_IO_APIC (void)
181 for (apic = 0; apic < nr_ioapics; apic++)
182 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
183 clear_IO_APIC_pin(apic, pin);
187 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
188 * specific CPU-side IRQs.
192 int pirq_entries [MAX_PIRQS];
194 int skip_ioapic_setup;
197 /* dummy parsing: see setup.c */
199 static int __init disable_ioapic_setup(char *str)
201 skip_ioapic_setup = 1;
205 static int __init enable_ioapic_setup(char *str)
208 skip_ioapic_setup = 0;
212 __setup("noapic", disable_ioapic_setup);
213 __setup("apic", enable_ioapic_setup);
215 #include <asm/pci-direct.h>
216 #include <linux/pci_ids.h>
217 #include <linux/pci.h>
219 /* Temporary Hack. Nvidia and VIA boards currently only work with IO-APIC
220 off. Check for an Nvidia or VIA PCI bridge and turn it off.
221 Use pci direct infrastructure because this runs before the PCI subsystem.
223 Can be overwritten with "apic"
225 And another hack to disable the IOMMU on VIA chipsets.
228 void __init check_ioapic(void)
234 /* Poor man's PCI discovery */
235 for (num = 0; num < 32; num++) {
236 for (slot = 0; slot < 32; slot++) {
237 for (func = 0; func < 8; func++) {
241 class = read_pci_config(num,slot,func,
243 if (class == 0xffffffff)
246 if ((class >> 16) != PCI_CLASS_BRIDGE_PCI)
249 vendor = read_pci_config(num, slot, func,
253 case PCI_VENDOR_ID_VIA:
254 #ifdef CONFIG_GART_IOMMU
255 if ((end_pfn >= (0xffffffff>>PAGE_SHIFT) ||
257 !iommu_aperture_allowed) {
259 "Looks like a VIA chipset. Disabling IOMMU. Overwrite with \"iommu=allowed\"\n");
260 iommu_aperture_disabled = 1;
264 case PCI_VENDOR_ID_NVIDIA:
267 "PCI bridge %02x:%02x from %x found. Setting \"noapic\". Overwrite with \"apic\"\n",
269 skip_ioapic_setup = 1;
274 /* No multi-function device? */
275 type = read_pci_config_byte(num,slot,func,
284 static int __init ioapic_pirq_setup(char *str)
287 int ints[MAX_PIRQS+1];
289 get_options(str, ARRAY_SIZE(ints), ints);
291 for (i = 0; i < MAX_PIRQS; i++)
292 pirq_entries[i] = -1;
295 printk(KERN_INFO "PIRQ redirection, working around broken MP-BIOS.\n");
297 if (ints[0] < MAX_PIRQS)
300 for (i = 0; i < max; i++) {
301 printk(KERN_DEBUG "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
303 * PIRQs are mapped upside down, usually.
305 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
310 __setup("pirq=", ioapic_pirq_setup);
313 * Find the IRQ entry number of a certain pin.
315 static int __init find_irq_entry(int apic, int pin, int type)
319 for (i = 0; i < mp_irq_entries; i++)
320 if (mp_irqs[i].mpc_irqtype == type &&
321 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
322 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
323 mp_irqs[i].mpc_dstirq == pin)
330 * Find the pin to which IRQ[irq] (ISA) is connected
332 static int __init find_isa_irq_pin(int irq, int type)
336 for (i = 0; i < mp_irq_entries; i++) {
337 int lbus = mp_irqs[i].mpc_srcbus;
339 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
340 mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
341 mp_bus_id_to_type[lbus] == MP_BUS_MCA) &&
342 (mp_irqs[i].mpc_irqtype == type) &&
343 (mp_irqs[i].mpc_srcbusirq == irq))
345 return mp_irqs[i].mpc_dstirq;
351 * Find a specific PCI IRQ entry.
352 * Not an __init, possibly needed by modules
354 static int pin_2_irq(int idx, int apic, int pin);
356 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
358 int apic, i, best_guess = -1;
360 Dprintk("querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
362 if (mp_bus_id_to_pci_bus[bus] == -1) {
363 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
366 for (i = 0; i < mp_irq_entries; i++) {
367 int lbus = mp_irqs[i].mpc_srcbus;
369 for (apic = 0; apic < nr_ioapics; apic++)
370 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
371 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
374 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
375 !mp_irqs[i].mpc_irqtype &&
377 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
378 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
380 if (!(apic || IO_APIC_IRQ(irq)))
383 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
386 * Use the first all-but-pin matching entry as a
387 * best-guess fuzzy result for broken mptables.
397 * EISA Edge/Level control register, ELCR
399 static int __init EISA_ELCR(unsigned int irq)
402 unsigned int port = 0x4d0 + (irq >> 3);
403 return (inb(port) >> (irq & 7)) & 1;
405 printk(KERN_INFO "Broken MPtable reports ISA irq %d\n", irq);
409 /* EISA interrupts are always polarity zero and can be edge or level
410 * trigger depending on the ELCR value. If an interrupt is listed as
411 * EISA conforming in the MP table, that means its trigger type must
412 * be read in from the ELCR */
414 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
415 #define default_EISA_polarity(idx) (0)
417 /* ISA interrupts are always polarity zero edge triggered,
418 * when listed as conforming in the MP table. */
420 #define default_ISA_trigger(idx) (0)
421 #define default_ISA_polarity(idx) (0)
423 /* PCI interrupts are always polarity one level triggered,
424 * when listed as conforming in the MP table. */
426 #define default_PCI_trigger(idx) (1)
427 #define default_PCI_polarity(idx) (1)
429 /* MCA interrupts are always polarity zero level triggered,
430 * when listed as conforming in the MP table. */
432 #define default_MCA_trigger(idx) (1)
433 #define default_MCA_polarity(idx) (0)
435 static int __init MPBIOS_polarity(int idx)
437 int bus = mp_irqs[idx].mpc_srcbus;
441 * Determine IRQ line polarity (high active or low active):
443 switch (mp_irqs[idx].mpc_irqflag & 3)
445 case 0: /* conforms, ie. bus-type dependent polarity */
447 switch (mp_bus_id_to_type[bus])
449 case MP_BUS_ISA: /* ISA pin */
451 polarity = default_ISA_polarity(idx);
454 case MP_BUS_EISA: /* EISA pin */
456 polarity = default_EISA_polarity(idx);
459 case MP_BUS_PCI: /* PCI pin */
461 polarity = default_PCI_polarity(idx);
464 case MP_BUS_MCA: /* MCA pin */
466 polarity = default_MCA_polarity(idx);
471 printk(KERN_WARNING "broken BIOS!!\n");
478 case 1: /* high active */
483 case 2: /* reserved */
485 printk(KERN_WARNING "broken BIOS!!\n");
489 case 3: /* low active */
494 default: /* invalid */
496 printk(KERN_WARNING "broken BIOS!!\n");
504 static int __init MPBIOS_trigger(int idx)
506 int bus = mp_irqs[idx].mpc_srcbus;
510 * Determine IRQ trigger mode (edge or level sensitive):
512 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
514 case 0: /* conforms, ie. bus-type dependent */
516 switch (mp_bus_id_to_type[bus])
518 case MP_BUS_ISA: /* ISA pin */
520 trigger = default_ISA_trigger(idx);
523 case MP_BUS_EISA: /* EISA pin */
525 trigger = default_EISA_trigger(idx);
528 case MP_BUS_PCI: /* PCI pin */
530 trigger = default_PCI_trigger(idx);
533 case MP_BUS_MCA: /* MCA pin */
535 trigger = default_MCA_trigger(idx);
540 printk(KERN_WARNING "broken BIOS!!\n");
552 case 2: /* reserved */
554 printk(KERN_WARNING "broken BIOS!!\n");
563 default: /* invalid */
565 printk(KERN_WARNING "broken BIOS!!\n");
573 static inline int irq_polarity(int idx)
575 return MPBIOS_polarity(idx);
578 static inline int irq_trigger(int idx)
580 return MPBIOS_trigger(idx);
583 static int pin_2_irq(int idx, int apic, int pin)
586 int bus = mp_irqs[idx].mpc_srcbus;
589 * Debugging check, we are in big trouble if this message pops up!
591 if (mp_irqs[idx].mpc_dstirq != pin)
592 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
594 switch (mp_bus_id_to_type[bus])
596 case MP_BUS_ISA: /* ISA pin */
600 irq = mp_irqs[idx].mpc_srcbusirq;
603 case MP_BUS_PCI: /* PCI pin */
606 * PCI IRQs are mapped in order
610 irq += nr_ioapic_registers[i++];
616 printk(KERN_ERR "unknown bus type %d.\n",bus);
623 * PCI IRQ command line redirection. Yes, limits are hardcoded.
625 if ((pin >= 16) && (pin <= 23)) {
626 if (pirq_entries[pin-16] != -1) {
627 if (!pirq_entries[pin-16]) {
628 printk(KERN_DEBUG "disabling PIRQ%d\n", pin-16);
630 irq = pirq_entries[pin-16];
631 printk(KERN_DEBUG "using PIRQ%d -> IRQ %d\n",
639 static inline int IO_APIC_irq_trigger(int irq)
643 for (apic = 0; apic < nr_ioapics; apic++) {
644 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
645 idx = find_irq_entry(apic,pin,mp_INT);
646 if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
647 return irq_trigger(idx);
651 * nonexistent IRQs are edge default
656 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
657 u8 irq_vector[NR_IRQ_VECTORS] = { FIRST_DEVICE_VECTOR , 0 };
659 #ifdef CONFIG_PCI_MSI
660 int assign_irq_vector(int irq)
662 int __init assign_irq_vector(int irq)
665 static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
667 BUG_ON(irq >= NR_IRQ_VECTORS);
668 if (IO_APIC_VECTOR(irq) > 0)
669 return IO_APIC_VECTOR(irq);
672 if (current_vector == IA32_SYSCALL_VECTOR)
675 if (current_vector >= FIRST_SYSTEM_VECTOR) {
679 current_vector = FIRST_DEVICE_VECTOR + offset;
682 vector_irq[current_vector] = irq;
683 if (irq != AUTO_ASSIGN)
684 IO_APIC_VECTOR(irq) = current_vector;
686 return current_vector;
689 extern void (*interrupt[NR_IRQS])(void);
690 static struct hw_interrupt_type ioapic_level_type;
691 static struct hw_interrupt_type ioapic_edge_type;
693 #define IOAPIC_AUTO -1
694 #define IOAPIC_EDGE 0
695 #define IOAPIC_LEVEL 1
697 static inline void ioapic_register_intr(int irq, int vector, unsigned long trigger)
699 if (use_pci_vector() && !platform_legacy_irq(irq)) {
700 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
701 trigger == IOAPIC_LEVEL)
702 irq_desc[vector].handler = &ioapic_level_type;
704 irq_desc[vector].handler = &ioapic_edge_type;
705 set_intr_gate(vector, interrupt[vector]);
707 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
708 trigger == IOAPIC_LEVEL)
709 irq_desc[irq].handler = &ioapic_level_type;
711 irq_desc[irq].handler = &ioapic_edge_type;
712 set_intr_gate(vector, interrupt[irq]);
716 void __init setup_IO_APIC_irqs(void)
718 struct IO_APIC_route_entry entry;
719 int apic, pin, idx, irq, first_notcon = 1, vector;
722 printk(KERN_DEBUG "init IO_APIC IRQs\n");
724 for (apic = 0; apic < nr_ioapics; apic++) {
725 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
728 * add it to the IO-APIC irq-routing table:
730 memset(&entry,0,sizeof(entry));
732 entry.delivery_mode = dest_LowestPrio;
733 entry.dest_mode = INT_DELIVERY_MODE;
734 entry.mask = 0; /* enable IRQ */
735 entry.dest.logical.logical_dest = TARGET_CPUS;
737 idx = find_irq_entry(apic,pin,mp_INT);
740 printk(KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
743 printk(", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
747 entry.trigger = irq_trigger(idx);
748 entry.polarity = irq_polarity(idx);
750 if (irq_trigger(idx)) {
753 entry.dest.logical.logical_dest = TARGET_CPUS;
756 irq = pin_2_irq(idx, apic, pin);
757 add_pin_to_irq(irq, apic, pin);
759 if (!apic && !IO_APIC_IRQ(irq))
762 if (IO_APIC_IRQ(irq)) {
763 vector = assign_irq_vector(irq);
764 entry.vector = vector;
766 ioapic_register_intr(irq, vector, IOAPIC_AUTO);
767 if (!apic && (irq < 16))
768 disable_8259A_irq(irq);
770 spin_lock_irqsave(&ioapic_lock, flags);
771 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
772 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
773 spin_unlock_irqrestore(&ioapic_lock, flags);
778 printk(" not connected.\n");
782 * Set up the 8259A-master output pin as broadcast to all
785 void __init setup_ExtINT_IRQ0_pin(unsigned int pin, int vector)
787 struct IO_APIC_route_entry entry;
790 memset(&entry,0,sizeof(entry));
792 disable_8259A_irq(0);
795 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
798 * We use logical delivery to get the timer IRQ
801 entry.dest_mode = INT_DELIVERY_MODE;
802 entry.mask = 0; /* unmask IRQ now */
803 entry.dest.logical.logical_dest = TARGET_CPUS;
804 entry.delivery_mode = dest_LowestPrio;
807 entry.vector = vector;
810 * The timer IRQ doesn't have to know that behind the
811 * scene we have a 8259A-master in AEOI mode ...
813 irq_desc[0].handler = &ioapic_edge_type;
816 * Add it to the IO-APIC irq-routing table:
818 spin_lock_irqsave(&ioapic_lock, flags);
819 io_apic_write(0, 0x11+2*pin, *(((int *)&entry)+1));
820 io_apic_write(0, 0x10+2*pin, *(((int *)&entry)+0));
821 spin_unlock_irqrestore(&ioapic_lock, flags);
826 void __init UNEXPECTED_IO_APIC(void)
829 printk(KERN_WARNING " WARNING: unexpected IO-APIC, please mail\n");
830 printk(KERN_WARNING " to linux-smp@vger.kernel.org\n");
834 void __init print_IO_APIC(void)
837 union IO_APIC_reg_00 reg_00;
838 union IO_APIC_reg_01 reg_01;
839 union IO_APIC_reg_02 reg_02;
842 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
843 for (i = 0; i < nr_ioapics; i++)
844 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
845 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
848 * We are a bit conservative about what we expect. We have to
849 * know about every hardware change ASAP.
851 printk(KERN_INFO "testing the IO APIC.......................\n");
853 for (apic = 0; apic < nr_ioapics; apic++) {
855 spin_lock_irqsave(&ioapic_lock, flags);
856 reg_00.raw = io_apic_read(apic, 0);
857 reg_01.raw = io_apic_read(apic, 1);
858 if (reg_01.bits.version >= 0x10)
859 reg_02.raw = io_apic_read(apic, 2);
860 spin_unlock_irqrestore(&ioapic_lock, flags);
863 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
864 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
865 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
866 if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
867 UNEXPECTED_IO_APIC();
869 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
870 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
871 if ( (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
872 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
873 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
874 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
875 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
876 (reg_01.bits.entries != 0x2E) &&
877 (reg_01.bits.entries != 0x3F) &&
878 (reg_01.bits.entries != 0x03)
880 UNEXPECTED_IO_APIC();
882 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
883 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
884 if ( (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
885 (reg_01.bits.version != 0x02) && /* 82801BA IO-APICs (ICH2) */
886 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
887 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
888 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
889 (reg_01.bits.version != 0x20) /* Intel P64H (82806 AA) */
891 UNEXPECTED_IO_APIC();
892 if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
893 UNEXPECTED_IO_APIC();
895 if (reg_01.bits.version >= 0x10) {
896 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
897 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
898 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
899 UNEXPECTED_IO_APIC();
902 printk(KERN_DEBUG ".... IRQ redirection table:\n");
904 printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
905 " Stat Dest Deli Vect: \n");
907 for (i = 0; i <= reg_01.bits.entries; i++) {
908 struct IO_APIC_route_entry entry;
910 spin_lock_irqsave(&ioapic_lock, flags);
911 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
912 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
913 spin_unlock_irqrestore(&ioapic_lock, flags);
915 printk(KERN_DEBUG " %02x %03X %02X ",
917 entry.dest.logical.logical_dest,
918 entry.dest.physical.physical_dest
921 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
926 entry.delivery_status,
933 if (use_pci_vector())
934 printk(KERN_INFO "Using vector-based indexing\n");
935 printk(KERN_DEBUG "IRQ to pin mappings:\n");
936 for (i = 0; i < NR_IRQS; i++) {
937 struct irq_pin_list *entry = irq_2_pin + i;
940 if (use_pci_vector() && !platform_legacy_irq(i))
941 printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
943 printk(KERN_DEBUG "IRQ%d ", i);
945 printk("-> %d:%d", entry->apic, entry->pin);
948 entry = irq_2_pin + entry->next;
953 printk(KERN_INFO ".................................... done.\n");
958 static void print_APIC_bitfield (int base)
963 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
964 for (i = 0; i < 8; i++) {
965 v = apic_read(base + i*0x10);
966 for (j = 0; j < 32; j++) {
976 void /*__init*/ print_local_APIC(void * dummy)
978 unsigned int v, ver, maxlvt;
980 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
981 smp_processor_id(), hard_smp_processor_id());
982 v = apic_read(APIC_ID);
983 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v));
984 v = apic_read(APIC_LVR);
985 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
986 ver = GET_APIC_VERSION(v);
987 maxlvt = get_maxlvt();
989 v = apic_read(APIC_TASKPRI);
990 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
992 if (APIC_INTEGRATED(ver)) { /* !82489DX */
993 v = apic_read(APIC_ARBPRI);
994 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
995 v & APIC_ARBPRI_MASK);
996 v = apic_read(APIC_PROCPRI);
997 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1000 v = apic_read(APIC_EOI);
1001 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1002 v = apic_read(APIC_RRR);
1003 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1004 v = apic_read(APIC_LDR);
1005 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1006 v = apic_read(APIC_DFR);
1007 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1008 v = apic_read(APIC_SPIV);
1009 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1011 printk(KERN_DEBUG "... APIC ISR field:\n");
1012 print_APIC_bitfield(APIC_ISR);
1013 printk(KERN_DEBUG "... APIC TMR field:\n");
1014 print_APIC_bitfield(APIC_TMR);
1015 printk(KERN_DEBUG "... APIC IRR field:\n");
1016 print_APIC_bitfield(APIC_IRR);
1018 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1019 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1020 apic_write(APIC_ESR, 0);
1021 v = apic_read(APIC_ESR);
1022 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1025 v = apic_read(APIC_ICR);
1026 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1027 v = apic_read(APIC_ICR2);
1028 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1030 v = apic_read(APIC_LVTT);
1031 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1033 if (maxlvt > 3) { /* PC is LVT#4. */
1034 v = apic_read(APIC_LVTPC);
1035 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1037 v = apic_read(APIC_LVT0);
1038 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1039 v = apic_read(APIC_LVT1);
1040 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1042 if (maxlvt > 2) { /* ERR is LVT#3. */
1043 v = apic_read(APIC_LVTERR);
1044 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1047 v = apic_read(APIC_TMICT);
1048 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1049 v = apic_read(APIC_TMCCT);
1050 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1051 v = apic_read(APIC_TDCR);
1052 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1056 void print_all_local_APICs (void)
1058 on_each_cpu(print_local_APIC, NULL, 1, 1);
1061 void /*__init*/ print_PIC(void)
1063 extern spinlock_t i8259A_lock;
1065 unsigned long flags;
1067 printk(KERN_DEBUG "\nprinting PIC contents\n");
1069 spin_lock_irqsave(&i8259A_lock, flags);
1071 v = inb(0xa1) << 8 | inb(0x21);
1072 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1074 v = inb(0xa0) << 8 | inb(0x20);
1075 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1079 v = inb(0xa0) << 8 | inb(0x20);
1083 spin_unlock_irqrestore(&i8259A_lock, flags);
1085 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1087 v = inb(0x4d1) << 8 | inb(0x4d0);
1088 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1091 static void __init enable_IO_APIC(void)
1093 union IO_APIC_reg_01 reg_01;
1095 unsigned long flags;
1097 for (i = 0; i < PIN_MAP_SIZE; i++) {
1098 irq_2_pin[i].pin = -1;
1099 irq_2_pin[i].next = 0;
1102 for (i = 0; i < MAX_PIRQS; i++)
1103 pirq_entries[i] = -1;
1106 * The number of IO-APIC IRQ registers (== #pins):
1108 for (i = 0; i < nr_ioapics; i++) {
1109 spin_lock_irqsave(&ioapic_lock, flags);
1110 reg_01.raw = io_apic_read(i, 1);
1111 spin_unlock_irqrestore(&ioapic_lock, flags);
1112 nr_ioapic_registers[i] = reg_01.bits.entries+1;
1116 * Do not trust the IO-APIC being empty at bootup
1122 * Not an __init, needed by the reboot code
1124 void disable_IO_APIC(void)
1127 * Clear the IO-APIC before rebooting:
1131 disconnect_bsp_APIC();
1135 * function to set the IO-APIC physical IDs based on the
1136 * values stored in the MPC table.
1138 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1141 static void __init setup_ioapic_ids_from_mpc (void)
1143 union IO_APIC_reg_00 reg_00;
1144 physid_mask_t phys_id_present_map = phys_cpu_present_map;
1147 unsigned char old_id;
1148 unsigned long flags;
1151 * Set the IOAPIC ID to the value stored in the MPC table.
1153 for (apic = 0; apic < nr_ioapics; apic++) {
1155 /* Read the register 0 value */
1156 spin_lock_irqsave(&ioapic_lock, flags);
1157 reg_00.raw = io_apic_read(apic, 0);
1158 spin_unlock_irqrestore(&ioapic_lock, flags);
1160 old_id = mp_ioapics[apic].mpc_apicid;
1162 if (mp_ioapics[apic].mpc_apicid >= 0xf) {
1163 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1164 apic, mp_ioapics[apic].mpc_apicid);
1165 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1167 mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1171 * Sanity check, is the ID really free? Every APIC in a
1172 * system must have a unique ID or we get lots of nice
1173 * 'stuck on smp_invalidate_needed IPI wait' messages.
1175 if (physid_isset(mp_ioapics[apic].mpc_apicid, phys_id_present_map)) {
1176 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1177 apic, mp_ioapics[apic].mpc_apicid);
1178 for (i = 0; i < 0xf; i++)
1179 if (!physid_isset(i, phys_id_present_map))
1182 panic("Max APIC ID exceeded!\n");
1183 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1185 physid_set(i, phys_id_present_map);
1186 mp_ioapics[apic].mpc_apicid = i;
1189 "Using IO-APIC %d\n", mp_ioapics[apic].mpc_apicid);
1190 physid_set(mp_ioapics[apic].mpc_apicid, phys_id_present_map);
1195 * We need to adjust the IRQ routing table
1196 * if the ID changed.
1198 if (old_id != mp_ioapics[apic].mpc_apicid)
1199 for (i = 0; i < mp_irq_entries; i++)
1200 if (mp_irqs[i].mpc_dstapic == old_id)
1201 mp_irqs[i].mpc_dstapic
1202 = mp_ioapics[apic].mpc_apicid;
1205 * Read the right value from the MPC table and
1206 * write it into the ID register.
1208 printk(KERN_INFO "...changing IO-APIC physical APIC ID to %d ...",
1209 mp_ioapics[apic].mpc_apicid);
1211 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1212 spin_lock_irqsave(&ioapic_lock, flags);
1213 io_apic_write(apic, 0, reg_00.raw);
1214 spin_unlock_irqrestore(&ioapic_lock, flags);
1219 spin_lock_irqsave(&ioapic_lock, flags);
1220 reg_00.raw = io_apic_read(apic, 0);
1221 spin_unlock_irqrestore(&ioapic_lock, flags);
1222 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1223 panic("could not set ID!\n");
1230 * There is a nasty bug in some older SMP boards, their mptable lies
1231 * about the timer IRQ. We do the following to work around the situation:
1233 * - timer IRQ defaults to IO-APIC IRQ
1234 * - if this function detects that timer IRQs are defunct, then we fall
1235 * back to ISA timer IRQs
1237 static int __init timer_irq_works(void)
1239 unsigned long t1 = jiffies;
1242 /* Let ten ticks pass... */
1243 mdelay((10 * 1000) / HZ);
1246 * Expect a few ticks at least, to be sure some possible
1247 * glue logic does not lock up after one or two first
1248 * ticks in a non-ExtINT mode. Also the local APIC
1249 * might have cached one ExtINT interrupt. Finally, at
1250 * least one tick may be lost due to delays.
1254 if (jiffies - t1 > 4)
1260 * In the SMP+IOAPIC case it might happen that there are an unspecified
1261 * number of pending IRQ events unhandled. These cases are very rare,
1262 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1263 * better to do it this way as thus we do not have to be aware of
1264 * 'pending' interrupts in the IRQ path, except at this point.
1267 * Edge triggered needs to resend any interrupt
1268 * that was delayed but this is now handled in the device
1273 * Starting up a edge-triggered IO-APIC interrupt is
1274 * nasty - we need to make sure that we get the edge.
1275 * If it is already asserted for some reason, we need
1276 * return 1 to indicate that is was pending.
1278 * This is not complete - we should be able to fake
1279 * an edge even if it isn't on the 8259A...
1282 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1284 int was_pending = 0;
1285 unsigned long flags;
1287 spin_lock_irqsave(&ioapic_lock, flags);
1289 disable_8259A_irq(irq);
1290 if (i8259A_irq_pending(irq))
1293 __unmask_IO_APIC_irq(irq);
1294 spin_unlock_irqrestore(&ioapic_lock, flags);
1300 * Once we have recorded IRQ_PENDING already, we can mask the
1301 * interrupt for real. This prevents IRQ storms from unhandled
1304 static void ack_edge_ioapic_irq(unsigned int irq)
1306 if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
1307 == (IRQ_PENDING | IRQ_DISABLED))
1308 mask_IO_APIC_irq(irq);
1313 * Level triggered interrupts can just be masked,
1314 * and shutting down and starting up the interrupt
1315 * is the same as enabling and disabling them -- except
1316 * with a startup need to return a "was pending" value.
1318 * Level triggered interrupts are special because we
1319 * do not touch any IO-APIC register while handling
1320 * them. We ack the APIC in the end-IRQ handler, not
1321 * in the start-IRQ-handler. Protection against reentrance
1322 * from the same interrupt is still provided, both by the
1323 * generic IRQ layer and by the fact that an unacked local
1324 * APIC does not accept IRQs.
1326 static unsigned int startup_level_ioapic_irq (unsigned int irq)
1328 unmask_IO_APIC_irq(irq);
1330 return 0; /* don't check for pending */
1333 static void end_level_ioapic_irq (unsigned int irq)
1339 * It appears there is an erratum which affects at least version 0x11
1340 * of I/O APIC (that's the 82093AA and cores integrated into various
1341 * chipsets). Under certain conditions a level-triggered interrupt is
1342 * erroneously delivered as edge-triggered one but the respective IRR
1343 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1344 * message but it will never arrive and further interrupts are blocked
1345 * from the source. The exact reason is so far unknown, but the
1346 * phenomenon was observed when two consecutive interrupt requests
1347 * from a given source get delivered to the same CPU and the source is
1348 * temporarily disabled in between.
1350 * A workaround is to simulate an EOI message manually. We achieve it
1351 * by setting the trigger mode to edge and then to level when the edge
1352 * trigger mode gets detected in the TMR of a local APIC for a
1353 * level-triggered interrupt. We mask the source for the time of the
1354 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1355 * The idea is from Manfred Spraul. --macro
1357 i = IO_APIC_VECTOR(irq);
1358 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1362 if (!(v & (1 << (i & 0x1f)))) {
1363 #ifdef APIC_LOCKUP_DEBUG
1364 struct irq_pin_list *entry;
1367 #ifdef APIC_MISMATCH_DEBUG
1368 atomic_inc(&irq_mis_count);
1370 spin_lock(&ioapic_lock);
1371 __mask_and_edge_IO_APIC_irq(irq);
1372 #ifdef APIC_LOCKUP_DEBUG
1373 for (entry = irq_2_pin + irq;;) {
1376 if (entry->pin == -1)
1378 reg = io_apic_read(entry->apic, 0x10 + entry->pin * 2);
1379 if (reg & 0x00004000)
1380 printk(KERN_CRIT "Aieee!!! Remote IRR"
1381 " still set after unlock!\n");
1384 entry = irq_2_pin + entry->next;
1387 __unmask_and_level_IO_APIC_irq(irq);
1388 spin_unlock(&ioapic_lock);
1392 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
1394 unsigned long flags;
1397 dest = cpu_mask_to_apicid(mask);
1400 * Only the first 8 bits are valid.
1404 spin_lock_irqsave(&ioapic_lock, flags);
1405 __DO_ACTION(1, = dest, )
1406 spin_unlock_irqrestore(&ioapic_lock, flags);
1409 #ifdef CONFIG_PCI_MSI
1410 static unsigned int startup_edge_ioapic_vector(unsigned int vector)
1412 int irq = vector_to_irq(vector);
1414 return startup_edge_ioapic_irq(irq);
1417 static void ack_edge_ioapic_vector(unsigned int vector)
1419 int irq = vector_to_irq(vector);
1421 ack_edge_ioapic_irq(irq);
1424 static unsigned int startup_level_ioapic_vector (unsigned int vector)
1426 int irq = vector_to_irq(vector);
1428 return startup_level_ioapic_irq (irq);
1431 static void end_level_ioapic_vector (unsigned int vector)
1433 int irq = vector_to_irq(vector);
1435 end_level_ioapic_irq(irq);
1438 static void mask_IO_APIC_vector (unsigned int vector)
1440 int irq = vector_to_irq(vector);
1442 mask_IO_APIC_irq(irq);
1445 static void unmask_IO_APIC_vector (unsigned int vector)
1447 int irq = vector_to_irq(vector);
1449 unmask_IO_APIC_irq(irq);
1452 static void set_ioapic_affinity_vector (unsigned int vector,
1455 int irq = vector_to_irq(vector);
1457 set_ioapic_affinity_irq(irq, cpu_mask);
1462 * Level and edge triggered IO-APIC interrupts need different handling,
1463 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1464 * handled with the level-triggered descriptor, but that one has slightly
1465 * more overhead. Level-triggered interrupts cannot be handled with the
1466 * edge-triggered handler, without risking IRQ storms and other ugly
1470 static struct hw_interrupt_type ioapic_edge_type = {
1471 .typename = "IO-APIC-edge",
1472 .startup = startup_edge_ioapic,
1473 .shutdown = shutdown_edge_ioapic,
1474 .enable = enable_edge_ioapic,
1475 .disable = disable_edge_ioapic,
1476 .ack = ack_edge_ioapic,
1477 .end = end_edge_ioapic,
1478 .set_affinity = set_ioapic_affinity,
1481 static struct hw_interrupt_type ioapic_level_type = {
1482 .typename = "IO-APIC-level",
1483 .startup = startup_level_ioapic,
1484 .shutdown = shutdown_level_ioapic,
1485 .enable = enable_level_ioapic,
1486 .disable = disable_level_ioapic,
1487 .ack = mask_and_ack_level_ioapic,
1488 .end = end_level_ioapic,
1489 .set_affinity = set_ioapic_affinity,
1492 static inline void init_IO_APIC_traps(void)
1497 * NOTE! The local APIC isn't very good at handling
1498 * multiple interrupts at the same interrupt level.
1499 * As the interrupt level is determined by taking the
1500 * vector number and shifting that right by 4, we
1501 * want to spread these out a bit so that they don't
1502 * all fall in the same interrupt level.
1504 * Also, we've got to be careful not to trash gate
1505 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1507 for (irq = 0; irq < NR_IRQS ; irq++) {
1509 if (use_pci_vector()) {
1510 if (!platform_legacy_irq(tmp))
1511 if ((tmp = vector_to_irq(tmp)) == -1)
1514 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
1516 * Hmm.. We don't have an entry for this,
1517 * so default to an old-fashioned 8259
1518 * interrupt if we can..
1521 make_8259A_irq(irq);
1523 /* Strange. Oh, well.. */
1524 irq_desc[irq].handler = &no_irq_type;
1529 static void enable_lapic_irq (unsigned int irq)
1533 v = apic_read(APIC_LVT0);
1534 apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
1537 static void disable_lapic_irq (unsigned int irq)
1541 v = apic_read(APIC_LVT0);
1542 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
1545 static void ack_lapic_irq (unsigned int irq)
1550 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1552 static struct hw_interrupt_type lapic_irq_type = {
1553 .typename = "local-APIC-edge",
1554 .startup = NULL, /* startup_irq() not used for IRQ0 */
1555 .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1556 .enable = enable_lapic_irq,
1557 .disable = disable_lapic_irq,
1558 .ack = ack_lapic_irq,
1559 .end = end_lapic_irq,
1562 static void setup_nmi (void)
1565 * Dirty trick to enable the NMI watchdog ...
1566 * We put the 8259A master into AEOI mode and
1567 * unmask on all local APICs LVT0 as NMI.
1569 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1570 * is from Maciej W. Rozycki - so we do not have to EOI from
1571 * the NMI handler or the timer interrupt.
1573 printk(KERN_INFO "activating NMI Watchdog ...");
1575 enable_NMI_through_LVT0(NULL);
1581 * This looks a bit hackish but it's about the only one way of sending
1582 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1583 * not support the ExtINT mode, unfortunately. We need to send these
1584 * cycles as some i82489DX-based boards have glue logic that keeps the
1585 * 8259A interrupt line asserted until INTA. --macro
1587 static inline void unlock_ExtINT_logic(void)
1590 struct IO_APIC_route_entry entry0, entry1;
1591 unsigned char save_control, save_freq_select;
1592 unsigned long flags;
1594 pin = find_isa_irq_pin(8, mp_INT);
1598 spin_lock_irqsave(&ioapic_lock, flags);
1599 *(((int *)&entry0) + 1) = io_apic_read(0, 0x11 + 2 * pin);
1600 *(((int *)&entry0) + 0) = io_apic_read(0, 0x10 + 2 * pin);
1601 spin_unlock_irqrestore(&ioapic_lock, flags);
1602 clear_IO_APIC_pin(0, pin);
1604 memset(&entry1, 0, sizeof(entry1));
1606 entry1.dest_mode = 0; /* physical delivery */
1607 entry1.mask = 0; /* unmask IRQ now */
1608 entry1.dest.physical.physical_dest = hard_smp_processor_id();
1609 entry1.delivery_mode = dest_ExtINT;
1610 entry1.polarity = entry0.polarity;
1614 spin_lock_irqsave(&ioapic_lock, flags);
1615 io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1616 io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1617 spin_unlock_irqrestore(&ioapic_lock, flags);
1619 save_control = CMOS_READ(RTC_CONTROL);
1620 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1621 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1623 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1628 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1632 CMOS_WRITE(save_control, RTC_CONTROL);
1633 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1634 clear_IO_APIC_pin(0, pin);
1636 spin_lock_irqsave(&ioapic_lock, flags);
1637 io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1638 io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1639 spin_unlock_irqrestore(&ioapic_lock, flags);
1643 * This code may look a bit paranoid, but it's supposed to cooperate with
1644 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1645 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1646 * fanatically on his truly buggy board.
1648 static inline void check_timer(void)
1654 * get/set the timer IRQ vector:
1656 disable_8259A_irq(0);
1657 vector = assign_irq_vector(0);
1658 set_intr_gate(vector, interrupt[0]);
1661 * Subtle, code in do_timer_interrupt() expects an AEOI
1662 * mode for the 8259A whenever interrupts are routed
1663 * through I/O APICs. Also IRQ0 has to be enabled in
1664 * the 8259A which implies the virtual wire has to be
1665 * disabled in the local APIC.
1667 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1669 enable_8259A_irq(0);
1671 pin1 = find_isa_irq_pin(0, mp_INT);
1672 pin2 = find_isa_irq_pin(0, mp_ExtINT);
1674 printk(KERN_INFO "..TIMER: vector=0x%02X pin1=%d pin2=%d\n", vector, pin1, pin2);
1678 * Ok, does IRQ0 through the IOAPIC work?
1680 unmask_IO_APIC_irq(0);
1681 if (timer_irq_works()) {
1682 nmi_watchdog_default();
1683 if (nmi_watchdog == NMI_IO_APIC) {
1684 disable_8259A_irq(0);
1686 enable_8259A_irq(0);
1687 check_nmi_watchdog();
1691 clear_IO_APIC_pin(0, pin1);
1692 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to IO-APIC\n");
1695 printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
1697 printk("\n..... (found pin %d) ...", pin2);
1699 * legacy devices should be connected to IO APIC #0
1701 setup_ExtINT_IRQ0_pin(pin2, vector);
1702 if (timer_irq_works()) {
1704 nmi_watchdog_default();
1705 if (nmi_watchdog == NMI_IO_APIC) {
1707 check_nmi_watchdog();
1712 * Cleanup, just in case ...
1714 clear_IO_APIC_pin(0, pin2);
1716 printk(" failed.\n");
1719 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1723 printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1725 disable_8259A_irq(0);
1726 irq_desc[0].handler = &lapic_irq_type;
1727 apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
1728 enable_8259A_irq(0);
1730 if (timer_irq_works()) {
1731 printk(" works.\n");
1734 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1735 printk(" failed.\n");
1737 printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1741 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
1743 unlock_ExtINT_logic();
1745 if (timer_irq_works()) {
1746 printk(" works.\n");
1749 printk(" failed :(.\n");
1750 panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1755 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1756 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1757 * Linux doesn't really care, as it's not actually used
1758 * for any interrupt handling anyway.
1760 #define PIC_IRQS (1<<2)
1762 void __init setup_IO_APIC(void)
1767 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
1769 io_apic_irqs = ~PIC_IRQS;
1771 printk("ENABLING IO-APIC IRQs\n");
1774 * Set up the IO-APIC IRQ routing table.
1777 setup_ioapic_ids_from_mpc();
1779 setup_IO_APIC_irqs();
1780 init_IO_APIC_traps();
1786 /* --------------------------------------------------------------------------
1787 ACPI-based IOAPIC Configuration
1788 -------------------------------------------------------------------------- */
1790 #ifdef CONFIG_ACPI_BOOT
1792 #define IO_APIC_MAX_ID 15
1794 int __init io_apic_get_unique_id (int ioapic, int apic_id)
1796 union IO_APIC_reg_00 reg_00;
1797 static physid_mask_t apic_id_map;
1798 unsigned long flags;
1802 * The P4 platform supports up to 256 APIC IDs on two separate APIC
1803 * buses (one for LAPICs, one for IOAPICs), where predecessors only
1804 * supports up to 16 on one shared APIC bus.
1806 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
1807 * advantage of new APIC bus architecture.
1810 if (physids_empty(apic_id_map))
1811 apic_id_map = phys_cpu_present_map;
1813 spin_lock_irqsave(&ioapic_lock, flags);
1814 reg_00.raw = io_apic_read(ioapic, 0);
1815 spin_unlock_irqrestore(&ioapic_lock, flags);
1817 if (apic_id >= IO_APIC_MAX_ID) {
1818 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
1819 "%d\n", ioapic, apic_id, reg_00.bits.ID);
1820 apic_id = reg_00.bits.ID;
1824 * Every APIC in a system must have a unique ID or we get lots of nice
1825 * 'stuck on smp_invalidate_needed IPI wait' messages.
1827 if (physid_isset(apic_id, apic_id_map)) {
1829 for (i = 0; i < IO_APIC_MAX_ID; i++) {
1830 if (!physid_isset(i, apic_id_map))
1834 if (i == IO_APIC_MAX_ID)
1835 panic("Max apic_id exceeded!\n");
1837 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
1838 "trying %d\n", ioapic, apic_id, i);
1843 physid_set(apic_id, apic_id_map);
1845 if (reg_00.bits.ID != apic_id) {
1846 reg_00.bits.ID = apic_id;
1848 spin_lock_irqsave(&ioapic_lock, flags);
1849 io_apic_write(ioapic, 0, reg_00.raw);
1850 reg_00.raw = io_apic_read(ioapic, 0);
1851 spin_unlock_irqrestore(&ioapic_lock, flags);
1854 if (reg_00.bits.ID != apic_id)
1855 panic("IOAPIC[%d]: Unable change apic_id!\n", ioapic);
1858 printk(KERN_INFO "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
1864 int __init io_apic_get_version (int ioapic)
1866 union IO_APIC_reg_01 reg_01;
1867 unsigned long flags;
1869 spin_lock_irqsave(&ioapic_lock, flags);
1870 reg_01.raw = io_apic_read(ioapic, 1);
1871 spin_unlock_irqrestore(&ioapic_lock, flags);
1873 return reg_01.bits.version;
1877 int __init io_apic_get_redir_entries (int ioapic)
1879 union IO_APIC_reg_01 reg_01;
1880 unsigned long flags;
1882 spin_lock_irqsave(&ioapic_lock, flags);
1883 reg_01.raw = io_apic_read(ioapic, 1);
1884 spin_unlock_irqrestore(&ioapic_lock, flags);
1886 return reg_01.bits.entries;
1890 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
1892 struct IO_APIC_route_entry entry;
1893 unsigned long flags;
1895 if (!IO_APIC_IRQ(irq)) {
1896 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
1902 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
1903 * Note that we mask (disable) IRQs now -- these get enabled when the
1904 * corresponding device driver registers for this IRQ.
1907 memset(&entry,0,sizeof(entry));
1909 entry.delivery_mode = dest_LowestPrio;
1910 entry.dest_mode = INT_DELIVERY_MODE;
1911 entry.dest.logical.logical_dest = TARGET_CPUS;
1912 entry.trigger = edge_level;
1913 entry.polarity = active_high_low;
1914 entry.mask = 1; /* Disabled (masked) */
1917 * IRQs < 16 are already in the irq_2_pin[] map
1920 add_pin_to_irq(irq, ioapic, pin);
1922 entry.vector = assign_irq_vector(irq);
1924 printk(KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> "
1925 "IRQ %d Mode:%i Active:%i)\n", ioapic,
1926 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
1927 edge_level, active_high_low);
1929 if (use_pci_vector() && !platform_legacy_irq(irq))
1930 irq = IO_APIC_VECTOR(irq);
1932 irq_desc[irq].handler = &ioapic_level_type;
1934 irq_desc[irq].handler = &ioapic_edge_type;
1937 set_intr_gate(entry.vector, interrupt[irq]);
1939 if (!ioapic && (irq < 16))
1940 disable_8259A_irq(irq);
1942 spin_lock_irqsave(&ioapic_lock, flags);
1943 io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
1944 io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
1945 spin_unlock_irqrestore(&ioapic_lock, flags);
1950 #endif /*CONFIG_ACPI_BOOT*/
1953 void send_IPI_self(int vector)
1960 apic_wait_icr_idle();
1961 cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
1964 * Send the IPI. The write to APIC_ICR fires this off.
1966 apic_write_around(APIC_ICR, cfg);