2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
5 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
15 * This code is released under the GNU General Public License version 2 or
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIP report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 #include <linux/config.h>
38 #include <linux/init.h>
41 #include <linux/kernel_stat.h>
42 #include <linux/smp_lock.h>
43 #include <linux/irq.h>
44 #include <linux/bootmem.h>
45 #include <linux/thread_info.h>
46 #include <linux/module.h>
48 #include <linux/delay.h>
49 #include <linux/mc146818rtc.h>
51 #include <asm/pgalloc.h>
53 #include <asm/kdebug.h>
54 #include <asm/tlbflush.h>
55 #include <asm/proto.h>
57 /* Number of siblings per CPU package */
58 int smp_num_siblings = 1;
59 /* Package ID of each logical CPU */
60 u8 phys_proc_id[NR_CPUS] = { [0 ... NR_CPUS-1] = BAD_APICID };
61 EXPORT_SYMBOL(phys_proc_id);
63 /* Bitmask of currently online CPUs */
64 cpumask_t cpu_online_map;
66 cpumask_t cpu_callin_map;
67 cpumask_t cpu_callout_map;
68 static cpumask_t smp_commenced_mask;
70 /* Per CPU bogomips and other parameters */
71 struct cpuinfo_x86 cpu_data[NR_CPUS] __cacheline_aligned;
73 /* Set when the idlers are all forked */
74 int smp_threads_ready;
76 cpumask_t cpu_sibling_map[NR_CPUS] __cacheline_aligned;
79 * Trampoline 80x86 program as an array.
82 extern unsigned char trampoline_data [];
83 extern unsigned char trampoline_end [];
86 * Currently trivial. Write the real->protected mode
87 * bootstrap into the page concerned. The caller
88 * has made sure it's suitably aligned.
91 static unsigned long __init setup_trampoline(void)
93 void *tramp = __va(SMP_TRAMPOLINE_BASE);
94 extern volatile __u32 tramp_gdt_ptr;
95 tramp_gdt_ptr = __pa_symbol(&cpu_gdt_table);
96 memcpy(tramp, trampoline_data, trampoline_end - trampoline_data);
97 return virt_to_phys(tramp);
101 * The bootstrap kernel entry code has set these up. Save them for
105 static void __init smp_store_cpu_info(int id)
107 struct cpuinfo_x86 *c = cpu_data + id;
114 * TSC synchronization.
116 * We first check whether all CPUs have their TSC's synchronized,
117 * then we print a warning if not, and always resync.
120 static atomic_t tsc_start_flag = ATOMIC_INIT(0);
121 static atomic_t tsc_count_start = ATOMIC_INIT(0);
122 static atomic_t tsc_count_stop = ATOMIC_INIT(0);
123 static unsigned long long tsc_values[NR_CPUS];
127 extern unsigned int fast_gettimeoffset_quotient;
129 static void __init synchronize_tsc_bp (void)
132 unsigned long long t0;
133 unsigned long long sum, avg;
138 printk(KERN_INFO "checking TSC synchronization across %u CPUs: ",num_booting_cpus());
142 atomic_set(&tsc_start_flag, 1);
146 * We loop a few times to get a primed instruction cache,
147 * then the last pass is more or less synchronized and
148 * the BP and APs set their cycle counters to zero all at
149 * once. This reduces the chance of having random offsets
150 * between the processors, and guarantees that the maximum
151 * delay between the cycle counters is never bigger than
152 * the latency of information-passing (cachelines) between
155 for (i = 0; i < NR_LOOPS; i++) {
157 * all APs synchronize but they loop on '== num_cpus'
159 while (atomic_read(&tsc_count_start) != num_booting_cpus()-1) mb();
160 atomic_set(&tsc_count_stop, 0);
163 * this lets the APs save their current TSC:
165 atomic_inc(&tsc_count_start);
168 rdtscll(tsc_values[smp_processor_id()]);
170 * We clear the TSC in the last loop:
176 * Wait for all APs to leave the synchronization point:
178 while (atomic_read(&tsc_count_stop) != num_booting_cpus()-1) mb();
179 atomic_set(&tsc_count_start, 0);
181 atomic_inc(&tsc_count_stop);
185 for (i = 0; i < NR_CPUS; i++) {
186 if (cpu_isset(i, cpu_callout_map)) {
191 avg = sum / num_booting_cpus();
194 for (i = 0; i < NR_CPUS; i++) {
195 if (!cpu_isset(i, cpu_callout_map))
198 delta = tsc_values[i] - avg;
202 * We report bigger than 2 microseconds clock differences.
204 if (delta > 2*one_usec) {
210 realdelta = delta / one_usec;
211 if (tsc_values[i] < avg)
212 realdelta = -realdelta;
214 printk("BIOS BUG: CPU#%d improperly initialized, has %ld usecs TSC skew! FIXED.\n",
224 static void __init synchronize_tsc_ap (void)
229 * Not every cpu is online at the time
230 * this gets called, so we first wait for the BP to
231 * finish SMP initialization:
233 while (!atomic_read(&tsc_start_flag)) mb();
235 for (i = 0; i < NR_LOOPS; i++) {
236 atomic_inc(&tsc_count_start);
237 while (atomic_read(&tsc_count_start) != num_booting_cpus()) mb();
240 rdtscll(tsc_values[smp_processor_id()]);
244 atomic_inc(&tsc_count_stop);
245 while (atomic_read(&tsc_count_stop) != num_booting_cpus()) mb();
250 static atomic_t init_deasserted;
252 void __init smp_callin(void)
255 unsigned long timeout;
258 * If waken up by an INIT in an 82489DX configuration
259 * we may get here before an INIT-deassert IPI reaches
260 * our local APIC. We have to wait for the IPI or we'll
261 * lock up on an APIC access.
263 while (!atomic_read(&init_deasserted));
266 * (This works even if the APIC is not enabled.)
268 phys_id = GET_APIC_ID(apic_read(APIC_ID));
269 cpuid = smp_processor_id();
270 if (cpu_isset(cpuid, cpu_callin_map)) {
271 panic("smp_callin: phys CPU#%d, CPU#%d already present??\n",
274 Dprintk("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id);
277 * STARTUP IPIs are fragile beasts as they might sometimes
278 * trigger some glue motherboard logic. Complete APIC bus
279 * silence for 1 second, this overestimates the time the
280 * boot CPU is spending to send the up to 2 STARTUP IPIs
281 * by a factor of two. This should be enough.
285 * Waiting 2s total for startup (udelay is not yet working)
287 timeout = jiffies + 2*HZ;
288 while (time_before(jiffies, timeout)) {
290 * Has the boot CPU finished it's STARTUP sequence?
292 if (cpu_isset(cpuid, cpu_callout_map))
297 if (!time_before(jiffies, timeout)) {
298 panic("smp_callin: CPU%d started up but did not get a callout!\n",
303 * the boot CPU has finished the init stage and is spinning
304 * on callin_map until we finish. We are free to set up this
305 * CPU, first the APIC. (this is probably redundant on most
309 Dprintk("CALLIN, before setup_local_APIC().\n");
318 Dprintk("Stack at about %p\n",&cpuid);
320 disable_APIC_timer();
323 * Save our processor parameters
325 smp_store_cpu_info(cpuid);
330 * Allow the master to continue.
332 cpu_set(cpuid, cpu_callin_map);
335 * Synchronize the TSC with the BP
338 synchronize_tsc_ap();
344 * Activate a secondary processor.
346 void __init start_secondary(void)
349 * Dont put anything before smp_callin(), SMP
350 * booting is too fragile that we want to limit the
351 * things done here to the most necessary things.
356 /* otherwise gcc will move up the smp_processor_id before the cpu_init */
359 Dprintk("cpu %d: waiting for commence\n", smp_processor_id());
360 while (!cpu_isset(smp_processor_id(), smp_commenced_mask))
363 Dprintk("cpu %d: setting up apic clock\n", smp_processor_id());
364 setup_secondary_APIC_clock();
366 Dprintk("cpu %d: enabling apic timer\n", smp_processor_id());
368 if (nmi_watchdog == NMI_IO_APIC) {
369 disable_8259A_irq(0);
370 enable_NMI_through_LVT0(NULL);
378 * low-memory mappings have been cleared, flush them from
379 * the local TLBs too.
383 Dprintk("cpu %d eSetting cpu_online_map\n", smp_processor_id());
384 cpu_set(smp_processor_id(), cpu_online_map);
390 extern volatile unsigned long init_rsp;
391 extern void (*initial_code)(void);
394 static inline void inquire_remote_apic(int apicid)
396 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
397 char *names[] = { "ID", "VERSION", "SPIV" };
400 printk(KERN_INFO "Inquiring remote APIC #%d...\n", apicid);
402 for (i = 0; i < sizeof(regs) / sizeof(*regs); i++) {
403 printk("... APIC #%d %s: ", apicid, names[i]);
408 apic_wait_icr_idle();
410 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
411 apic_write_around(APIC_ICR, APIC_DM_REMRD | regs[i]);
416 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
417 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
420 case APIC_ICR_RR_VALID:
421 status = apic_read(APIC_RRR);
422 printk("%08x\n", status);
431 static int __init wakeup_secondary_via_INIT(int phys_apicid, unsigned int start_rip)
433 unsigned long send_status = 0, accept_status = 0;
434 int maxlvt, timeout, num_starts, j;
436 Dprintk("Asserting INIT.\n");
439 * Turn INIT on target chip
441 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
446 apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT
449 Dprintk("Waiting for send to finish...\n");
454 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
455 } while (send_status && (timeout++ < 1000));
459 Dprintk("Deasserting INIT.\n");
462 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
465 apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT);
467 Dprintk("Waiting for send to finish...\n");
472 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
473 } while (send_status && (timeout++ < 1000));
475 atomic_set(&init_deasserted, 1);
478 * Should we send STARTUP IPIs ?
480 * Determine this based on the APIC version.
481 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
483 if (APIC_INTEGRATED(apic_version[phys_apicid]))
489 * Run STARTUP IPI loop.
491 Dprintk("#startup loops: %d.\n", num_starts);
493 maxlvt = get_maxlvt();
495 for (j = 1; j <= num_starts; j++) {
496 Dprintk("Sending STARTUP #%d.\n",j);
497 apic_read_around(APIC_SPIV);
498 apic_write(APIC_ESR, 0);
500 Dprintk("After apic_write.\n");
507 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
509 /* Boot on the stack */
510 /* Kick the second */
511 apic_write_around(APIC_ICR, APIC_DM_STARTUP
512 | (start_rip >> 12));
515 * Give the other CPU some time to accept the IPI.
519 Dprintk("Startup point 1.\n");
521 Dprintk("Waiting for send to finish...\n");
526 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
527 } while (send_status && (timeout++ < 1000));
530 * Give the other CPU some time to accept the IPI.
534 * Due to the Pentium erratum 3AP.
537 apic_read_around(APIC_SPIV);
538 apic_write(APIC_ESR, 0);
540 accept_status = (apic_read(APIC_ESR) & 0xEF);
541 if (send_status || accept_status)
544 Dprintk("After Startup.\n");
547 printk(KERN_ERR "APIC never delivered???\n");
549 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status);
551 return (send_status | accept_status);
554 static void __init do_boot_cpu (int apicid)
556 struct task_struct *idle;
557 unsigned long boot_error;
559 unsigned long start_rip;
563 * We can't use kernel_thread since we must avoid to
564 * reschedule the child.
566 idle = fork_idle(cpu);
568 panic("failed fork for CPU %d", cpu);
569 x86_cpu_to_apicid[cpu] = apicid;
571 cpu_pda[cpu].pcurrent = idle;
573 start_rip = setup_trampoline();
575 init_rsp = idle->thread.rsp;
576 per_cpu(init_tss,cpu).rsp0 = init_rsp;
577 initial_code = start_secondary;
578 clear_ti_thread_flag(idle->thread_info, TIF_FORK);
580 printk(KERN_INFO "Booting processor %d/%d rip %lx rsp %lx\n", cpu, apicid,
581 start_rip, init_rsp);
584 * This grunge runs the startup process for
585 * the targeted processor.
588 atomic_set(&init_deasserted, 0);
590 Dprintk("Setting warm reset code and vector.\n");
592 CMOS_WRITE(0xa, 0xf);
595 *((volatile unsigned short *) phys_to_virt(0x469)) = start_rip >> 4;
597 *((volatile unsigned short *) phys_to_virt(0x467)) = start_rip & 0xf;
601 * Be paranoid about clearing APIC errors.
603 if (APIC_INTEGRATED(apic_version[apicid])) {
604 apic_read_around(APIC_SPIV);
605 apic_write(APIC_ESR, 0);
610 * Status is now clean
615 * Starting actual IPI sequence...
617 boot_error = wakeup_secondary_via_INIT(apicid, start_rip);
621 * allow APs to start initializing.
623 Dprintk("Before Callout %d.\n", cpu);
624 cpu_set(cpu, cpu_callout_map);
625 Dprintk("After Callout %d.\n", cpu);
628 * Wait 5s total for a response
630 for (timeout = 0; timeout < 50000; timeout++) {
631 if (cpu_isset(cpu, cpu_callin_map))
632 break; /* It has booted */
636 if (cpu_isset(cpu, cpu_callin_map)) {
637 /* number CPUs logically, starting from 1 (BSP is 0) */
639 print_cpu_info(&cpu_data[cpu]);
640 Dprintk("CPU has booted.\n");
643 if (*((volatile unsigned char *)phys_to_virt(SMP_TRAMPOLINE_BASE))
645 /* trampoline started but...? */
646 printk("Stuck ??\n");
648 /* trampoline code not run */
649 printk("Not responding.\n");
651 inquire_remote_apic(apicid);
656 cpu_clear(cpu, cpu_callout_map); /* was set here (do_boot_cpu()) */
657 clear_bit(cpu, &cpu_initialized); /* was set by cpu_init() */
659 x86_cpu_to_apicid[cpu] = BAD_APICID;
660 x86_cpu_to_log_apicid[cpu] = BAD_APICID;
664 cycles_t cacheflush_time;
665 unsigned long cache_decay_ticks;
667 static void smp_tune_scheduling (void)
669 int cachesize; /* kB */
670 unsigned long bandwidth = 1000; /* MB/s */
672 * Rough estimation for SMP scheduling, this is the number of
673 * cycles it takes for a fully memory-limited process to flush
674 * the SMP-local cache.
676 * (For a P5 this pretty much means we will choose another idle
677 * CPU almost always at wakeup time (this is due to the small
678 * L1 cache), on PIIs it's around 50-100 usecs, depending on
684 * this basically disables processor-affinity
685 * scheduling on SMP without a TSC.
690 cachesize = boot_cpu_data.x86_cache_size;
691 if (cachesize == -1) {
692 cachesize = 16; /* Pentiums, 2x8kB cache */
696 cacheflush_time = (cpu_khz>>10) * (cachesize<<10) / bandwidth;
699 cache_decay_ticks = (long)cacheflush_time/cpu_khz * HZ / 1000;
701 printk(KERN_INFO "per-CPU timeslice cutoff: %ld.%02ld usecs.\n",
702 (long)cacheflush_time/(cpu_khz/1000),
703 ((long)cacheflush_time*100/(cpu_khz/1000)) % 100);
704 printk(KERN_INFO "task migration cache decay timeout: %ld msecs.\n",
705 (cache_decay_ticks + 1) * 1000 / HZ);
709 * Cycle through the processors sending APIC IPIs to boot each.
712 static void __init smp_boot_cpus(unsigned int max_cpus)
714 unsigned apicid, cpu, bit, kicked;
716 nmi_watchdog_default();
719 * Setup boot CPU information
721 smp_store_cpu_info(0); /* Final full version of the data */
722 printk(KERN_INFO "CPU%d: ", 0);
723 print_cpu_info(&cpu_data[0]);
725 current_thread_info()->cpu = 0;
726 smp_tune_scheduling();
728 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
729 printk("weird, boot CPU (#%d) not listed by the BIOS.\n",
730 hard_smp_processor_id());
731 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
735 * If we couldn't find an SMP configuration at boot time,
736 * get out of here now!
738 if (!smp_found_config) {
739 printk(KERN_NOTICE "SMP motherboard not detected.\n");
741 cpu_online_map = cpumask_of_cpu(0);
742 phys_cpu_present_map = physid_mask_of_physid(0);
743 if (APIC_init_uniprocessor())
744 printk(KERN_NOTICE "Local APIC not detected."
745 " Using dummy APIC emulation.\n");
750 * Should not be necessary because the MP table should list the boot
751 * CPU too, but we do it for the sake of robustness anyway.
753 if (!physid_isset(boot_cpu_id, phys_cpu_present_map)) {
754 printk(KERN_NOTICE "weird, boot CPU (#%d) not listed by the BIOS.\n",
756 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
760 * If we couldn't find a local APIC, then get out of here now!
762 if (APIC_INTEGRATED(apic_version[boot_cpu_id]) && !cpu_has_apic) {
763 printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
765 printk(KERN_ERR "... forcing use of dummy APIC emulation. (tell your hw vendor)\n");
767 cpu_online_map = cpumask_of_cpu(0);
768 phys_cpu_present_map = physid_mask_of_physid(0);
776 * If SMP should be disabled, then really disable it!
779 smp_found_config = 0;
780 printk(KERN_INFO "SMP mode deactivated, forcing use of dummy APIC emulation.\n");
782 cpu_online_map = cpumask_of_cpu(0);
783 phys_cpu_present_map = physid_mask_of_physid(0);
791 if (GET_APIC_ID(apic_read(APIC_ID)) != boot_cpu_id)
794 x86_cpu_to_apicid[0] = boot_cpu_id;
797 * Now scan the CPU present map and fire up the other CPUs.
799 Dprintk("CPU present map: %lx\n", physids_coerce(phys_cpu_present_map));
802 for (bit = 0; kicked < NR_CPUS && bit < MAX_APICS; bit++) {
803 apicid = cpu_present_to_apicid(bit);
805 * Don't even attempt to start the boot CPU!
807 if (apicid == boot_cpu_id || (apicid == BAD_APICID))
810 if (!physid_isset(apicid, phys_cpu_present_map))
812 if ((max_cpus >= 0) && (max_cpus <= cpucount+1))
820 * Cleanup possible dangling ends...
824 * Install writable page 0 entry to set BIOS data area.
829 * Paranoid: Set warm reset code and vector here back
834 *((volatile int *) phys_to_virt(0x467)) = 0;
838 * Allow the user to impress friends.
841 Dprintk("Before bogomips.\n");
843 printk(KERN_INFO "Only one processor found.\n");
845 unsigned long bogosum = 0;
846 for (cpu = 0; cpu < NR_CPUS; cpu++)
847 if (cpu_isset(cpu, cpu_callout_map))
848 bogosum += cpu_data[cpu].loops_per_jiffy;
849 printk(KERN_INFO "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
852 (bogosum/(5000/HZ))%100);
853 Dprintk("Before bogocount - setting activated=1.\n");
857 * Construct cpu_sibling_map[], so that we can tell the
858 * sibling CPU efficiently.
860 for (cpu = 0; cpu < NR_CPUS; cpu++)
861 cpus_clear(cpu_sibling_map[cpu]);
863 for (cpu = 0; cpu < NR_CPUS; cpu++) {
866 if (!cpu_isset(cpu, cpu_callout_map))
869 if (smp_num_siblings > 1) {
870 for (i = 0; i < NR_CPUS; i++) {
871 if (!cpu_isset(i, cpu_callout_map))
873 if (phys_proc_id[cpu] == phys_proc_id[i]) {
875 cpu_set(i, cpu_sibling_map[cpu]);
880 cpu_set(cpu, cpu_sibling_map[cpu]);
883 if (siblings != smp_num_siblings) {
885 "WARNING: %d siblings found for CPU%d, should be %d\n",
886 siblings, cpu, smp_num_siblings);
887 smp_num_siblings = siblings;
891 Dprintk("Boot done.\n");
894 * Here we can be sure that there is an IO-APIC in the system. Let's
897 if (!skip_ioapic_setup && nr_ioapics)
902 setup_boot_APIC_clock();
905 * Synchronize the TSC with the AP
907 if (cpu_has_tsc && cpucount)
908 synchronize_tsc_bp();
914 /* These are wrappers to interface to the new boot process. Someone
915 who understands all this stuff should rewrite it properly. --RR 15/Jul/02 */
916 void __init smp_prepare_cpus(unsigned int max_cpus)
918 smp_boot_cpus(max_cpus);
921 void __devinit smp_prepare_boot_cpu(void)
923 cpu_set(smp_processor_id(), cpu_online_map);
924 cpu_set(smp_processor_id(), cpu_callout_map);
927 int __devinit __cpu_up(unsigned int cpu)
929 /* This only works at boot for x86. See "rewrite" above. */
930 if (cpu_isset(cpu, smp_commenced_mask)) {
935 /* In case one didn't come up */
936 if (!cpu_isset(cpu, cpu_callin_map)) {
942 /* Unleash the CPU! */
943 Dprintk("waiting for cpu %d\n", cpu);
945 cpu_set(cpu, smp_commenced_mask);
946 while (!cpu_isset(cpu, cpu_online_map))
951 void __init smp_cpus_done(unsigned int max_cpus)
953 #ifdef CONFIG_X86_IO_APIC