2 * r2300.c: R2000 and R3000 specific mmu/cache code.
4 * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
6 * with a lot of changes to make this thing work for R3000s
7 * Tx39XX R4k style caches added. HK
8 * Copyright (C) 1998, 1999, 2000 Harald Koerfgen
9 * Copyright (C) 1998 Gleb Raiko & Vladimir Roganov
11 #include <linux/init.h>
12 #include <linux/kernel.h>
13 #include <linux/sched.h>
16 #include <asm/cacheops.h>
18 #include <asm/pgtable.h>
19 #include <asm/mmu_context.h>
20 #include <asm/system.h>
21 #include <asm/isadep.h>
23 #include <asm/bootinfo.h>
26 /* For R3000 cores with R4000 style caches */
27 static unsigned long icache_size, dcache_size; /* Size in bytes */
29 #include <asm/r4kcache.h>
31 extern int r3k_have_wired_reg; /* in r3k-tlb.c */
33 /* This sequence is required to ensure icache is disabled immediately */
34 #define TX39_STOP_STREAMING() \
35 __asm__ __volatile__( \
37 ".set noreorder\n\t" \
44 /* TX39H-style cache flush routines. */
45 static void tx39h_flush_icache_all(void)
47 unsigned long start = KSEG0;
48 unsigned long end = (start + icache_size);
49 unsigned long flags, config;
51 /* disable icache (set ICE#) */
52 local_irq_save(flags);
53 config = read_c0_conf();
54 write_c0_conf(config & ~TX39_CONF_ICE);
55 TX39_STOP_STREAMING();
57 /* invalidate icache */
59 cache16_unroll32(start, Index_Invalidate_I);
63 write_c0_conf(config);
64 local_irq_restore(flags);
67 static void tx39h_dma_cache_wback_inv(unsigned long addr, unsigned long size)
70 unsigned long dc_lsize = current_cpu_data.dcache.linesz;
72 /* Catch bad driver code */
76 a = addr & ~(dc_lsize - 1);
77 end = (addr + size - 1) & ~(dc_lsize - 1);
79 invalidate_dcache_line(a); /* Hit_Invalidate_D */
87 static inline void tx39_blast_dcache_page(unsigned long addr)
89 if (current_cpu_data.cputype != CPU_TX3912)
90 blast_dcache16_page(addr);
93 static inline void tx39_blast_dcache_page_indexed(unsigned long addr)
95 blast_dcache16_page_indexed(addr);
98 static inline void tx39_blast_dcache(void)
103 static inline void tx39_blast_icache_page(unsigned long addr)
105 unsigned long flags, config;
106 /* disable icache (set ICE#) */
107 local_irq_save(flags);
108 config = read_c0_conf();
109 write_c0_conf(config & ~TX39_CONF_ICE);
110 TX39_STOP_STREAMING();
111 blast_icache16_page(addr);
112 write_c0_conf(config);
113 local_irq_restore(flags);
116 static inline void tx39_blast_icache_page_indexed(unsigned long addr)
118 unsigned long flags, config;
119 /* disable icache (set ICE#) */
120 local_irq_save(flags);
121 config = read_c0_conf();
122 write_c0_conf(config & ~TX39_CONF_ICE);
123 TX39_STOP_STREAMING();
124 blast_icache16_page_indexed(addr);
125 write_c0_conf(config);
126 local_irq_restore(flags);
129 static inline void tx39_blast_icache(void)
131 unsigned long flags, config;
132 /* disable icache (set ICE#) */
133 local_irq_save(flags);
134 config = read_c0_conf();
135 write_c0_conf(config & ~TX39_CONF_ICE);
136 TX39_STOP_STREAMING();
138 write_c0_conf(config);
139 local_irq_restore(flags);
142 static inline void tx39_flush_cache_all(void)
144 if (!cpu_has_dc_aliases)
151 static inline void tx39___flush_cache_all(void)
157 static void tx39_flush_cache_mm(struct mm_struct *mm)
159 if (!cpu_has_dc_aliases)
162 if (cpu_context(smp_processor_id(), mm) != 0) {
163 tx39_flush_cache_all();
167 static void tx39_flush_cache_range(struct vm_area_struct *vma,
168 unsigned long start, unsigned long end)
170 struct mm_struct *mm = vma->vm_mm;
172 if (!cpu_has_dc_aliases)
175 if (cpu_context(smp_processor_id(), mm) != 0) {
181 static void tx39_flush_cache_page(struct vm_area_struct *vma,
184 int exec = vma->vm_flags & VM_EXEC;
185 struct mm_struct *mm = vma->vm_mm;
191 * If ownes no valid ASID yet, cannot possibly have gotten
192 * this page into the cache.
194 if (cpu_context(smp_processor_id(), mm) == 0)
198 pgdp = pgd_offset(mm, page);
199 pmdp = pmd_offset(pgdp, page);
200 ptep = pte_offset(pmdp, page);
203 * If the page isn't marked valid, the page cannot possibly be
206 if (!(pte_val(*ptep) & _PAGE_PRESENT))
210 * Doing flushes for another ASID than the current one is
211 * too difficult since stupid R4k caches do a TLB translation
212 * for every cache flush operation. So we do indexed flushes
213 * in that case, which doesn't overly flush the cache too much.
215 if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) {
216 if (cpu_has_dc_aliases || exec)
217 tx39_blast_dcache_page(page);
219 tx39_blast_icache_page(page);
225 * Do indexed flush, too much work to get the (possible) TLB refills
228 page = (KSEG0 + (page & (dcache_size - 1)));
229 if (cpu_has_dc_aliases || exec)
230 tx39_blast_dcache_page_indexed(page);
232 tx39_blast_icache_page_indexed(page);
235 static void tx39_flush_data_cache_page(unsigned long addr)
237 tx39_blast_dcache_page(addr);
240 static void tx39_flush_icache_range(unsigned long start, unsigned long end)
242 unsigned long dc_lsize = current_cpu_data.dcache.linesz;
243 unsigned long addr, aend;
245 if (end - start > dcache_size)
248 addr = start & ~(dc_lsize - 1);
249 aend = (end - 1) & ~(dc_lsize - 1);
252 /* Hit_Writeback_Inv_D */
253 protected_writeback_dcache_line(addr);
260 if (end - start > icache_size)
263 unsigned long flags, config;
264 addr = start & ~(dc_lsize - 1);
265 aend = (end - 1) & ~(dc_lsize - 1);
266 /* disable icache (set ICE#) */
267 local_irq_save(flags);
268 config = read_c0_conf();
269 write_c0_conf(config & ~TX39_CONF_ICE);
270 TX39_STOP_STREAMING();
272 /* Hit_Invalidate_I */
273 protected_flush_icache_line(addr);
278 write_c0_conf(config);
279 local_irq_restore(flags);
284 * Ok, this seriously sucks. We use them to flush a user page but don't
285 * know the virtual address, so we have to blast away the whole icache
286 * which is significantly more expensive than the real thing. Otoh we at
287 * least know the kernel address of the page so we can flush it
290 static void tx39_flush_icache_page(struct vm_area_struct *vma, struct page *page)
294 * If there's no context yet, or the page isn't executable, no icache
297 if (!(vma->vm_flags & VM_EXEC))
300 addr = (unsigned long) page_address(page);
301 tx39_blast_dcache_page(addr);
304 * We're not sure of the virtual address(es) involved here, so
305 * we have to flush the entire I-cache.
310 static void tx39_dma_cache_wback_inv(unsigned long addr, unsigned long size)
312 unsigned long end, a;
314 if (((size | addr) & (PAGE_SIZE - 1)) == 0) {
317 tx39_blast_dcache_page(addr);
319 } while(addr != end);
320 } else if (size > dcache_size) {
323 unsigned long dc_lsize = current_cpu_data.dcache.linesz;
324 a = addr & ~(dc_lsize - 1);
325 end = (addr + size - 1) & ~(dc_lsize - 1);
327 flush_dcache_line(a); /* Hit_Writeback_Inv_D */
334 static void tx39_dma_cache_inv(unsigned long addr, unsigned long size)
336 unsigned long end, a;
338 if (((size | addr) & (PAGE_SIZE - 1)) == 0) {
341 tx39_blast_dcache_page(addr);
343 } while(addr != end);
344 } else if (size > dcache_size) {
347 unsigned long dc_lsize = current_cpu_data.dcache.linesz;
348 a = addr & ~(dc_lsize - 1);
349 end = (addr + size - 1) & ~(dc_lsize - 1);
351 invalidate_dcache_line(a); /* Hit_Invalidate_D */
358 static void tx39_flush_cache_sigtramp(unsigned long addr)
360 unsigned long ic_lsize = current_cpu_data.icache.linesz;
361 unsigned long dc_lsize = current_cpu_data.dcache.linesz;
362 unsigned long config;
365 protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
367 /* disable icache (set ICE#) */
368 local_irq_save(flags);
369 config = read_c0_conf();
370 write_c0_conf(config & ~TX39_CONF_ICE);
371 TX39_STOP_STREAMING();
372 protected_flush_icache_line(addr & ~(ic_lsize - 1));
373 write_c0_conf(config);
374 local_irq_restore(flags);
377 static __init void tx39_probe_cache(void)
379 unsigned long config;
381 config = read_c0_conf();
383 icache_size = 1 << (10 + ((config & TX39_CONF_ICS_MASK) >>
384 TX39_CONF_ICS_SHIFT));
385 dcache_size = 1 << (10 + ((config & TX39_CONF_DCS_MASK) >>
386 TX39_CONF_DCS_SHIFT));
388 current_cpu_data.icache.linesz = 16;
389 switch (current_cpu_data.cputype) {
391 current_cpu_data.icache.ways = 1;
392 current_cpu_data.dcache.ways = 1;
393 current_cpu_data.dcache.linesz = 4;
397 current_cpu_data.icache.ways = 2;
398 current_cpu_data.dcache.ways = 2;
399 current_cpu_data.dcache.linesz = 16;
404 current_cpu_data.icache.ways = 1;
405 current_cpu_data.dcache.ways = 1;
406 current_cpu_data.dcache.linesz = 16;
411 void __init ld_mmu_tx39(void)
413 extern void build_clear_page(void);
414 extern void build_copy_page(void);
415 unsigned long config;
417 config = read_c0_conf();
418 config &= ~TX39_CONF_WBON;
419 write_c0_conf(config);
423 switch (current_cpu_data.cputype) {
425 /* TX39/H core (writethru direct-map cache) */
426 flush_cache_all = tx39h_flush_icache_all;
427 __flush_cache_all = tx39h_flush_icache_all;
428 flush_cache_mm = (void *) tx39h_flush_icache_all;
429 flush_cache_range = (void *) tx39h_flush_icache_all;
430 flush_cache_page = (void *) tx39h_flush_icache_all;
431 flush_icache_page = (void *) tx39h_flush_icache_all;
432 flush_icache_range = (void *) tx39h_flush_icache_all;
434 flush_cache_sigtramp = (void *) tx39h_flush_icache_all;
435 flush_data_cache_page = (void *) tx39h_flush_icache_all;
437 _dma_cache_wback_inv = tx39h_dma_cache_wback_inv;
439 shm_align_mask = PAGE_SIZE - 1;
446 /* TX39/H2,H3 core (writeback 2way-set-associative cache) */
447 r3k_have_wired_reg = 1;
448 write_c0_wired(0); /* set 8 on reset... */
449 /* board-dependent init code may set WBON */
451 flush_cache_all = tx39_flush_cache_all;
452 __flush_cache_all = tx39___flush_cache_all;
453 flush_cache_mm = tx39_flush_cache_mm;
454 flush_cache_range = tx39_flush_cache_range;
455 flush_cache_page = tx39_flush_cache_page;
456 flush_icache_page = tx39_flush_icache_page;
457 flush_icache_range = tx39_flush_icache_range;
459 flush_cache_sigtramp = tx39_flush_cache_sigtramp;
460 flush_data_cache_page = tx39_flush_data_cache_page;
462 _dma_cache_wback_inv = tx39_dma_cache_wback_inv;
463 _dma_cache_wback = tx39_dma_cache_wback_inv;
464 _dma_cache_inv = tx39_dma_cache_inv;
466 shm_align_mask = max_t(unsigned long,
467 (dcache_size / current_cpu_data.dcache.ways) - 1,
473 current_cpu_data.icache.waysize = icache_size / current_cpu_data.icache.ways;
474 current_cpu_data.dcache.waysize = dcache_size / current_cpu_data.dcache.ways;
476 current_cpu_data.icache.sets =
477 current_cpu_data.icache.waysize / current_cpu_data.icache.linesz;
478 current_cpu_data.dcache.sets =
479 current_cpu_data.dcache.waysize / current_cpu_data.dcache.linesz;
481 if (current_cpu_data.dcache.waysize > PAGE_SIZE)
482 current_cpu_data.dcache.flags |= MIPS_CACHE_ALIASES;
484 current_cpu_data.icache.waybit = 0;
485 current_cpu_data.dcache.waybit = 0;
487 printk("Primary instruction cache %ldkB, linesize %d bytes\n",
488 icache_size >> 10, current_cpu_data.icache.linesz);
489 printk("Primary data cache %ldkB, linesize %d bytes\n",
490 dcache_size >> 10, current_cpu_data.dcache.linesz);