2 Madge Horizon ATM Adapter driver.
3 Copyright (C) 1995-1999 Madge Networks Ltd.
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 The GNU GPL is contained in /usr/doc/copyright/GPL on a Debian
20 system and in the file COPYING in the Linux kernel source.
24 IMPORTANT NOTE: Madge Networks no longer makes the adapters
25 supported by this driver and makes no commitment to maintain it.
28 #include <linux/module.h>
29 #include <linux/kernel.h>
31 #include <linux/pci.h>
32 #include <linux/errno.h>
33 #include <linux/atm.h>
34 #include <linux/atmdev.h>
35 #include <linux/sonet.h>
36 #include <linux/skbuff.h>
37 #include <linux/time.h>
38 #include <linux/delay.h>
39 #include <linux/uio.h>
40 #include <linux/init.h>
41 #include <linux/ioport.h>
43 #include <asm/system.h>
45 #include <asm/atomic.h>
46 #include <asm/uaccess.h>
47 #include <asm/string.h>
48 #include <asm/byteorder.h>
52 #define maintainer_string "Giuliano Procida at Madge Networks <gprocida@madge.com>"
53 #define description_string "Madge ATM Horizon [Ultra] driver"
54 #define version_string "1.2.1"
56 static inline void __init show_version (void) {
57 printk ("%s version %s\n", description_string, version_string);
64 Driver and documentation by:
66 Chris Aston Madge Networks
67 Giuliano Procida Madge Networks
68 Simon Benham Madge Networks
69 Simon Johnson Madge Networks
70 Various Others Madge Networks
72 Some inspiration taken from other drivers by:
75 Kari Mettinen University of Helsinki
76 Werner Almesberger EPFL LRC
80 I Hardware, detection, initialisation and shutdown.
84 This driver should handle all variants of the PCI Madge ATM adapters
85 with the Horizon chipset. These are all PCI cards supporting PIO, BM
86 DMA and a form of MMIO (registers only, not internal RAM).
88 The driver is only known to work with SONET and UTP Horizon Ultra
89 cards at 155Mb/s. However, code is in place to deal with both the
90 original Horizon and 25Mb/s operation.
92 There are two revisions of the Horizon ASIC: the original and the
93 Ultra. Details of hardware bugs are in section III.
95 The ASIC version can be distinguished by chip markings but is NOT
96 indicated by the PCI revision (all adapters seem to have PCI rev 1).
100 Horizon => Collage 25 PCI Adapter (UTP and STP)
101 Horizon Ultra => Collage 155 PCI Client (UTP or SONET)
102 Ambassador x => Collage 155 PCI Server (completely different)
104 Horizon (25Mb/s) is fitted with UTP and STP connectors. It seems to
105 have a Madge B154 plus glue logic serializer. I have also found a
106 really ancient version of this with slightly different glue. It
107 comes with the revision 0 (140-025-01) ASIC.
109 Horizon Ultra (155Mb/s) is fitted with either a Pulse Medialink
110 output (UTP) or an HP HFBR 5205 output (SONET). It has either
111 Madge's SAMBA framer or a SUNI-lite device (early versions). It
112 comes with the revision 1 (140-027-01) ASIC.
116 All Horizon-based cards present with the same PCI Vendor and Device
117 IDs. The standard Linux 2.2 PCI API is used to locate any cards and
118 to enable bus-mastering (with appropriate latency).
120 ATM_LAYER_STATUS in the control register distinguishes between the
121 two possible physical layers (25 and 155). It is not clear whether
122 the 155 cards can also operate at 25Mbps. We rely on the fact that a
123 card operates at 155 if and only if it has the newer Horizon Ultra
126 For 155 cards the two possible framers are probed for and then set
131 The card is reset and then put into a known state. The physical
132 layer is configured for normal operation at the appropriate speed;
133 in the case of the 155 cards, the framer is initialised with
134 line-based timing; the internal RAM is zeroed and the allocation of
135 buffers for RX and TX is made; the Burnt In Address is read and
136 copied to the ATM ESI; various policy settings for RX (VPI bits,
137 unknown VCs, oam cells) are made. Ideally all policy items should be
138 configurable at module load (if not actually on-demand), however,
139 only the vpi vs vci bit allocation can be specified at insmod.
143 This is in response to module_cleaup. No VCs are in use and the card
144 should be idle; it is reset.
146 II Driver software (as it should be)
148 0. Traffic Parameters
150 The traffic classes (not an enumeration) are currently: ATM_NONE (no
151 traffic), ATM_UBR, ATM_CBR, ATM_VBR and ATM_ABR, ATM_ANYCLASS
152 (compatible with everything). Together with (perhaps only some of)
153 the following items they make up the traffic specification.
156 unsigned char traffic_class; traffic class (ATM_UBR, ...)
157 int max_pcr; maximum PCR in cells per second
158 int pcr; desired PCR in cells per second
159 int min_pcr; minimum PCR in cells per second
160 int max_cdv; maximum CDV in microseconds
161 int max_sdu; maximum SDU in bytes
164 Note that these denote bandwidth available not bandwidth used; the
165 possibilities according to ATMF are:
167 Real Time (cdv and max CDT given)
169 CBR(pcr) pcr bandwidth always available
170 rtVBR(pcr,scr,mbs) scr bandwidth always available, upto pcr at mbs too
174 nrtVBR(pcr,scr,mbs) scr bandwidth always available, upto pcr at mbs too
176 ABR(mcr,pcr) mcr bandwidth always available, upto pcr (depending) too
178 mbs is max burst size (bucket)
179 pcr and scr have associated cdvt values
180 mcr is like scr but has no cdtv
181 cdtv may differ at each hop
183 Some of the above items are qos items (as opposed to traffic
184 parameters). We have nothing to do with qos. All except ABR can have
185 their traffic parameters converted to GCRA parameters. The GCRA may
186 be implemented as a (real-number) leaky bucket. The GCRA can be used
187 in complicated ways by switches and in simpler ways by end-stations.
188 It can be used both to filter incoming cells and shape out-going
191 ATM Linux actually supports:
193 ATM_NONE() (no traffic in this direction)
194 ATM_UBR(max_frame_size)
195 ATM_CBR(max/min_pcr, max_cdv, max_frame_size)
197 0 or ATM_MAX_PCR are used to indicate maximum available PCR
199 A traffic specification consists of the AAL type and separate
200 traffic specifications for either direction. In ATM Linux it is:
203 struct atm_trafprm txtp;
204 struct atm_trafprm rxtp;
210 ATM_NO_AAL AAL not specified
211 ATM_AAL0 "raw" ATM cells
214 ATM_AAL34 AAL3/4 (data)
216 ATM_SAAL signaling AAL
218 The Horizon has support for AAL frame types: 0, 3/4 and 5. However,
219 it does not implement AAL 3/4 SAR and it has a different notion of
220 "raw cell" to ATM Linux's (48 bytes vs. 52 bytes) so neither are
221 supported by this driver.
223 The Horizon has limited support for ABR (including UBR), VBR and
224 CBR. Each TX channel has a bucket (containing up to 31 cell units)
225 and two timers (PCR and SCR) associated with it that can be used to
226 govern cell emissions and host notification (in the case of ABR this
227 is presumably so that RM cells may be emitted at appropriate times).
228 The timers may either be disabled or may be set to any of 240 values
229 (determined by the clock crystal, a fixed (?) per-device divider, a
230 configurable divider and a configurable timer preload value).
232 At the moment only UBR and CBR are supported by the driver. VBR will
233 be supported as soon as ATM for Linux supports it. ABR support is
234 very unlikely as RM cell handling is completely up to the driver.
236 1. TX (TX channel setup and TX transfer)
238 The TX half of the driver owns the TX Horizon registers. The TX
239 component in the IRQ handler is the BM completion handler. This can
240 only be entered when tx_busy is true (enforced by hardware). The
241 other TX component can only be entered when tx_busy is false
242 (enforced by driver). So TX is single-threaded.
244 Apart from a minor optimisation to not re-select the last channel,
245 the TX send component works as follows:
247 Atomic test and set tx_busy until we succeed; we should implement
248 some sort of timeout so that tx_busy will never be stuck at true.
250 If no TX channel is set up for this VC we wait for an idle one (if
251 necessary) and set it up.
253 At this point we have a TX channel ready for use. We wait for enough
254 buffers to become available then start a TX transmit (set the TX
255 descriptor, schedule transfer, exit).
257 The IRQ component handles TX completion (stats, free buffer, tx_busy
258 unset, exit). We also re-schedule further transfers for the same
261 TX setup in more detail:
263 TX open is a nop, the relevant information is held in the hrz_vcc
264 (vcc->dev_data) structure and is "cached" on the card.
266 TX close gets the TX lock and clears the channel from the "cache".
268 2. RX (Data Available and RX transfer)
270 The RX half of the driver owns the RX registers. There are two RX
271 components in the IRQ handler: the data available handler deals with
272 fresh data that has arrived on the card, the BM completion handler
273 is very similar to the TX completion handler. The data available
274 handler grabs the rx_lock and it is only released once the data has
275 been discarded or completely transferred to the host. The BM
276 completion handler only runs when the lock is held; the data
277 available handler is locked out over the same period.
279 Data available on the card triggers an interrupt. If the data is not
280 suitable for our existing RX channels or we cannot allocate a buffer
281 it is flushed. Otherwise an RX receive is scheduled. Multiple RX
282 transfers may be scheduled for the same frame.
284 RX setup in more detail:
291 0. Byte vs Word addressing of adapter RAM.
293 A design feature; see the .h file (especially the memory map).
295 1. Bus Master Data Transfers (original Horizon only, fixed in Ultra)
297 The host must not start a transmit direction transfer at a
298 non-four-byte boundary in host memory. Instead the host should
299 perform a byte, or a two byte, or one byte followed by two byte
300 transfer in order to start the rest of the transfer on a four byte
303 Simultaneous transmit and receive direction bus master transfers are
306 The simplest solution to these two is to always do PIO (never DMA)
307 in the TX direction on the original Horizon. More complicated
308 solutions are likely to hurt my brain.
310 2. Loss of buffer on close VC
312 When a VC is being closed, the buffer associated with it is not
313 returned to the pool. The host must store the reference to this
314 buffer and when opening a new VC then give it to that new VC.
316 The host intervention currently consists of stacking such a buffer
317 pointer at VC close and checking the stack at VC open.
319 3. Failure to close a VC
321 If a VC is currently receiving a frame then closing the VC may fail
322 and the frame continues to be received.
324 The solution is to make sure any received frames are flushed when
325 ready. This is currently done just before the solution to 2.
327 4. PCI bus (original Horizon only, fixed in Ultra)
329 Reading from the data port prior to initialisation will hang the PCI
330 bus. Just don't do that then! We don't.
334 . Timer code may be broken.
336 . Allow users to specify buffer allocation split for TX and RX.
338 . Deal once and for all with buggy VC close.
340 . Handle interrupted and/or non-blocking operations.
342 . Change some macros to functions and move from .h to .c.
344 . Try to limit the number of TX frames each VC may have queued, in
345 order to reduce the chances of TX buffer exhaustion.
347 . Implement VBR (bucket and timers not understood) and ABR (need to
348 do RM cells manually); also no Linux support for either.
350 . Implement QoS changes on open VCs (involves extracting parts of VC open
351 and close into separate functions and using them to make changes).
355 /********** globals **********/
357 static hrz_dev * hrz_devs = NULL;
358 static struct timer_list housekeeping;
360 static unsigned short debug = 0;
361 static unsigned short vpi_bits = 0;
362 static int max_tx_size = 9000;
363 static int max_rx_size = 9000;
364 static unsigned char pci_lat = 0;
366 /********** access functions **********/
368 /* Read / Write Horizon registers */
369 static inline void wr_regl (const hrz_dev * dev, unsigned char reg, u32 data) {
370 outl (cpu_to_le32 (data), dev->iobase + reg);
373 static inline u32 rd_regl (const hrz_dev * dev, unsigned char reg) {
374 return le32_to_cpu (inl (dev->iobase + reg));
377 static inline void wr_regw (const hrz_dev * dev, unsigned char reg, u16 data) {
378 outw (cpu_to_le16 (data), dev->iobase + reg);
381 static inline u16 rd_regw (const hrz_dev * dev, unsigned char reg) {
382 return le16_to_cpu (inw (dev->iobase + reg));
385 static inline void wrs_regb (const hrz_dev * dev, unsigned char reg, void * addr, u32 len) {
386 outsb (dev->iobase + reg, addr, len);
389 static inline void rds_regb (const hrz_dev * dev, unsigned char reg, void * addr, u32 len) {
390 insb (dev->iobase + reg, addr, len);
393 /* Read / Write to a given address in Horizon buffer memory.
394 Interrupts must be disabled between the address register and data
395 port accesses as these must form an atomic operation. */
396 static inline void wr_mem (const hrz_dev * dev, HDW * addr, u32 data) {
397 // wr_regl (dev, MEM_WR_ADDR_REG_OFF, (u32) addr);
398 wr_regl (dev, MEM_WR_ADDR_REG_OFF, (addr - (HDW *) 0) * sizeof(HDW));
399 wr_regl (dev, MEMORY_PORT_OFF, data);
402 static inline u32 rd_mem (const hrz_dev * dev, HDW * addr) {
403 // wr_regl (dev, MEM_RD_ADDR_REG_OFF, (u32) addr);
404 wr_regl (dev, MEM_RD_ADDR_REG_OFF, (addr - (HDW *) 0) * sizeof(HDW));
405 return rd_regl (dev, MEMORY_PORT_OFF);
408 static inline void wr_framer (const hrz_dev * dev, u32 addr, u32 data) {
409 wr_regl (dev, MEM_WR_ADDR_REG_OFF, (u32) addr | 0x80000000);
410 wr_regl (dev, MEMORY_PORT_OFF, data);
413 static inline u32 rd_framer (const hrz_dev * dev, u32 addr) {
414 wr_regl (dev, MEM_RD_ADDR_REG_OFF, (u32) addr | 0x80000000);
415 return rd_regl (dev, MEMORY_PORT_OFF);
418 /********** specialised access functions **********/
422 static inline void FLUSH_RX_CHANNEL (hrz_dev * dev, u16 channel) {
423 wr_regw (dev, RX_CHANNEL_PORT_OFF, FLUSH_CHANNEL | channel);
427 static inline void WAIT_FLUSH_RX_COMPLETE (hrz_dev * dev) {
428 while (rd_regw (dev, RX_CHANNEL_PORT_OFF) & FLUSH_CHANNEL)
433 static inline void SELECT_RX_CHANNEL (hrz_dev * dev, u16 channel) {
434 wr_regw (dev, RX_CHANNEL_PORT_OFF, channel);
438 static inline void WAIT_UPDATE_COMPLETE (hrz_dev * dev) {
439 while (rd_regw (dev, RX_CHANNEL_PORT_OFF) & RX_CHANNEL_UPDATE_IN_PROGRESS)
446 static inline void SELECT_TX_CHANNEL (hrz_dev * dev, u16 tx_channel) {
447 wr_regl (dev, TX_CHANNEL_PORT_OFF, tx_channel);
451 /* Update or query one configuration parameter of a particular channel. */
453 static inline void update_tx_channel_config (hrz_dev * dev, short chan, u8 mode, u16 value) {
454 wr_regw (dev, TX_CHANNEL_CONFIG_COMMAND_OFF,
455 chan * TX_CHANNEL_CONFIG_MULT | mode);
456 wr_regw (dev, TX_CHANNEL_CONFIG_DATA_OFF, value);
460 static inline u16 query_tx_channel_config (hrz_dev * dev, short chan, u8 mode) {
461 wr_regw (dev, TX_CHANNEL_CONFIG_COMMAND_OFF,
462 chan * TX_CHANNEL_CONFIG_MULT | mode);
463 return rd_regw (dev, TX_CHANNEL_CONFIG_DATA_OFF);
466 /********** dump functions **********/
468 static inline void dump_skb (char * prefix, unsigned int vc, struct sk_buff * skb) {
471 unsigned char * data = skb->data;
472 PRINTDB (DBG_DATA, "%s(%u) ", prefix, vc);
473 for (i=0; i<skb->len && i < 256;i++)
474 PRINTDM (DBG_DATA, "%02x ", data[i]);
475 PRINTDE (DBG_DATA,"");
484 static inline void dump_regs (hrz_dev * dev) {
486 PRINTD (DBG_REGS, "CONTROL 0: %#x", rd_regl (dev, CONTROL_0_REG));
487 PRINTD (DBG_REGS, "RX CONFIG: %#x", rd_regw (dev, RX_CONFIG_OFF));
488 PRINTD (DBG_REGS, "TX CONFIG: %#x", rd_regw (dev, TX_CONFIG_OFF));
489 PRINTD (DBG_REGS, "TX STATUS: %#x", rd_regw (dev, TX_STATUS_OFF));
490 PRINTD (DBG_REGS, "IRQ ENBLE: %#x", rd_regl (dev, INT_ENABLE_REG_OFF));
491 PRINTD (DBG_REGS, "IRQ SORCE: %#x", rd_regl (dev, INT_SOURCE_REG_OFF));
498 static inline void dump_framer (hrz_dev * dev) {
501 PRINTDB (DBG_REGS, "framer registers:");
502 for (i = 0; i < 0x10; ++i)
503 PRINTDM (DBG_REGS, " %02x", rd_framer (dev, i));
504 PRINTDE (DBG_REGS,"");
511 /********** VPI/VCI <-> (RX) channel conversions **********/
513 /* RX channels are 10 bit integers, these fns are quite paranoid */
515 static inline int channel_to_vpivci (const u16 channel, short * vpi, int * vci) {
516 unsigned short vci_bits = 10 - vpi_bits;
517 if ((channel & RX_CHANNEL_MASK) == channel) {
518 *vci = channel & ((~0)<<vci_bits);
519 *vpi = channel >> vci_bits;
520 return channel ? 0 : -EINVAL;
525 static inline int vpivci_to_channel (u16 * channel, const short vpi, const int vci) {
526 unsigned short vci_bits = 10 - vpi_bits;
527 if (0 <= vpi && vpi < 1<<vpi_bits && 0 <= vci && vci < 1<<vci_bits) {
528 *channel = vpi<<vci_bits | vci;
529 return *channel ? 0 : -EINVAL;
534 /********** decode RX queue entries **********/
536 static inline u16 rx_q_entry_to_length (u32 x) {
537 return x & RX_Q_ENTRY_LENGTH_MASK;
540 static inline u16 rx_q_entry_to_rx_channel (u32 x) {
541 return (x>>RX_Q_ENTRY_CHANNEL_SHIFT) & RX_CHANNEL_MASK;
544 /* Cell Transmit Rate Values
546 * the cell transmit rate (cells per sec) can be set to a variety of
547 * different values by specifying two parameters: a timer preload from
548 * 1 to 16 (stored as 0 to 15) and a clock divider (2 to the power of
549 * an exponent from 0 to 14; the special value 15 disables the timer).
551 * cellrate = baserate / (preload * 2^divider)
553 * The maximum cell rate that can be specified is therefore just the
554 * base rate. Halving the preload is equivalent to adding 1 to the
555 * divider and so values 1 to 8 of the preload are redundant except
556 * in the case of a maximal divider (14).
558 * Given a desired cell rate, an algorithm to determine the preload
561 * a) x = baserate / cellrate, want p * 2^d = x (as far as possible)
562 * b) if x > 16 * 2^14 then set p = 16, d = 14 (min rate), done
563 * if x <= 16 then set p = x, d = 0 (high rates), done
564 * c) now have 16 < x <= 2^18, or 1 < x/16 <= 2^14 and we want to
565 * know n such that 2^(n-1) < x/16 <= 2^n, so slide a bit until
566 * we find the range (n will be between 1 and 14), set d = n
567 * d) Also have 8 < x/2^n <= 16, so set p nearest x/2^n
569 * The algorithm used below is a minor variant of the above.
571 * The base rate is derived from the oscillator frequency (Hz) using a
574 * baserate = freq / 32 in the case of some Unknown Card
575 * baserate = freq / 8 in the case of the Horizon 25
576 * baserate = freq / 8 in the case of the Horizon Ultra 155
578 * The Horizon cards have oscillators and base rates as follows:
580 * Card Oscillator Base Rate
581 * Unknown Card 33 MHz 1.03125 MHz (33 MHz = PCI freq)
582 * Horizon 25 32 MHz 4 MHz
583 * Horizon Ultra 155 40 MHz 5 MHz
585 * The following defines give the base rates in Hz. These were
586 * previously a factor of 100 larger, no doubt someone was using
590 #define BR_UKN 1031250l
591 #define BR_HRZ 4000000l
592 #define BR_ULT 5000000l
598 // p ranges from 1 to a power of 2
601 static int make_rate (const hrz_dev * dev, u32 c, rounding r,
602 u16 * bits, unsigned int * actual) {
604 // note: rounding the rate down means rounding 'p' up
606 const unsigned long br = test_bit(ultra, &dev->flags) ? BR_ULT : BR_HRZ;
611 // local fn to build the timer bits
614 if (div > CR_MAXD || (!pre) || pre > 1<<CR_MAXPEXP) {
615 PRINTD (DBG_QOS, "set_cr internal failure: d=%u p=%u",
620 *bits = (div<<CLOCK_SELECT_SHIFT) | (pre-1);
622 *actual = (br + (pre<<div) - 1) / (pre<<div);
623 PRINTD (DBG_QOS, "actual rate: %u", *actual);
629 // br_exp and br_man are used to avoid overflowing (c*maxp*2^d) in
630 // the tests below. We could think harder about exact possibilities
633 unsigned long br_man = br;
634 unsigned int br_exp = 0;
636 PRINTD (DBG_QOS|DBG_FLOW, "make_rate b=%lu, c=%u, %s", br, c,
637 (r == round_up) ? "up" : (r == round_down) ? "down" : "nearest");
641 PRINTD (DBG_QOS|DBG_ERR, "zero rate is not allowed!");
645 while (br_exp < CR_MAXPEXP + CR_MIND && (br_man % 2 == 0)) {
646 br_man = br_man >> 1;
649 // (br >>br_exp) <<br_exp == br and
650 // br_exp <= CR_MAXPEXP+CR_MIND
652 if (br_man <= (c << (CR_MAXPEXP+CR_MIND-br_exp))) {
653 // Equivalent to: B <= (c << (MAXPEXP+MIND))
654 // take care of rounding
657 pre = (br+(c<<div)-1)/(c<<div);
658 // but p must be non-zero
663 pre = (br+(c<<div)/2)/(c<<div);
664 // but p must be non-zero
670 // but p must be non-zero
675 PRINTD (DBG_QOS, "A: p=%u, d=%u", pre, div);
679 // at this point we have
680 // d == MIND and (c << (MAXPEXP+MIND)) < B
681 while (div < CR_MAXD) {
683 if (br_man <= (c << (CR_MAXPEXP+div-br_exp))) {
684 // Equivalent to: B <= (c << (MAXPEXP+d))
685 // c << (MAXPEXP+d-1) < B <= c << (MAXPEXP+d)
686 // 1 << (MAXPEXP-1) < B/2^d/c <= 1 << MAXPEXP
687 // MAXP/2 < B/c2^d <= MAXP
688 // take care of rounding
691 pre = (br+(c<<div)-1)/(c<<div);
694 pre = (br+(c<<div)/2)/(c<<div);
700 PRINTD (DBG_QOS, "B: p=%u, d=%u", pre, div);
704 // at this point we have
705 // d == MAXD and (c << (MAXPEXP+MAXD)) < B
706 // but we cannot go any higher
707 // take care of rounding
717 pre = 1 << CR_MAXPEXP;
718 PRINTD (DBG_QOS, "C: p=%u, d=%u", pre, div);
722 static int make_rate_with_tolerance (const hrz_dev * dev, u32 c, rounding r, unsigned int tol,
723 u16 * bit_pattern, unsigned int * actual) {
724 unsigned int my_actual;
726 PRINTD (DBG_QOS|DBG_FLOW, "make_rate_with_tolerance c=%u, %s, tol=%u",
727 c, (r == round_up) ? "up" : (r == round_down) ? "down" : "nearest", tol);
730 // actual rate is not returned
733 if (make_rate (dev, c, round_nearest, bit_pattern, actual))
734 // should never happen as round_nearest always succeeds
737 if (c - tol <= *actual && *actual <= c + tol)
741 // intolerant, try rounding instead
742 return make_rate (dev, c, r, bit_pattern, actual);
745 /********** Listen on a VC **********/
747 static int hrz_open_rx (hrz_dev * dev, u16 channel) {
748 // is there any guarantee that we don't get two simulataneous
749 // identical calls of this function from different processes? yes
752 u32 channel_type; // u16?
754 u16 buf_ptr = RX_CHANNEL_IDLE;
756 rx_ch_desc * rx_desc = &memmap->rx_descs[channel];
758 PRINTD (DBG_FLOW, "hrz_open_rx %x", channel);
760 spin_lock_irqsave (&dev->mem_lock, flags);
761 channel_type = rd_mem (dev, &rx_desc->wr_buf_type) & BUFFER_PTR_MASK;
762 spin_unlock_irqrestore (&dev->mem_lock, flags);
764 // very serious error, should never occur
765 if (channel_type != RX_CHANNEL_DISABLED) {
766 PRINTD (DBG_ERR|DBG_VCC, "RX channel for VC already open");
767 return -EBUSY; // clean up?
770 // Give back spare buffer
771 if (dev->noof_spare_buffers) {
772 buf_ptr = dev->spare_buffers[--dev->noof_spare_buffers];
773 PRINTD (DBG_VCC, "using a spare buffer: %u", buf_ptr);
774 // should never occur
775 if (buf_ptr == RX_CHANNEL_DISABLED || buf_ptr == RX_CHANNEL_IDLE) {
776 // but easy to recover from
777 PRINTD (DBG_ERR|DBG_VCC, "bad spare buffer pointer, using IDLE");
778 buf_ptr = RX_CHANNEL_IDLE;
781 PRINTD (DBG_VCC, "using IDLE buffer pointer");
784 // Channel is currently disabled so change its status to idle
786 // do we really need to save the flags again?
787 spin_lock_irqsave (&dev->mem_lock, flags);
789 wr_mem (dev, &rx_desc->wr_buf_type,
790 buf_ptr | CHANNEL_TYPE_AAL5 | FIRST_CELL_OF_AAL5_FRAME);
791 if (buf_ptr != RX_CHANNEL_IDLE)
792 wr_mem (dev, &rx_desc->rd_buf_type, buf_ptr);
794 spin_unlock_irqrestore (&dev->mem_lock, flags);
796 // rxer->rate = make_rate (qos->peak_cells);
798 PRINTD (DBG_FLOW, "hrz_open_rx ok");
804 /********** change vc rate for a given vc **********/
806 static void hrz_change_vc_qos (ATM_RXER * rxer, MAAL_QOS * qos) {
807 rxer->rate = make_rate (qos->peak_cells);
811 /********** free an skb (as per ATM device driver documentation) **********/
813 static inline void hrz_kfree_skb (struct sk_buff * skb) {
814 if (ATM_SKB(skb)->vcc->pop) {
815 ATM_SKB(skb)->vcc->pop (ATM_SKB(skb)->vcc, skb);
817 dev_kfree_skb_any (skb);
821 /********** cancel listen on a VC **********/
823 static void hrz_close_rx (hrz_dev * dev, u16 vc) {
830 rx_ch_desc * rx_desc = &memmap->rx_descs[vc];
834 spin_lock_irqsave (&dev->mem_lock, flags);
835 value = rd_mem (dev, &rx_desc->wr_buf_type) & BUFFER_PTR_MASK;
836 spin_unlock_irqrestore (&dev->mem_lock, flags);
838 if (value == RX_CHANNEL_DISABLED) {
839 // I suppose this could happen once we deal with _NONE traffic properly
840 PRINTD (DBG_VCC, "closing VC: RX channel %u already disabled", vc);
843 if (value == RX_CHANNEL_IDLE)
846 spin_lock_irqsave (&dev->mem_lock, flags);
849 wr_mem (dev, &rx_desc->wr_buf_type, RX_CHANNEL_DISABLED);
851 if ((rd_mem (dev, &rx_desc->wr_buf_type) & BUFFER_PTR_MASK) == RX_CHANNEL_DISABLED)
858 spin_unlock_irqrestore (&dev->mem_lock, flags);
862 WAIT_FLUSH_RX_COMPLETE(dev);
864 // XXX Is this all really necessary? We can rely on the rx_data_av
865 // handler to discard frames that remain queued for delivery. If the
866 // worry is that immediately reopening the channel (perhaps by a
867 // different process) may cause some data to be mis-delivered then
868 // there may still be a simpler solution (such as busy-waiting on
869 // rx_busy once the channel is disabled or before a new one is
870 // opened - does this leave any holes?). Arguably setting up and
871 // tearing down the TX and RX halves of each virtual circuit could
872 // most safely be done within ?x_busy protected regions.
874 // OK, current changes are that Simon's marker is disabled and we DO
875 // look for NULL rxer elsewhere. The code here seems flush frames
876 // and then remember the last dead cell belonging to the channel
877 // just disabled - the cell gets relinked at the next vc_open.
878 // However, when all VCs are closed or only a few opened there are a
879 // handful of buffers that are unusable.
881 // Does anyone feel like documenting spare_buffers properly?
882 // Does anyone feel like fixing this in a nicer way?
884 // Flush any data which is left in the channel
886 // Change the rx channel port to something different to the RX
887 // channel we are trying to close to force Horizon to flush the rx
888 // channel read and write pointers.
890 u16 other = vc^(RX_CHANS/2);
892 SELECT_RX_CHANNEL (dev, other);
893 WAIT_UPDATE_COMPLETE (dev);
895 r1 = rd_mem (dev, &rx_desc->rd_buf_type);
897 // Select this RX channel. Flush doesn't seem to work unless we
898 // select an RX channel before hand
900 SELECT_RX_CHANNEL (dev, vc);
901 WAIT_UPDATE_COMPLETE (dev);
903 // Attempt to flush a frame on this RX channel
905 FLUSH_RX_CHANNEL (dev, vc);
906 WAIT_FLUSH_RX_COMPLETE (dev);
908 // Force Horizon to flush rx channel read and write pointers as before
910 SELECT_RX_CHANNEL (dev, other);
911 WAIT_UPDATE_COMPLETE (dev);
913 r2 = rd_mem (dev, &rx_desc->rd_buf_type);
915 PRINTD (DBG_VCC|DBG_RX, "r1 = %u, r2 = %u", r1, r2);
918 dev->spare_buffers[dev->noof_spare_buffers++] = (u16)r1;
925 rx_q_entry * wr_ptr = &memmap->rx_q_entries[rd_regw (dev, RX_QUEUE_WR_PTR_OFF)];
926 rx_q_entry * rd_ptr = dev->rx_q_entry;
928 PRINTD (DBG_VCC|DBG_RX, "rd_ptr = %u, wr_ptr = %u", rd_ptr, wr_ptr);
930 while (rd_ptr != wr_ptr) {
931 u32 x = rd_mem (dev, (HDW *) rd_ptr);
933 if (vc == rx_q_entry_to_rx_channel (x)) {
934 x |= SIMONS_DODGEY_MARKER;
936 PRINTD (DBG_RX|DBG_VCC|DBG_WARN, "marking a frame as dodgey");
938 wr_mem (dev, (HDW *) rd_ptr, x);
941 if (rd_ptr == dev->rx_q_wrap)
942 rd_ptr = dev->rx_q_reset;
949 spin_unlock_irqrestore (&dev->mem_lock, flags);
954 /********** schedule RX transfers **********/
956 // Note on tail recursion: a GCC developer said that it is not likely
957 // to be fixed soon, so do not define TAILRECUSRIONWORKS unless you
958 // are sure it does as you may otherwise overflow the kernel stack.
960 // giving this fn a return value would help GCC, alledgedly
962 static void rx_schedule (hrz_dev * dev, int irq) {
963 unsigned int rx_bytes;
966 #ifndef TAILRECURSIONWORKS
968 while (pio_instead) {
970 // bytes waiting for RX transfer
971 rx_bytes = dev->rx_bytes;
975 while (rd_regl (dev, MASTER_RX_COUNT_REG_OFF)) {
976 PRINTD (DBG_RX|DBG_WARN, "RX error: other PCI Bus Master RX still in progress!");
977 if (++spin_count > 10) {
978 PRINTD (DBG_RX|DBG_ERR, "spun out waiting PCI Bus Master RX completion");
979 wr_regl (dev, MASTER_RX_COUNT_REG_OFF, 0);
980 clear_bit (rx_busy, &dev->flags);
981 hrz_kfree_skb (dev->rx_skb);
987 // this code follows the TX code but (at the moment) there is only
988 // one region - the skb itself. I don't know if this will change,
989 // but it doesn't hurt to have the code here, disabled.
992 // start next transfer within same region
993 if (rx_bytes <= MAX_PIO_COUNT) {
994 PRINTD (DBG_RX|DBG_BUS, "(pio)");
997 if (rx_bytes <= MAX_TRANSFER_COUNT) {
998 PRINTD (DBG_RX|DBG_BUS, "(simple or last multi)");
1001 PRINTD (DBG_RX|DBG_BUS, "(continuing multi)");
1002 dev->rx_bytes = rx_bytes - MAX_TRANSFER_COUNT;
1003 rx_bytes = MAX_TRANSFER_COUNT;
1006 // rx_bytes == 0 -- we're between regions
1007 // regions remaining to transfer
1009 unsigned int rx_regions = dev->rx_regions;
1011 unsigned int rx_regions = 0;
1016 // start a new region
1017 dev->rx_addr = dev->rx_iovec->iov_base;
1018 rx_bytes = dev->rx_iovec->iov_len;
1020 dev->rx_regions = rx_regions - 1;
1022 if (rx_bytes <= MAX_PIO_COUNT) {
1023 PRINTD (DBG_RX|DBG_BUS, "(pio)");
1026 if (rx_bytes <= MAX_TRANSFER_COUNT) {
1027 PRINTD (DBG_RX|DBG_BUS, "(full region)");
1030 PRINTD (DBG_RX|DBG_BUS, "(start multi region)");
1031 dev->rx_bytes = rx_bytes - MAX_TRANSFER_COUNT;
1032 rx_bytes = MAX_TRANSFER_COUNT;
1037 // that's all folks - end of frame
1038 struct sk_buff * skb = dev->rx_skb;
1039 // dev->rx_iovec = 0;
1041 FLUSH_RX_CHANNEL (dev, dev->rx_channel);
1043 dump_skb ("<<<", dev->rx_channel, skb);
1045 PRINTD (DBG_RX|DBG_SKB, "push %p %u", skb->data, skb->len);
1048 struct atm_vcc * vcc = ATM_SKB(skb)->vcc;
1050 atomic_inc(&vcc->stats->rx);
1051 do_gettimeofday(&skb->stamp);
1052 // end of our responsability
1053 vcc->push (vcc, skb);
1058 // note: writing RX_COUNT clears any interrupt condition
1062 wr_regl (dev, MASTER_RX_COUNT_REG_OFF, 0);
1063 rds_regb (dev, DATA_PORT_OFF, dev->rx_addr, rx_bytes);
1065 wr_regl (dev, MASTER_RX_ADDR_REG_OFF, virt_to_bus (dev->rx_addr));
1066 wr_regl (dev, MASTER_RX_COUNT_REG_OFF, rx_bytes);
1068 dev->rx_addr += rx_bytes;
1071 wr_regl (dev, MASTER_RX_COUNT_REG_OFF, 0);
1072 // allow another RX thread to start
1074 clear_bit (rx_busy, &dev->flags);
1075 PRINTD (DBG_RX, "cleared rx_busy for dev %p", dev);
1078 #ifdef TAILRECURSIONWORKS
1079 // and we all bless optimised tail calls
1081 return rx_schedule (dev, 0);
1091 /********** handle RX bus master complete events **********/
1093 static inline void rx_bus_master_complete_handler (hrz_dev * dev) {
1094 if (test_bit (rx_busy, &dev->flags)) {
1095 rx_schedule (dev, 1);
1097 PRINTD (DBG_RX|DBG_ERR, "unexpected RX bus master completion");
1098 // clear interrupt condition on adapter
1099 wr_regl (dev, MASTER_RX_COUNT_REG_OFF, 0);
1104 /********** (queue to) become the next TX thread **********/
1106 static inline int tx_hold (hrz_dev * dev) {
1107 while (test_and_set_bit (tx_busy, &dev->flags)) {
1108 PRINTD (DBG_TX, "sleeping at tx lock %p %lu", dev, dev->flags);
1109 interruptible_sleep_on (&dev->tx_queue);
1110 PRINTD (DBG_TX, "woken at tx lock %p %lu", dev, dev->flags);
1111 if (signal_pending (current))
1114 PRINTD (DBG_TX, "set tx_busy for dev %p", dev);
1118 /********** allow another TX thread to start **********/
1120 static inline void tx_release (hrz_dev * dev) {
1121 clear_bit (tx_busy, &dev->flags);
1122 PRINTD (DBG_TX, "cleared tx_busy for dev %p", dev);
1123 wake_up_interruptible (&dev->tx_queue);
1126 /********** schedule TX transfers **********/
1128 static void tx_schedule (hrz_dev * const dev, int irq) {
1129 unsigned int tx_bytes;
1131 int append_desc = 0;
1133 int pio_instead = 0;
1134 #ifndef TAILRECURSIONWORKS
1136 while (pio_instead) {
1138 // bytes in current region waiting for TX transfer
1139 tx_bytes = dev->tx_bytes;
1143 while (rd_regl (dev, MASTER_TX_COUNT_REG_OFF)) {
1144 PRINTD (DBG_TX|DBG_WARN, "TX error: other PCI Bus Master TX still in progress!");
1145 if (++spin_count > 10) {
1146 PRINTD (DBG_TX|DBG_ERR, "spun out waiting PCI Bus Master TX completion");
1147 wr_regl (dev, MASTER_TX_COUNT_REG_OFF, 0);
1149 hrz_kfree_skb (dev->tx_skb);
1156 // start next transfer within same region
1157 if (!test_bit (ultra, &dev->flags) || tx_bytes <= MAX_PIO_COUNT) {
1158 PRINTD (DBG_TX|DBG_BUS, "(pio)");
1161 if (tx_bytes <= MAX_TRANSFER_COUNT) {
1162 PRINTD (DBG_TX|DBG_BUS, "(simple or last multi)");
1163 if (!dev->tx_iovec) {
1164 // end of last region
1169 PRINTD (DBG_TX|DBG_BUS, "(continuing multi)");
1170 dev->tx_bytes = tx_bytes - MAX_TRANSFER_COUNT;
1171 tx_bytes = MAX_TRANSFER_COUNT;
1174 // tx_bytes == 0 -- we're between regions
1175 // regions remaining to transfer
1176 unsigned int tx_regions = dev->tx_regions;
1179 // start a new region
1180 dev->tx_addr = dev->tx_iovec->iov_base;
1181 tx_bytes = dev->tx_iovec->iov_len;
1183 dev->tx_regions = tx_regions - 1;
1185 if (!test_bit (ultra, &dev->flags) || tx_bytes <= MAX_PIO_COUNT) {
1186 PRINTD (DBG_TX|DBG_BUS, "(pio)");
1189 if (tx_bytes <= MAX_TRANSFER_COUNT) {
1190 PRINTD (DBG_TX|DBG_BUS, "(full region)");
1193 PRINTD (DBG_TX|DBG_BUS, "(start multi region)");
1194 dev->tx_bytes = tx_bytes - MAX_TRANSFER_COUNT;
1195 tx_bytes = MAX_TRANSFER_COUNT;
1199 // that's all folks - end of frame
1200 struct sk_buff * skb = dev->tx_skb;
1204 atomic_inc(&ATM_SKB(skb)->vcc->stats->tx);
1207 hrz_kfree_skb (skb);
1211 // note: writing TX_COUNT clears any interrupt condition
1215 wr_regl (dev, MASTER_TX_COUNT_REG_OFF, 0);
1216 wrs_regb (dev, DATA_PORT_OFF, dev->tx_addr, tx_bytes);
1218 wr_regl (dev, TX_DESCRIPTOR_PORT_OFF, cpu_to_be32 (dev->tx_skb->len));
1220 wr_regl (dev, MASTER_TX_ADDR_REG_OFF, virt_to_bus (dev->tx_addr));
1222 wr_regl (dev, TX_DESCRIPTOR_REG_OFF, cpu_to_be32 (dev->tx_skb->len));
1223 wr_regl (dev, MASTER_TX_COUNT_REG_OFF,
1225 ? tx_bytes | MASTER_TX_AUTO_APPEND_DESC
1228 dev->tx_addr += tx_bytes;
1231 wr_regl (dev, MASTER_TX_COUNT_REG_OFF, 0);
1236 #ifdef TAILRECURSIONWORKS
1237 // and we all bless optimised tail calls
1239 return tx_schedule (dev, 0);
1249 /********** handle TX bus master complete events **********/
1251 static inline void tx_bus_master_complete_handler (hrz_dev * dev) {
1252 if (test_bit (tx_busy, &dev->flags)) {
1253 tx_schedule (dev, 1);
1255 PRINTD (DBG_TX|DBG_ERR, "unexpected TX bus master completion");
1256 // clear interrupt condition on adapter
1257 wr_regl (dev, MASTER_TX_COUNT_REG_OFF, 0);
1262 /********** move RX Q pointer to next item in circular buffer **********/
1264 // called only from IRQ sub-handler
1265 static inline u32 rx_queue_entry_next (hrz_dev * dev) {
1267 spin_lock (&dev->mem_lock);
1268 rx_queue_entry = rd_mem (dev, &dev->rx_q_entry->entry);
1269 if (dev->rx_q_entry == dev->rx_q_wrap)
1270 dev->rx_q_entry = dev->rx_q_reset;
1273 wr_regw (dev, RX_QUEUE_RD_PTR_OFF, dev->rx_q_entry - dev->rx_q_reset);
1274 spin_unlock (&dev->mem_lock);
1275 return rx_queue_entry;
1278 /********** handle RX disabled by device **********/
1280 static inline void rx_disabled_handler (hrz_dev * dev) {
1281 wr_regw (dev, RX_CONFIG_OFF, rd_regw (dev, RX_CONFIG_OFF) | RX_ENABLE);
1283 PRINTK (KERN_WARNING, "RX was disabled!");
1286 /********** handle RX data received by device **********/
1288 // called from IRQ handler
1289 static inline void rx_data_av_handler (hrz_dev * dev) {
1291 u32 rx_queue_entry_flags;
1295 PRINTD (DBG_FLOW, "hrz_data_av_handler");
1297 // try to grab rx lock (not possible during RX bus mastering)
1298 if (test_and_set_bit (rx_busy, &dev->flags)) {
1299 PRINTD (DBG_RX, "locked out of rx lock");
1302 PRINTD (DBG_RX, "set rx_busy for dev %p", dev);
1303 // lock is cleared if we fail now, o/w after bus master completion
1305 YELLOW_LED_OFF(dev);
1307 rx_queue_entry = rx_queue_entry_next (dev);
1309 rx_len = rx_q_entry_to_length (rx_queue_entry);
1310 rx_channel = rx_q_entry_to_rx_channel (rx_queue_entry);
1312 WAIT_FLUSH_RX_COMPLETE (dev);
1314 SELECT_RX_CHANNEL (dev, rx_channel);
1316 PRINTD (DBG_RX, "rx_queue_entry is: %#x", rx_queue_entry);
1317 rx_queue_entry_flags = rx_queue_entry & (RX_CRC_32_OK|RX_COMPLETE_FRAME|SIMONS_DODGEY_MARKER);
1320 // (at least) bus-mastering breaks if we try to handle a
1321 // zero-length frame, besides AAL5 does not support them
1322 PRINTK (KERN_ERR, "zero-length frame!");
1323 rx_queue_entry_flags &= ~RX_COMPLETE_FRAME;
1326 if (rx_queue_entry_flags & SIMONS_DODGEY_MARKER) {
1327 PRINTD (DBG_RX|DBG_ERR, "Simon's marker detected!");
1329 if (rx_queue_entry_flags == (RX_CRC_32_OK | RX_COMPLETE_FRAME)) {
1330 struct atm_vcc * atm_vcc;
1332 PRINTD (DBG_RX, "got a frame on rx_channel %x len %u", rx_channel, rx_len);
1334 atm_vcc = dev->rxer[rx_channel];
1335 // if no vcc is assigned to this channel, we should drop the frame
1336 // (is this what SIMONS etc. was trying to achieve?)
1340 if (atm_vcc->qos.rxtp.traffic_class != ATM_NONE) {
1342 if (rx_len <= atm_vcc->qos.rxtp.max_sdu) {
1344 struct sk_buff * skb = atm_alloc_charge (atm_vcc, rx_len, GFP_ATOMIC);
1346 // remember this so we can push it later
1348 // remember this so we can flush it later
1349 dev->rx_channel = rx_channel;
1351 // prepare socket buffer
1352 skb_put (skb, rx_len);
1353 ATM_SKB(skb)->vcc = atm_vcc;
1356 // dev->rx_regions = 0;
1357 // dev->rx_iovec = 0;
1358 dev->rx_bytes = rx_len;
1359 dev->rx_addr = skb->data;
1360 PRINTD (DBG_RX, "RX start simple transfer (addr %p, len %d)",
1364 rx_schedule (dev, 0);
1368 PRINTD (DBG_SKB|DBG_WARN, "failed to get skb");
1372 PRINTK (KERN_INFO, "frame received on TX-only VC %x", rx_channel);
1373 // do we count this?
1377 PRINTK (KERN_WARNING, "dropped over-size frame");
1378 // do we count this?
1382 PRINTD (DBG_WARN|DBG_VCC|DBG_RX, "no VCC for this frame (VC closed)");
1383 // do we count this?
1387 // Wait update complete ? SPONG
1393 FLUSH_RX_CHANNEL (dev,rx_channel);
1394 clear_bit (rx_busy, &dev->flags);
1399 /********** interrupt handler **********/
1401 static irqreturn_t interrupt_handler(int irq, void *dev_id,
1402 struct pt_regs *pt_regs) {
1403 hrz_dev * dev = hrz_devs;
1405 unsigned int irq_ok;
1408 PRINTD (DBG_FLOW, "interrupt_handler: %p", dev_id);
1411 PRINTD (DBG_IRQ|DBG_ERR, "irq with NULL dev_id: %d", irq);
1414 // Did one of our cards generate the interrupt?
1421 PRINTD (DBG_IRQ, "irq not for me: %d", irq);
1424 if (irq != dev->irq) {
1425 PRINTD (DBG_IRQ|DBG_ERR, "irq mismatch: %d", irq);
1429 // definitely for us
1431 while ((int_source = rd_regl (dev, INT_SOURCE_REG_OFF)
1432 & INTERESTING_INTERRUPTS)) {
1433 // In the interests of fairness, the (inline) handlers below are
1434 // called in sequence and without immediate return to the head of
1435 // the while loop. This is only of issue for slow hosts (or when
1436 // debugging messages are on). Really slow hosts may find a fast
1437 // sender keeps them permanently in the IRQ handler. :(
1439 // (only an issue for slow hosts) RX completion goes before
1440 // rx_data_av as the former implies rx_busy and so the latter
1441 // would just abort. If it reschedules another transfer
1442 // (continuing the same frame) then it will not clear rx_busy.
1444 // (only an issue for slow hosts) TX completion goes before RX
1445 // data available as it is a much shorter routine - there is the
1446 // chance that any further transfers it schedules will be complete
1447 // by the time of the return to the head of the while loop
1449 if (int_source & RX_BUS_MASTER_COMPLETE) {
1451 PRINTD (DBG_IRQ|DBG_BUS|DBG_RX, "rx_bus_master_complete asserted");
1452 rx_bus_master_complete_handler (dev);
1454 if (int_source & TX_BUS_MASTER_COMPLETE) {
1456 PRINTD (DBG_IRQ|DBG_BUS|DBG_TX, "tx_bus_master_complete asserted");
1457 tx_bus_master_complete_handler (dev);
1459 if (int_source & RX_DATA_AV) {
1461 PRINTD (DBG_IRQ|DBG_RX, "rx_data_av asserted");
1462 rx_data_av_handler (dev);
1466 PRINTD (DBG_IRQ, "work done: %u", irq_ok);
1468 PRINTD (DBG_IRQ|DBG_WARN, "spurious interrupt source: %#x", int_source);
1471 PRINTD (DBG_IRQ|DBG_FLOW, "interrupt_handler done: %p", dev_id);
1477 /********** housekeeping **********/
1479 static void set_timer (struct timer_list * timer, unsigned int delay) {
1480 timer->expires = jiffies + delay;
1485 static void do_housekeeping (unsigned long arg) {
1486 // just stats at the moment
1487 hrz_dev * dev = hrz_devs;
1489 // data is set to zero at module unload
1490 if (housekeeping.data) {
1492 // collect device-specific (not driver/atm-linux) stats here
1493 dev->tx_cell_count += rd_regw (dev, TX_CELL_COUNT_OFF);
1494 dev->rx_cell_count += rd_regw (dev, RX_CELL_COUNT_OFF);
1495 dev->hec_error_count += rd_regw (dev, HEC_ERROR_COUNT_OFF);
1496 dev->unassigned_cell_count += rd_regw (dev, UNASSIGNED_CELL_COUNT_OFF);
1499 set_timer (&housekeeping, HZ/10);
1504 /********** find an idle channel for TX and set it up **********/
1506 // called with tx_busy set
1507 static inline short setup_idle_tx_channel (hrz_dev * dev, hrz_vcc * vcc) {
1508 unsigned short idle_channels;
1509 short tx_channel = -1;
1510 unsigned int spin_count;
1511 PRINTD (DBG_FLOW|DBG_TX, "setup_idle_tx_channel %p", dev);
1513 // better would be to fail immediately, the caller can then decide whether
1514 // to wait or drop (depending on whether this is UBR etc.)
1516 while (!(idle_channels = rd_regw (dev, TX_STATUS_OFF) & IDLE_CHANNELS_MASK)) {
1517 PRINTD (DBG_TX|DBG_WARN, "waiting for idle TX channel");
1519 if (++spin_count > 100) {
1520 PRINTD (DBG_TX|DBG_ERR, "spun out waiting for idle TX channel");
1525 // got an idle channel
1527 // tx_idle ensures we look for idle channels in RR order
1528 int chan = dev->tx_idle;
1531 while (keep_going) {
1532 if (idle_channels & (1<<chan)) {
1537 if (chan == TX_CHANS)
1541 dev->tx_idle = chan;
1544 // set up the channel we found
1546 // Initialise the cell header in the transmit channel descriptor
1547 // a.k.a. prepare the channel and remember that we have done so.
1549 tx_ch_desc * tx_desc = &memmap->tx_descs[tx_channel];
1552 u16 channel = vcc->channel;
1554 unsigned long flags;
1555 spin_lock_irqsave (&dev->mem_lock, flags);
1557 // Update the transmit channel record.
1558 dev->tx_channel_record[tx_channel] = channel;
1561 update_tx_channel_config (dev, tx_channel, RATE_TYPE_ACCESS,
1564 // Update the PCR counter preload value etc.
1565 update_tx_channel_config (dev, tx_channel, PCR_TIMER_ACCESS,
1569 if (vcc->tx_xbr_bits == VBR_RATE_TYPE) {
1571 update_tx_channel_config (dev, tx_channel, SCR_TIMER_ACCESS,
1575 update_tx_channel_config (dev, tx_channel, BUCKET_CAPACITY_ACCESS,
1576 vcc->tx_bucket_bits);
1579 update_tx_channel_config (dev, tx_channel, BUCKET_FULLNESS_ACCESS,
1580 vcc->tx_bucket_bits);
1584 // Initialise the read and write buffer pointers
1585 rd_ptr = rd_mem (dev, &tx_desc->rd_buf_type) & BUFFER_PTR_MASK;
1586 wr_ptr = rd_mem (dev, &tx_desc->wr_buf_type) & BUFFER_PTR_MASK;
1588 // idle TX channels should have identical pointers
1589 if (rd_ptr != wr_ptr) {
1590 PRINTD (DBG_TX|DBG_ERR, "TX buffer pointers are broken!");
1591 // spin_unlock... return -E...
1592 // I wonder if gcc would get rid of one of the pointer aliases
1594 PRINTD (DBG_TX, "TX buffer pointers are: rd %x, wr %x.",
1599 PRINTD (DBG_QOS|DBG_TX, "tx_channel: aal0");
1600 rd_ptr |= CHANNEL_TYPE_RAW_CELLS;
1601 wr_ptr |= CHANNEL_TYPE_RAW_CELLS;
1604 PRINTD (DBG_QOS|DBG_TX, "tx_channel: aal34");
1605 rd_ptr |= CHANNEL_TYPE_AAL3_4;
1606 wr_ptr |= CHANNEL_TYPE_AAL3_4;
1609 rd_ptr |= CHANNEL_TYPE_AAL5;
1610 wr_ptr |= CHANNEL_TYPE_AAL5;
1611 // Initialise the CRC
1612 wr_mem (dev, &tx_desc->partial_crc, INITIAL_CRC);
1616 wr_mem (dev, &tx_desc->rd_buf_type, rd_ptr);
1617 wr_mem (dev, &tx_desc->wr_buf_type, wr_ptr);
1619 // Write the Cell Header
1620 // Payload Type, CLP and GFC would go here if non-zero
1621 wr_mem (dev, &tx_desc->cell_header, channel);
1623 spin_unlock_irqrestore (&dev->mem_lock, flags);
1629 /********** send a frame **********/
1631 static int hrz_send (struct atm_vcc * atm_vcc, struct sk_buff * skb) {
1632 unsigned int spin_count;
1634 hrz_dev * dev = HRZ_DEV(atm_vcc->dev);
1635 hrz_vcc * vcc = HRZ_VCC(atm_vcc);
1636 u16 channel = vcc->channel;
1638 u32 buffers_required;
1640 /* signed for error return */
1643 PRINTD (DBG_FLOW|DBG_TX, "hrz_send vc %x data %p len %u",
1644 channel, skb->data, skb->len);
1646 dump_skb (">>>", channel, skb);
1648 if (atm_vcc->qos.txtp.traffic_class == ATM_NONE) {
1649 PRINTK (KERN_ERR, "attempt to send on RX-only VC %x", channel);
1650 hrz_kfree_skb (skb);
1654 // don't understand this
1655 ATM_SKB(skb)->vcc = atm_vcc;
1657 if (skb->len > atm_vcc->qos.txtp.max_sdu) {
1658 PRINTK (KERN_ERR, "sk_buff length greater than agreed max_sdu, dropping...");
1659 hrz_kfree_skb (skb);
1664 PRINTD (DBG_ERR|DBG_TX, "attempt to transmit on zero (rx_)channel");
1665 hrz_kfree_skb (skb);
1671 // where would be a better place for this? housekeeping?
1673 pci_read_config_word (dev->pci_dev, PCI_STATUS, &status);
1674 if (status & PCI_STATUS_REC_MASTER_ABORT) {
1675 PRINTD (DBG_BUS|DBG_ERR, "Clearing PCI Master Abort (and cleaning up)");
1676 status &= ~PCI_STATUS_REC_MASTER_ABORT;
1677 pci_write_config_word (dev->pci_dev, PCI_STATUS, status);
1678 if (test_bit (tx_busy, &dev->flags)) {
1679 hrz_kfree_skb (dev->tx_skb);
1686 #ifdef DEBUG_HORIZON
1688 if (channel == 1023) {
1690 unsigned short d = 0;
1691 char * s = skb->data;
1693 for (i = 0; i < 4; ++i) {
1694 d = (d<<4) | ((*s <= '9') ? (*s - '0') : (*s - 'a' + 10));
1697 PRINTK (KERN_INFO, "debug bitmap is now %hx", debug = d);
1702 // wait until TX is free and grab lock
1703 if (tx_hold (dev)) {
1704 hrz_kfree_skb (skb);
1705 return -ERESTARTSYS;
1708 // Wait for enough space to be available in transmit buffer memory.
1710 // should be number of cells needed + 2 (according to hardware docs)
1711 // = ((framelen+8)+47) / 48 + 2
1712 // = (framelen+7) / 48 + 3, hmm... faster to put addition inside XXX
1713 buffers_required = (skb->len+(ATM_AAL5_TRAILER-1)) / ATM_CELL_PAYLOAD + 3;
1715 // replace with timer and sleep, add dev->tx_buffers_queue (max 1 entry)
1717 while ((free_buffers = rd_regw (dev, TX_FREE_BUFFER_COUNT_OFF)) < buffers_required) {
1718 PRINTD (DBG_TX, "waiting for free TX buffers, got %d of %d",
1719 free_buffers, buffers_required);
1720 // what is the appropriate delay? implement a timeout? (depending on line speed?)
1722 // what happens if we kill (current_pid, SIGKILL) ?
1724 if (++spin_count > 1000) {
1725 PRINTD (DBG_TX|DBG_ERR, "spun out waiting for tx buffers, got %d of %d",
1726 free_buffers, buffers_required);
1728 hrz_kfree_skb (skb);
1729 return -ERESTARTSYS;
1733 // Select a channel to transmit the frame on.
1734 if (channel == dev->last_vc) {
1735 PRINTD (DBG_TX, "last vc hack: hit");
1736 tx_channel = dev->tx_last;
1738 PRINTD (DBG_TX, "last vc hack: miss");
1739 // Are we currently transmitting this VC on one of the channels?
1740 for (tx_channel = 0; tx_channel < TX_CHANS; ++tx_channel)
1741 if (dev->tx_channel_record[tx_channel] == channel) {
1742 PRINTD (DBG_TX, "vc already on channel: hit");
1745 if (tx_channel == TX_CHANS) {
1746 PRINTD (DBG_TX, "vc already on channel: miss");
1747 // Find and set up an idle channel.
1748 tx_channel = setup_idle_tx_channel (dev, vcc);
1749 if (tx_channel < 0) {
1750 PRINTD (DBG_TX|DBG_ERR, "failed to get channel");
1756 PRINTD (DBG_TX, "got channel");
1757 SELECT_TX_CHANNEL(dev, tx_channel);
1759 dev->last_vc = channel;
1760 dev->tx_last = tx_channel;
1763 PRINTD (DBG_TX, "using channel %u", tx_channel);
1765 YELLOW_LED_OFF(dev);
1767 // TX start transfer
1770 unsigned int tx_len = skb->len;
1771 unsigned int tx_iovcnt = skb_shinfo(skb)->nr_frags;
1772 // remember this so we can free it later
1776 // scatter gather transfer
1777 dev->tx_regions = tx_iovcnt;
1778 dev->tx_iovec = 0; /* @@@ needs rewritten */
1780 PRINTD (DBG_TX|DBG_BUS, "TX start scatter-gather transfer (iovec %p, len %d)",
1783 hrz_kfree_skb (skb);
1787 dev->tx_regions = 0;
1789 dev->tx_bytes = tx_len;
1790 dev->tx_addr = skb->data;
1791 PRINTD (DBG_TX|DBG_BUS, "TX start simple transfer (addr %p, len %d)",
1795 // and do the business
1796 tx_schedule (dev, 0);
1803 /********** reset a card **********/
1805 static void hrz_reset (const hrz_dev * dev) {
1806 u32 control_0_reg = rd_regl (dev, CONTROL_0_REG);
1808 // why not set RESET_HORIZON to one and wait for the card to
1809 // reassert that bit as zero? Like so:
1810 control_0_reg = control_0_reg & RESET_HORIZON;
1811 wr_regl (dev, CONTROL_0_REG, control_0_reg);
1812 while (control_0_reg & RESET_HORIZON)
1813 control_0_reg = rd_regl (dev, CONTROL_0_REG);
1815 // old reset code retained:
1816 wr_regl (dev, CONTROL_0_REG, control_0_reg |
1817 RESET_ATM | RESET_RX | RESET_TX | RESET_HOST);
1818 // just guessing here
1821 wr_regl (dev, CONTROL_0_REG, control_0_reg);
1824 /********** read the burnt in address **********/
1826 static u16 __init read_bia (const hrz_dev * dev, u16 addr) {
1828 u32 ctrl = rd_regl (dev, CONTROL_0_REG);
1830 void WRITE_IT_WAIT (void) {
1831 wr_regl (dev, CONTROL_0_REG, ctrl);
1835 void CLOCK_IT (void) {
1836 // DI must be valid around rising SK edge
1837 ctrl &= ~SEEPROM_SK;
1843 const unsigned int addr_bits = 6;
1844 const unsigned int data_bits = 16;
1850 ctrl &= ~(SEEPROM_CS | SEEPROM_SK | SEEPROM_DI);
1853 // wake Serial EEPROM and send 110 (READ) command
1854 ctrl |= (SEEPROM_CS | SEEPROM_DI);
1860 ctrl &= ~SEEPROM_DI;
1863 for (i=0; i<addr_bits; i++) {
1864 if (addr & (1 << (addr_bits-1)))
1867 ctrl &= ~SEEPROM_DI;
1874 // we could check that we have DO = 0 here
1875 ctrl &= ~SEEPROM_DI;
1878 for (i=0;i<data_bits;i++) {
1883 if (rd_regl (dev, CONTROL_0_REG) & SEEPROM_DO)
1884 res |= (1 << (data_bits-1));
1887 ctrl &= ~(SEEPROM_SK | SEEPROM_CS);
1893 /********** initialise a card **********/
1895 static int __init hrz_init (hrz_dev * dev) {
1909 ctrl = rd_regl (dev, CONTROL_0_REG);
1910 PRINTD (DBG_INFO, "ctrl0reg is %#x", ctrl);
1911 onefivefive = ctrl & ATM_LAYER_STATUS;
1914 printk (DEV_LABEL ": Horizon Ultra (at 155.52 MBps)");
1916 printk (DEV_LABEL ": Horizon (at 25 MBps)");
1919 // Reset the card to get everything in a known state
1924 // Clear all the buffer memory
1926 printk (" clearing memory");
1928 for (mem = (HDW *) memmap; mem < (HDW *) (memmap + 1); ++mem)
1929 wr_mem (dev, mem, 0);
1931 printk (" tx channels");
1933 // All transmit eight channels are set up as AAL5 ABR channels with
1934 // a 16us cell spacing. Why?
1936 // Channel 0 gets the free buffer at 100h, channel 1 gets the free
1937 // buffer at 110h etc.
1939 for (chan = 0; chan < TX_CHANS; ++chan) {
1940 tx_ch_desc * tx_desc = &memmap->tx_descs[chan];
1941 cell_buf * buf = &memmap->inittxbufs[chan];
1943 // initialise the read and write buffer pointers
1944 wr_mem (dev, &tx_desc->rd_buf_type, BUF_PTR(buf));
1945 wr_mem (dev, &tx_desc->wr_buf_type, BUF_PTR(buf));
1947 // set the status of the initial buffers to empty
1948 wr_mem (dev, &buf->next, BUFF_STATUS_EMPTY);
1951 // Use space bufn3 at the moment for tx buffers
1953 printk (" tx buffers");
1955 tx_desc = memmap->bufn3;
1957 wr_mem (dev, &memmap->txfreebufstart.next, BUF_PTR(tx_desc) | BUFF_STATUS_EMPTY);
1959 for (buff_count = 0; buff_count < BUFN3_SIZE-1; buff_count++) {
1960 wr_mem (dev, &tx_desc->next, BUF_PTR(tx_desc+1) | BUFF_STATUS_EMPTY);
1964 wr_mem (dev, &tx_desc->next, BUF_PTR(&memmap->txfreebufend) | BUFF_STATUS_EMPTY);
1966 // Initialise the transmit free buffer count
1967 wr_regw (dev, TX_FREE_BUFFER_COUNT_OFF, BUFN3_SIZE);
1969 printk (" rx channels");
1971 // Initialise all of the receive channels to be AAL5 disabled with
1972 // an interrupt threshold of 0
1974 for (chan = 0; chan < RX_CHANS; ++chan) {
1975 rx_ch_desc * rx_desc = &memmap->rx_descs[chan];
1977 wr_mem (dev, &rx_desc->wr_buf_type, CHANNEL_TYPE_AAL5 | RX_CHANNEL_DISABLED);
1980 printk (" rx buffers");
1982 // Use space bufn4 at the moment for rx buffers
1984 rx_desc = memmap->bufn4;
1986 wr_mem (dev, &memmap->rxfreebufstart.next, BUF_PTR(rx_desc) | BUFF_STATUS_EMPTY);
1988 for (buff_count = 0; buff_count < BUFN4_SIZE-1; buff_count++) {
1989 wr_mem (dev, &rx_desc->next, BUF_PTR(rx_desc+1) | BUFF_STATUS_EMPTY);
1994 wr_mem (dev, &rx_desc->next, BUF_PTR(&memmap->rxfreebufend) | BUFF_STATUS_EMPTY);
1996 // Initialise the receive free buffer count
1997 wr_regw (dev, RX_FREE_BUFFER_COUNT_OFF, BUFN4_SIZE);
1999 // Initialize Horizons registers
2002 wr_regw (dev, TX_CONFIG_OFF,
2003 ABR_ROUND_ROBIN | TX_NORMAL_OPERATION | DRVR_DRVRBAR_ENABLE);
2005 // RX config. Use 10-x VC bits, x VP bits, non user cells in channel 0.
2006 wr_regw (dev, RX_CONFIG_OFF,
2007 DISCARD_UNUSED_VPI_VCI_BITS_SET | NON_USER_CELLS_IN_ONE_CHANNEL | vpi_bits);
2010 wr_regw (dev, RX_LINE_CONFIG_OFF,
2011 LOCK_DETECT_ENABLE | FREQUENCY_DETECT_ENABLE | GXTALOUT_SELECT_DIV4);
2013 // Set the max AAL5 cell count to be just enough to contain the
2014 // largest AAL5 frame that the user wants to receive
2015 wr_regw (dev, MAX_AAL5_CELL_COUNT_OFF,
2016 (max_rx_size + ATM_AAL5_TRAILER + ATM_CELL_PAYLOAD - 1) / ATM_CELL_PAYLOAD);
2019 wr_regw (dev, RX_CONFIG_OFF, rd_regw (dev, RX_CONFIG_OFF) | RX_ENABLE);
2021 printk (" control");
2023 // Drive the OE of the LEDs then turn the green LED on
2024 ctrl |= GREEN_LED_OE | YELLOW_LED_OE | GREEN_LED | YELLOW_LED;
2025 wr_regl (dev, CONTROL_0_REG, ctrl);
2027 // Test for a 155-capable card
2030 // Select 155 mode... make this a choice (or: how do we detect
2031 // external line speed and switch?)
2032 ctrl |= ATM_LAYER_SELECT;
2033 wr_regl (dev, CONTROL_0_REG, ctrl);
2035 // test SUNI-lite vs SAMBA
2037 // Register 0x00 in the SUNI will have some of bits 3-7 set, and
2038 // they will always be zero for the SAMBA. Ha! Bloody hardware
2039 // engineers. It'll never work.
2041 if (rd_framer (dev, 0) & 0x00f0) {
2045 // Reset, just in case
2046 wr_framer (dev, 0x00, 0x0080);
2047 wr_framer (dev, 0x00, 0x0000);
2049 // Configure transmit FIFO
2050 wr_framer (dev, 0x63, rd_framer (dev, 0x63) | 0x0002);
2052 // Set line timed mode
2053 wr_framer (dev, 0x05, rd_framer (dev, 0x05) | 0x0001);
2058 // Reset, just in case
2059 wr_framer (dev, 0, rd_framer (dev, 0) | 0x0001);
2060 wr_framer (dev, 0, rd_framer (dev, 0) &~ 0x0001);
2062 // Turn off diagnostic loopback and enable line-timed mode
2063 wr_framer (dev, 0, 0x0002);
2065 // Turn on transmit outputs
2066 wr_framer (dev, 2, 0x0B80);
2070 ctrl &= ~ATM_LAYER_SELECT;
2086 u8 * esi = dev->atm_dev->esi;
2088 // in the card I have, EEPROM
2089 // addresses 0, 1, 2 contain 0
2090 // addresess 5, 6 etc. contain ffff
2091 // NB: Madge prefix is 00 00 f6 (which is 00 00 6f in Ethernet bit order)
2092 // the read_bia routine gets the BIA in Ethernet bit order
2094 for (i=0; i < ESI_LEN; ++i) {
2096 b = read_bia (dev, i/2 + 2);
2100 printk ("%02x", esi[i]);
2104 // Enable RX_Q and ?X_COMPLETE interrupts only
2105 wr_regl (dev, INT_ENABLE_REG_OFF, INTERESTING_INTERRUPTS);
2113 /********** check max_sdu **********/
2115 static int check_max_sdu (hrz_aal aal, struct atm_trafprm * tp, unsigned int max_frame_size) {
2116 PRINTD (DBG_FLOW|DBG_QOS, "check_max_sdu");
2120 if (!(tp->max_sdu)) {
2121 PRINTD (DBG_QOS, "defaulting max_sdu");
2122 tp->max_sdu = ATM_AAL0_SDU;
2123 } else if (tp->max_sdu != ATM_AAL0_SDU) {
2124 PRINTD (DBG_QOS|DBG_ERR, "rejecting max_sdu");
2129 if (tp->max_sdu == 0 || tp->max_sdu > ATM_MAX_AAL34_PDU) {
2130 PRINTD (DBG_QOS, "%sing max_sdu", tp->max_sdu ? "capp" : "default");
2131 tp->max_sdu = ATM_MAX_AAL34_PDU;
2135 if (tp->max_sdu == 0 || tp->max_sdu > max_frame_size) {
2136 PRINTD (DBG_QOS, "%sing max_sdu", tp->max_sdu ? "capp" : "default");
2137 tp->max_sdu = max_frame_size;
2144 /********** check pcr **********/
2146 // something like this should be part of ATM Linux
2147 static int atm_pcr_check (struct atm_trafprm * tp, unsigned int pcr) {
2148 // we are assuming non-UBR, and non-special values of pcr
2149 if (tp->min_pcr == ATM_MAX_PCR)
2150 PRINTD (DBG_QOS, "luser gave min_pcr = ATM_MAX_PCR");
2151 else if (tp->min_pcr < 0)
2152 PRINTD (DBG_QOS, "luser gave negative min_pcr");
2153 else if (tp->min_pcr && tp->min_pcr > pcr)
2154 PRINTD (DBG_QOS, "pcr less than min_pcr");
2156 // !! max_pcr = UNSPEC (0) is equivalent to max_pcr = MAX (-1)
2157 // easier to #define ATM_MAX_PCR 0 and have all rates unsigned?
2158 // [this would get rid of next two conditionals]
2159 if ((0) && tp->max_pcr == ATM_MAX_PCR)
2160 PRINTD (DBG_QOS, "luser gave max_pcr = ATM_MAX_PCR");
2161 else if ((tp->max_pcr != ATM_MAX_PCR) && tp->max_pcr < 0)
2162 PRINTD (DBG_QOS, "luser gave negative max_pcr");
2163 else if (tp->max_pcr && tp->max_pcr != ATM_MAX_PCR && tp->max_pcr < pcr)
2164 PRINTD (DBG_QOS, "pcr greater than max_pcr");
2166 // each limit unspecified or not violated
2167 PRINTD (DBG_QOS, "xBR(pcr) OK");
2170 PRINTD (DBG_QOS, "pcr=%u, tp: min_pcr=%d, pcr=%d, max_pcr=%d",
2171 pcr, tp->min_pcr, tp->pcr, tp->max_pcr);
2175 /********** open VC **********/
2177 static int hrz_open (struct atm_vcc *atm_vcc)
2182 struct atm_qos * qos;
2183 struct atm_trafprm * txtp;
2184 struct atm_trafprm * rxtp;
2186 hrz_dev * dev = HRZ_DEV(atm_vcc->dev);
2188 hrz_vcc * vccp; // allocated late
2189 short vpi = atm_vcc->vpi;
2190 int vci = atm_vcc->vci;
2191 PRINTD (DBG_FLOW|DBG_VCC, "hrz_open %x %x", vpi, vci);
2193 #ifdef ATM_VPI_UNSPEC
2194 // UNSPEC is deprecated, remove this code eventually
2195 if (vpi == ATM_VPI_UNSPEC || vci == ATM_VCI_UNSPEC) {
2196 PRINTK (KERN_WARNING, "rejecting open with unspecified VPI/VCI (deprecated)");
2201 error = vpivci_to_channel (&channel, vpi, vci);
2203 PRINTD (DBG_WARN|DBG_VCC, "VPI/VCI out of range: %hd/%d", vpi, vci);
2207 vcc.channel = channel;
2208 // max speed for the moment
2211 qos = &atm_vcc->qos;
2213 // check AAL and remember it
2216 // we would if it were 48 bytes and not 52!
2217 PRINTD (DBG_QOS|DBG_VCC, "AAL0");
2221 // we would if I knew how do the SAR!
2222 PRINTD (DBG_QOS|DBG_VCC, "AAL3/4");
2226 PRINTD (DBG_QOS|DBG_VCC, "AAL5");
2230 PRINTD (DBG_QOS|DBG_VCC, "Bad AAL!");
2235 // TX traffic parameters
2237 // there are two, interrelated problems here: 1. the reservation of
2238 // PCR is not a binary choice, we are given bounds and/or a
2239 // desirable value; 2. the device is only capable of certain values,
2240 // most of which are not integers. It is almost certainly acceptable
2241 // to be off by a maximum of 1 to 10 cps.
2243 // Pragmatic choice: always store an integral PCR as that which has
2244 // been allocated, even if we allocate a little (or a lot) less,
2245 // after rounding. The actual allocation depends on what we can
2246 // manage with our rate selection algorithm. The rate selection
2247 // algorithm is given an integral PCR and a tolerance and told
2248 // whether it should round the value up or down if the tolerance is
2249 // exceeded; it returns: a) the actual rate selected (rounded up to
2250 // the nearest integer), b) a bit pattern to feed to the timer
2251 // register, and c) a failure value if no applicable rate exists.
2253 // Part of the job is done by atm_pcr_goal which gives us a PCR
2254 // specification which says: EITHER grab the maximum available PCR
2255 // (and perhaps a lower bound which we musn't pass), OR grab this
2256 // amount, rounding down if you have to (and perhaps a lower bound
2257 // which we musn't pass) OR grab this amount, rounding up if you
2258 // have to (and perhaps an upper bound which we musn't pass). If any
2259 // bounds ARE passed we fail. Note that rounding is only rounding to
2260 // match device limitations, we do not round down to satisfy
2261 // bandwidth availability even if this would not violate any given
2264 // Note: telephony = 64kb/s = 48 byte cell payload @ 500/3 cells/s
2265 // (say) so this is not even a binary fixpoint cell rate (but this
2266 // device can do it). To avoid this sort of hassle we use a
2267 // tolerance parameter (currently fixed at 10 cps).
2269 PRINTD (DBG_QOS, "TX:");
2273 // set up defaults for no traffic
2275 // who knows what would actually happen if you try and send on this?
2276 vcc.tx_xbr_bits = IDLE_RATE_TYPE;
2277 vcc.tx_pcr_bits = CLOCK_DISABLE;
2279 vcc.tx_scr_bits = CLOCK_DISABLE;
2280 vcc.tx_bucket_bits = 0;
2283 if (txtp->traffic_class != ATM_NONE) {
2284 error = check_max_sdu (vcc.aal, txtp, max_tx_size);
2286 PRINTD (DBG_QOS, "TX max_sdu check failed");
2290 switch (txtp->traffic_class) {
2292 // we take "the PCR" as a rate-cap
2295 make_rate (dev, 1<<30, round_nearest, &vcc.tx_pcr_bits, 0);
2296 vcc.tx_xbr_bits = ABR_RATE_TYPE;
2301 // reserve min, allow up to max
2302 vcc.tx_rate = 0; // ?
2303 make_rate (dev, 1<<30, round_nearest, &vcc.tx_pcr_bits, 0);
2304 vcc.tx_xbr_bits = ABR_RATE_TYPE;
2309 int pcr = atm_pcr_goal (txtp);
2312 // down vs. up, remaining bandwidth vs. unlimited bandwidth!!
2313 // should really have: once someone gets unlimited bandwidth
2314 // that no more non-UBR channels can be opened until the
2315 // unlimited one closes?? For the moment, round_down means
2316 // greedy people actually get something and not nothing
2318 // slight race (no locking) here so we may get -EAGAIN
2319 // later; the greedy bastards would deserve it :)
2320 PRINTD (DBG_QOS, "snatching all remaining TX bandwidth");
2321 pcr = dev->tx_avail;
2322 } else if (pcr < 0) {
2328 error = make_rate_with_tolerance (dev, pcr, r, 10,
2329 &vcc.tx_pcr_bits, &vcc.tx_rate);
2331 PRINTD (DBG_QOS, "could not make rate from TX PCR");
2334 // not really clear what further checking is needed
2335 error = atm_pcr_check (txtp, vcc.tx_rate);
2337 PRINTD (DBG_QOS, "TX PCR failed consistency check");
2340 vcc.tx_xbr_bits = CBR_RATE_TYPE;
2345 int pcr = atm_pcr_goal (txtp);
2346 // int scr = atm_scr_goal (txtp);
2347 int scr = pcr/2; // just for fun
2348 unsigned int mbs = 60; // just for fun
2351 unsigned int bucket;
2355 } else if (pcr < 0) {
2361 error = make_rate_with_tolerance (dev, pcr, pr, 10,
2362 &vcc.tx_pcr_bits, 0);
2364 // see comments for PCR with CBR above
2366 // slight race (no locking) here so we may get -EAGAIN
2367 // later; the greedy bastards would deserve it :)
2368 PRINTD (DBG_QOS, "snatching all remaining TX bandwidth");
2369 scr = dev->tx_avail;
2370 } else if (scr < 0) {
2376 error = make_rate_with_tolerance (dev, scr, sr, 10,
2377 &vcc.tx_scr_bits, &vcc.tx_rate);
2379 PRINTD (DBG_QOS, "could not make rate from TX SCR");
2382 // not really clear what further checking is needed
2383 // error = atm_scr_check (txtp, vcc.tx_rate);
2385 PRINTD (DBG_QOS, "TX SCR failed consistency check");
2388 // bucket calculations (from a piece of paper...) cell bucket
2389 // capacity must be largest integer smaller than m(p-s)/p + 1
2390 // where m = max burst size, p = pcr, s = scr
2391 bucket = mbs*(pcr-scr)/pcr;
2392 if (bucket*pcr != mbs*(pcr-scr))
2394 if (bucket > BUCKET_MAX_SIZE) {
2395 PRINTD (DBG_QOS, "shrinking bucket from %u to %u",
2396 bucket, BUCKET_MAX_SIZE);
2397 bucket = BUCKET_MAX_SIZE;
2399 vcc.tx_xbr_bits = VBR_RATE_TYPE;
2400 vcc.tx_bucket_bits = bucket;
2405 PRINTD (DBG_QOS, "unsupported TX traffic class");
2412 // RX traffic parameters
2414 PRINTD (DBG_QOS, "RX:");
2418 // set up defaults for no traffic
2421 if (rxtp->traffic_class != ATM_NONE) {
2422 error = check_max_sdu (vcc.aal, rxtp, max_rx_size);
2424 PRINTD (DBG_QOS, "RX max_sdu check failed");
2427 switch (rxtp->traffic_class) {
2435 vcc.rx_rate = 0; // ?
2440 int pcr = atm_pcr_goal (rxtp);
2442 // slight race (no locking) here so we may get -EAGAIN
2443 // later; the greedy bastards would deserve it :)
2444 PRINTD (DBG_QOS, "snatching all remaining RX bandwidth");
2445 pcr = dev->rx_avail;
2446 } else if (pcr < 0) {
2450 // not really clear what further checking is needed
2451 error = atm_pcr_check (rxtp, vcc.rx_rate);
2453 PRINTD (DBG_QOS, "RX PCR failed consistency check");
2460 // int scr = atm_scr_goal (rxtp);
2461 int scr = 1<<16; // just for fun
2463 // slight race (no locking) here so we may get -EAGAIN
2464 // later; the greedy bastards would deserve it :)
2465 PRINTD (DBG_QOS, "snatching all remaining RX bandwidth");
2466 scr = dev->rx_avail;
2467 } else if (scr < 0) {
2471 // not really clear what further checking is needed
2472 // error = atm_scr_check (rxtp, vcc.rx_rate);
2474 PRINTD (DBG_QOS, "RX SCR failed consistency check");
2481 PRINTD (DBG_QOS, "unsupported RX traffic class");
2489 // late abort useful for diagnostics
2490 if (vcc.aal != aal5) {
2491 PRINTD (DBG_QOS, "AAL not supported");
2495 // get space for our vcc stuff and copy parameters into it
2496 vccp = kmalloc (sizeof(hrz_vcc), GFP_KERNEL);
2498 PRINTK (KERN_ERR, "out of memory!");
2503 // clear error and grab cell rate resource lock
2505 spin_lock (&dev->rate_lock);
2507 if (vcc.tx_rate > dev->tx_avail) {
2508 PRINTD (DBG_QOS, "not enough TX PCR left");
2512 if (vcc.rx_rate > dev->rx_avail) {
2513 PRINTD (DBG_QOS, "not enough RX PCR left");
2518 // really consume cell rates
2519 dev->tx_avail -= vcc.tx_rate;
2520 dev->rx_avail -= vcc.rx_rate;
2521 PRINTD (DBG_QOS|DBG_VCC, "reserving %u TX PCR and %u RX PCR",
2522 vcc.tx_rate, vcc.rx_rate);
2525 // release lock and exit on error
2526 spin_unlock (&dev->rate_lock);
2528 PRINTD (DBG_QOS|DBG_VCC, "insufficient cell rate resources");
2533 // this is "immediately before allocating the connection identifier
2534 // in hardware" - so long as the next call does not fail :)
2535 set_bit(ATM_VF_ADDR,&atm_vcc->flags);
2537 // any errors here are very serious and should never occur
2539 if (rxtp->traffic_class != ATM_NONE) {
2540 if (dev->rxer[channel]) {
2541 PRINTD (DBG_ERR|DBG_VCC, "VC already open for RX");
2545 error = hrz_open_rx (dev, channel);
2550 // this link allows RX frames through
2551 dev->rxer[channel] = atm_vcc;
2554 // success, set elements of atm_vcc
2555 atm_vcc->dev_data = (void *) vccp;
2557 // indicate readiness
2558 set_bit(ATM_VF_READY,&atm_vcc->flags);
2563 /********** close VC **********/
2565 static void hrz_close (struct atm_vcc * atm_vcc) {
2566 hrz_dev * dev = HRZ_DEV(atm_vcc->dev);
2567 hrz_vcc * vcc = HRZ_VCC(atm_vcc);
2568 u16 channel = vcc->channel;
2569 PRINTD (DBG_VCC|DBG_FLOW, "hrz_close");
2571 // indicate unreadiness
2572 clear_bit(ATM_VF_READY,&atm_vcc->flags);
2574 if (atm_vcc->qos.txtp.traffic_class != ATM_NONE) {
2577 // let any TX on this channel that has started complete
2578 // no restart, just keep trying
2579 while (tx_hold (dev))
2581 // remove record of any tx_channel having been setup for this channel
2582 for (i = 0; i < TX_CHANS; ++i)
2583 if (dev->tx_channel_record[i] == channel) {
2584 dev->tx_channel_record[i] = -1;
2587 if (dev->last_vc == channel)
2592 if (atm_vcc->qos.rxtp.traffic_class != ATM_NONE) {
2593 // disable RXing - it tries quite hard
2594 hrz_close_rx (dev, channel);
2595 // forget the vcc - no more skbs will be pushed
2596 if (atm_vcc != dev->rxer[channel])
2597 PRINTK (KERN_ERR, "%s atm_vcc=%p rxer[channel]=%p",
2598 "arghhh! we're going to die!",
2599 atm_vcc, dev->rxer[channel]);
2600 dev->rxer[channel] = 0;
2603 // atomically release our rate reservation
2604 spin_lock (&dev->rate_lock);
2605 PRINTD (DBG_QOS|DBG_VCC, "releasing %u TX PCR and %u RX PCR",
2606 vcc->tx_rate, vcc->rx_rate);
2607 dev->tx_avail += vcc->tx_rate;
2608 dev->rx_avail += vcc->rx_rate;
2609 spin_unlock (&dev->rate_lock);
2611 // free our structure
2613 // say the VPI/VCI is free again
2614 clear_bit(ATM_VF_ADDR,&atm_vcc->flags);
2618 static int hrz_getsockopt (struct atm_vcc * atm_vcc, int level, int optname,
2619 void *optval, int optlen) {
2620 hrz_dev * dev = HRZ_DEV(atm_vcc->dev);
2621 PRINTD (DBG_FLOW|DBG_VCC, "hrz_getsockopt");
2630 return -ENOPROTOOPT;
2638 static int hrz_setsockopt (struct atm_vcc * atm_vcc, int level, int optname,
2639 void *optval, int optlen) {
2640 hrz_dev * dev = HRZ_DEV(atm_vcc->dev);
2641 PRINTD (DBG_FLOW|DBG_VCC, "hrz_setsockopt");
2650 return -ENOPROTOOPT;
2660 static int hrz_ioctl (struct atm_dev * atm_dev, unsigned int cmd, void *arg) {
2661 hrz_dev * dev = HRZ_DEV(atm_dev);
2662 PRINTD (DBG_FLOW, "hrz_ioctl");
2666 unsigned char hrz_phy_get (struct atm_dev * atm_dev, unsigned long addr) {
2667 hrz_dev * dev = HRZ_DEV(atm_dev);
2668 PRINTD (DBG_FLOW, "hrz_phy_get");
2672 static void hrz_phy_put (struct atm_dev * atm_dev, unsigned char value,
2673 unsigned long addr) {
2674 hrz_dev * dev = HRZ_DEV(atm_dev);
2675 PRINTD (DBG_FLOW, "hrz_phy_put");
2678 static int hrz_change_qos (struct atm_vcc * atm_vcc, struct atm_qos *qos, int flgs) {
2679 hrz_dev * dev = HRZ_DEV(vcc->dev);
2680 PRINTD (DBG_FLOW, "hrz_change_qos");
2685 /********** proc file contents **********/
2687 static int hrz_proc_read (struct atm_dev * atm_dev, loff_t * pos, char * page) {
2688 hrz_dev * dev = HRZ_DEV(atm_dev);
2690 PRINTD (DBG_FLOW, "hrz_proc_read");
2692 /* more diagnostics here? */
2696 unsigned int count = sprintf (page, "vbr buckets:");
2698 for (i = 0; i < TX_CHANS; ++i)
2699 count += sprintf (page, " %u/%u",
2700 query_tx_channel_config (dev, i, BUCKET_FULLNESS_ACCESS),
2701 query_tx_channel_config (dev, i, BUCKET_CAPACITY_ACCESS));
2702 count += sprintf (page+count, ".\n");
2708 return sprintf (page,
2709 "cells: TX %lu, RX %lu, HEC errors %lu, unassigned %lu.\n",
2710 dev->tx_cell_count, dev->rx_cell_count,
2711 dev->hec_error_count, dev->unassigned_cell_count);
2714 return sprintf (page,
2715 "free cell buffers: TX %hu, RX %hu+%hu.\n",
2716 rd_regw (dev, TX_FREE_BUFFER_COUNT_OFF),
2717 rd_regw (dev, RX_FREE_BUFFER_COUNT_OFF),
2718 dev->noof_spare_buffers);
2721 return sprintf (page,
2722 "cps remaining: TX %u, RX %u\n",
2723 dev->tx_avail, dev->rx_avail);
2728 static const struct atmdev_ops hrz_ops = {
2732 .proc_read = hrz_proc_read,
2733 .owner = THIS_MODULE,
2736 static int __init hrz_probe (void) {
2737 struct pci_dev * pci_dev;
2740 PRINTD (DBG_FLOW, "hrz_probe");
2744 while ((pci_dev = pci_find_device
2745 (PCI_VENDOR_ID_MADGE, PCI_DEVICE_ID_MADGE_HORIZON, pci_dev)
2749 // adapter slot free, read resources from PCI configuration space
2750 u32 iobase = pci_resource_start (pci_dev, 0);
2751 u32 * membase = bus_to_virt (pci_resource_start (pci_dev, 1));
2752 u8 irq = pci_dev->irq;
2754 /* XXX DEV_LABEL is a guess */
2755 if (!request_region (iobase, HRZ_IO_EXTENT, DEV_LABEL))
2758 if (pci_enable_device (pci_dev))
2761 dev = kmalloc (sizeof(hrz_dev), GFP_KERNEL);
2763 // perhaps we should be nice: deregister all adapters and abort?
2764 PRINTD (DBG_ERR, "out of memory");
2768 memset (dev, 0, sizeof(hrz_dev));
2770 // grab IRQ and install handler - move this someplace more sensible
2771 if (request_irq (irq,
2773 SA_SHIRQ, /* irqflags guess */
2774 DEV_LABEL, /* name guess */
2776 PRINTD (DBG_WARN, "request IRQ failed!");
2777 // free_irq is at "endif"
2780 PRINTD (DBG_INFO, "found Madge ATM adapter (hrz) at: IO %x, IRQ %u, MEM %p",
2781 iobase, irq, membase);
2783 dev->atm_dev = atm_dev_register (DEV_LABEL, &hrz_ops, -1, NULL);
2784 if (!(dev->atm_dev)) {
2785 PRINTD (DBG_ERR, "failed to register Madge ATM adapter");
2789 PRINTD (DBG_INFO, "registered Madge ATM adapter (no. %d) (%p) at %p",
2790 dev->atm_dev->number, dev, dev->atm_dev);
2791 dev->atm_dev->dev_data = (void *) dev;
2792 dev->pci_dev = pci_dev;
2794 // enable bus master accesses
2795 pci_set_master (pci_dev);
2797 // frobnicate latency (upwards, usually)
2798 pci_read_config_byte (pci_dev, PCI_LATENCY_TIMER, &lat);
2800 PRINTD (DBG_INFO, "%s PCI latency timer from %hu to %hu",
2801 "changing", lat, pci_lat);
2802 pci_write_config_byte (pci_dev, PCI_LATENCY_TIMER, pci_lat);
2803 } else if (lat < MIN_PCI_LATENCY) {
2804 PRINTK (KERN_INFO, "%s PCI latency timer from %hu to %hu",
2805 "increasing", lat, MIN_PCI_LATENCY);
2806 pci_write_config_byte (pci_dev, PCI_LATENCY_TIMER, MIN_PCI_LATENCY);
2809 dev->iobase = iobase;
2811 dev->membase = membase;
2813 dev->rx_q_entry = dev->rx_q_reset = &memmap->rx_q_entries[0];
2814 dev->rx_q_wrap = &memmap->rx_q_entries[RX_CHANS-1];
2816 // these next three are performance hacks
2821 dev->tx_regions = 0;
2826 dev->tx_cell_count = 0;
2827 dev->rx_cell_count = 0;
2828 dev->hec_error_count = 0;
2829 dev->unassigned_cell_count = 0;
2831 dev->noof_spare_buffers = 0;
2835 for (i = 0; i < TX_CHANS; ++i)
2836 dev->tx_channel_record[i] = -1;
2841 // Allocate cell rates and remember ASIC version
2842 // Fibre: ATM_OC3_PCR = 1555200000/8/270*260/53 - 29/53
2843 // Copper: (WRONG) we want 6 into the above, close to 25Mb/s
2844 // Copper: (plagarise!) 25600000/8/270*260/53 - n/53
2846 if (hrz_init (dev)) {
2847 // to be really pedantic, this should be ATM_OC3c_PCR
2848 dev->tx_avail = ATM_OC3_PCR;
2849 dev->rx_avail = ATM_OC3_PCR;
2850 set_bit (ultra, &dev->flags); // NOT "|= ultra" !
2852 dev->tx_avail = ((25600000/8)*26)/(27*53);
2853 dev->rx_avail = ((25600000/8)*26)/(27*53);
2854 PRINTD (DBG_WARN, "Buggy ASIC: no TX bus-mastering.");
2857 // rate changes spinlock
2858 spin_lock_init (&dev->rate_lock);
2860 // on-board memory access spinlock; we want atomic reads and
2861 // writes to adapter memory (handles IRQ and SMP)
2862 spin_lock_init (&dev->mem_lock);
2864 init_waitqueue_head (&dev->tx_queue);
2866 // vpi in 0..4, vci in 6..10
2867 dev->atm_dev->ci_range.vpi_bits = vpi_bits;
2868 dev->atm_dev->ci_range.vci_bits = 10-vpi_bits;
2870 // update count and linked list
2872 dev->prev = hrz_devs;
2877 /* not currently reached */
2878 atm_dev_deregister (dev->atm_dev);
2879 } /* atm_dev_register */
2880 free_irq (irq, dev);
2884 release_region(iobase, HRZ_IO_EXTENT);
2885 } /* kmalloc and while */
2889 static void __init hrz_check_args (void) {
2890 #ifdef DEBUG_HORIZON
2891 PRINTK (KERN_NOTICE, "debug bitmap is %hx", debug &= DBG_MASK);
2894 PRINTK (KERN_NOTICE, "no debug support in this image");
2897 if (vpi_bits > HRZ_MAX_VPI)
2898 PRINTK (KERN_ERR, "vpi_bits has been limited to %hu",
2899 vpi_bits = HRZ_MAX_VPI);
2901 if (max_tx_size < 0 || max_tx_size > TX_AAL5_LIMIT)
2902 PRINTK (KERN_NOTICE, "max_tx_size has been limited to %hu",
2903 max_tx_size = TX_AAL5_LIMIT);
2905 if (max_rx_size < 0 || max_rx_size > RX_AAL5_LIMIT)
2906 PRINTK (KERN_NOTICE, "max_rx_size has been limited to %hu",
2907 max_rx_size = RX_AAL5_LIMIT);
2912 MODULE_AUTHOR(maintainer_string);
2913 MODULE_DESCRIPTION(description_string);
2914 MODULE_LICENSE("GPL");
2915 MODULE_PARM(debug, "h");
2916 MODULE_PARM(vpi_bits, "h");
2917 MODULE_PARM(max_tx_size, "i");
2918 MODULE_PARM(max_rx_size, "i");
2919 MODULE_PARM(pci_lat, "b");
2920 MODULE_PARM_DESC(debug, "debug bitmap, see .h file");
2921 MODULE_PARM_DESC(vpi_bits, "number of bits (0..4) to allocate to VPIs");
2922 MODULE_PARM_DESC(max_tx_size, "maximum size of TX AAL5 frames");
2923 MODULE_PARM_DESC(max_rx_size, "maximum size of RX AAL5 frames");
2924 MODULE_PARM_DESC(pci_lat, "PCI latency in bus cycles");
2926 /********** module entry **********/
2928 static int __init hrz_module_init (void) {
2931 // sanity check - cast is needed since printk does not support %Zu
2932 if (sizeof(struct MEMMAP) != 128*1024/4) {
2933 PRINTK (KERN_ERR, "Fix struct MEMMAP (is %lu fakewords).",
2934 (unsigned long) sizeof(struct MEMMAP));
2947 init_timer (&housekeeping);
2948 housekeeping.function = do_housekeeping;
2950 housekeeping.data = 1;
2951 set_timer (&housekeeping, 0);
2953 PRINTK (KERN_ERR, "no (usable) adapters found");
2956 return devs ? 0 : -ENODEV;
2959 /********** module exit **********/
2961 static void __exit hrz_module_exit (void) {
2963 PRINTD (DBG_FLOW, "cleanup_module");
2966 housekeeping.data = 0;
2967 del_timer (&housekeeping);
2971 hrz_devs = dev->prev;
2973 PRINTD (DBG_INFO, "closing %p (atm_dev = %p)", dev, dev->atm_dev);
2975 atm_dev_deregister (dev->atm_dev);
2976 free_irq (dev->irq, dev);
2977 release_region (dev->iobase, HRZ_IO_EXTENT);
2984 module_init(hrz_module_init);
2985 module_exit(hrz_module_exit);