1 /* r128_drv.h -- Private header for r128 driver -*- linux-c -*-
2 * Created: Mon Dec 13 09:51:11 1999 by faith@precisioninsight.com
4 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
28 * Rickard E. (Rik) Faith <faith@valinux.com>
29 * Kevin E. Martin <martin@valinux.com>
30 * Gareth Hughes <gareth@valinux.com>
31 * Michel Dänzer <daenzerm@student.ethz.ch>
34 #ifndef __R128_DRV_H__
35 #define __R128_DRV_H__
37 #define GET_RING_HEAD(ring) DRM_READ32( (ring)->ring_rptr, 0 ) /* (ring)->head */
38 #define SET_RING_HEAD(ring,val) DRM_WRITE32( (ring)->ring_rptr, 0, (val) ) /* (ring)->head */
40 typedef struct drm_r128_freelist {
43 struct drm_r128_freelist *next;
44 struct drm_r128_freelist *prev;
45 } drm_r128_freelist_t;
47 typedef struct drm_r128_ring_buffer {
59 drm_local_map_t *ring_rptr;
60 } drm_r128_ring_buffer_t;
62 typedef struct drm_r128_private {
63 drm_r128_ring_buffer_t ring;
64 drm_r128_sarea_t *sarea_priv;
70 drm_r128_freelist_t *head;
71 drm_r128_freelist_t *tail;
75 unsigned long phys_pci_gart;
76 dma_addr_t bus_pci_gart;
77 unsigned long cce_buffers_offset;
87 unsigned int front_offset;
88 unsigned int front_pitch;
89 unsigned int back_offset;
90 unsigned int back_pitch;
93 unsigned int depth_offset;
94 unsigned int depth_pitch;
95 unsigned int span_offset;
97 u32 front_pitch_offset_c;
98 u32 back_pitch_offset_c;
99 u32 depth_pitch_offset_c;
100 u32 span_pitch_offset_c;
102 drm_local_map_t *sarea;
104 drm_local_map_t *mmio;
105 drm_local_map_t *cce_ring;
106 drm_local_map_t *ring_rptr;
107 drm_local_map_t *buffers;
108 drm_local_map_t *agp_textures;
109 } drm_r128_private_t;
111 typedef struct drm_r128_buf_priv {
116 drm_r128_freelist_t *list_entry;
117 } drm_r128_buf_priv_t;
120 extern int r128_cce_init( DRM_IOCTL_ARGS );
121 extern int r128_cce_start( DRM_IOCTL_ARGS );
122 extern int r128_cce_stop( DRM_IOCTL_ARGS );
123 extern int r128_cce_reset( DRM_IOCTL_ARGS );
124 extern int r128_cce_idle( DRM_IOCTL_ARGS );
125 extern int r128_engine_reset( DRM_IOCTL_ARGS );
126 extern int r128_fullscreen( DRM_IOCTL_ARGS );
127 extern int r128_cce_buffers( DRM_IOCTL_ARGS );
128 extern int r128_getparam( DRM_IOCTL_ARGS );
130 extern void r128_freelist_reset( drm_device_t *dev );
131 extern drm_buf_t *r128_freelist_get( drm_device_t *dev );
133 extern int r128_wait_ring( drm_r128_private_t *dev_priv, int n );
135 static __inline__ void
136 r128_update_ring_snapshot( drm_r128_ring_buffer_t *ring )
138 ring->space = (GET_RING_HEAD( ring ) - ring->tail) * sizeof(u32);
139 if ( ring->space <= 0 )
140 ring->space += ring->size;
143 extern int r128_do_cce_idle( drm_r128_private_t *dev_priv );
144 extern int r128_do_cleanup_cce( drm_device_t *dev );
145 extern int r128_do_cleanup_pageflip( drm_device_t *dev );
148 extern int r128_cce_clear( DRM_IOCTL_ARGS );
149 extern int r128_cce_swap( DRM_IOCTL_ARGS );
150 extern int r128_cce_flip( DRM_IOCTL_ARGS );
151 extern int r128_cce_vertex( DRM_IOCTL_ARGS );
152 extern int r128_cce_indices( DRM_IOCTL_ARGS );
153 extern int r128_cce_blit( DRM_IOCTL_ARGS );
154 extern int r128_cce_depth( DRM_IOCTL_ARGS );
155 extern int r128_cce_stipple( DRM_IOCTL_ARGS );
156 extern int r128_cce_indirect( DRM_IOCTL_ARGS );
159 /* Register definitions, register access macros and drmAddMap constants
160 * for Rage 128 kernel driver.
163 #define R128_AUX_SC_CNTL 0x1660
164 # define R128_AUX1_SC_EN (1 << 0)
165 # define R128_AUX1_SC_MODE_OR (0 << 1)
166 # define R128_AUX1_SC_MODE_NAND (1 << 1)
167 # define R128_AUX2_SC_EN (1 << 2)
168 # define R128_AUX2_SC_MODE_OR (0 << 3)
169 # define R128_AUX2_SC_MODE_NAND (1 << 3)
170 # define R128_AUX3_SC_EN (1 << 4)
171 # define R128_AUX3_SC_MODE_OR (0 << 5)
172 # define R128_AUX3_SC_MODE_NAND (1 << 5)
173 #define R128_AUX1_SC_LEFT 0x1664
174 #define R128_AUX1_SC_RIGHT 0x1668
175 #define R128_AUX1_SC_TOP 0x166c
176 #define R128_AUX1_SC_BOTTOM 0x1670
177 #define R128_AUX2_SC_LEFT 0x1674
178 #define R128_AUX2_SC_RIGHT 0x1678
179 #define R128_AUX2_SC_TOP 0x167c
180 #define R128_AUX2_SC_BOTTOM 0x1680
181 #define R128_AUX3_SC_LEFT 0x1684
182 #define R128_AUX3_SC_RIGHT 0x1688
183 #define R128_AUX3_SC_TOP 0x168c
184 #define R128_AUX3_SC_BOTTOM 0x1690
186 #define R128_BRUSH_DATA0 0x1480
187 #define R128_BUS_CNTL 0x0030
188 # define R128_BUS_MASTER_DIS (1 << 6)
190 #define R128_CLOCK_CNTL_INDEX 0x0008
191 #define R128_CLOCK_CNTL_DATA 0x000c
192 # define R128_PLL_WR_EN (1 << 7)
193 #define R128_CONSTANT_COLOR_C 0x1d34
194 #define R128_CRTC_OFFSET 0x0224
195 #define R128_CRTC_OFFSET_CNTL 0x0228
196 # define R128_CRTC_OFFSET_FLIP_CNTL (1 << 16)
198 #define R128_DP_GUI_MASTER_CNTL 0x146c
199 # define R128_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
200 # define R128_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
201 # define R128_GMC_BRUSH_SOLID_COLOR (13 << 4)
202 # define R128_GMC_BRUSH_NONE (15 << 4)
203 # define R128_GMC_DST_16BPP (4 << 8)
204 # define R128_GMC_DST_24BPP (5 << 8)
205 # define R128_GMC_DST_32BPP (6 << 8)
206 # define R128_GMC_DST_DATATYPE_SHIFT 8
207 # define R128_GMC_SRC_DATATYPE_COLOR (3 << 12)
208 # define R128_DP_SRC_SOURCE_MEMORY (2 << 24)
209 # define R128_DP_SRC_SOURCE_HOST_DATA (3 << 24)
210 # define R128_GMC_CLR_CMP_CNTL_DIS (1 << 28)
211 # define R128_GMC_AUX_CLIP_DIS (1 << 29)
212 # define R128_GMC_WR_MSK_DIS (1 << 30)
213 # define R128_ROP3_S 0x00cc0000
214 # define R128_ROP3_P 0x00f00000
215 #define R128_DP_WRITE_MASK 0x16cc
216 #define R128_DST_PITCH_OFFSET_C 0x1c80
217 # define R128_DST_TILE (1 << 31)
219 #define R128_GEN_INT_CNTL 0x0040
220 # define R128_CRTC_VBLANK_INT_EN (1 << 0)
221 #define R128_GEN_INT_STATUS 0x0044
222 # define R128_CRTC_VBLANK_INT (1 << 0)
223 # define R128_CRTC_VBLANK_INT_AK (1 << 0)
224 #define R128_GEN_RESET_CNTL 0x00f0
225 # define R128_SOFT_RESET_GUI (1 << 0)
227 #define R128_GUI_SCRATCH_REG0 0x15e0
228 #define R128_GUI_SCRATCH_REG1 0x15e4
229 #define R128_GUI_SCRATCH_REG2 0x15e8
230 #define R128_GUI_SCRATCH_REG3 0x15ec
231 #define R128_GUI_SCRATCH_REG4 0x15f0
232 #define R128_GUI_SCRATCH_REG5 0x15f4
234 #define R128_GUI_STAT 0x1740
235 # define R128_GUI_FIFOCNT_MASK 0x0fff
236 # define R128_GUI_ACTIVE (1 << 31)
238 #define R128_MCLK_CNTL 0x000f
239 # define R128_FORCE_GCP (1 << 16)
240 # define R128_FORCE_PIPE3D_CP (1 << 17)
241 # define R128_FORCE_RCP (1 << 18)
243 #define R128_PC_GUI_CTLSTAT 0x1748
244 #define R128_PC_NGUI_CTLSTAT 0x0184
245 # define R128_PC_FLUSH_GUI (3 << 0)
246 # define R128_PC_RI_GUI (1 << 2)
247 # define R128_PC_FLUSH_ALL 0x00ff
248 # define R128_PC_BUSY (1 << 31)
250 #define R128_PCI_GART_PAGE 0x017c
251 #define R128_PRIM_TEX_CNTL_C 0x1cb0
253 #define R128_SCALE_3D_CNTL 0x1a00
254 #define R128_SEC_TEX_CNTL_C 0x1d00
255 #define R128_SEC_TEXTURE_BORDER_COLOR_C 0x1d3c
256 #define R128_SETUP_CNTL 0x1bc4
257 #define R128_STEN_REF_MASK_C 0x1d40
259 #define R128_TEX_CNTL_C 0x1c9c
260 # define R128_TEX_CACHE_FLUSH (1 << 23)
262 #define R128_WAIT_UNTIL 0x1720
263 # define R128_EVENT_CRTC_OFFSET (1 << 0)
264 #define R128_WINDOW_XY_OFFSET 0x1bcc
269 #define R128_PM4_BUFFER_OFFSET 0x0700
270 #define R128_PM4_BUFFER_CNTL 0x0704
271 # define R128_PM4_MASK (15 << 28)
272 # define R128_PM4_NONPM4 (0 << 28)
273 # define R128_PM4_192PIO (1 << 28)
274 # define R128_PM4_192BM (2 << 28)
275 # define R128_PM4_128PIO_64INDBM (3 << 28)
276 # define R128_PM4_128BM_64INDBM (4 << 28)
277 # define R128_PM4_64PIO_128INDBM (5 << 28)
278 # define R128_PM4_64BM_128INDBM (6 << 28)
279 # define R128_PM4_64PIO_64VCBM_64INDBM (7 << 28)
280 # define R128_PM4_64BM_64VCBM_64INDBM (8 << 28)
281 # define R128_PM4_64PIO_64VCPIO_64INDPIO (15 << 28)
283 #define R128_PM4_BUFFER_WM_CNTL 0x0708
284 # define R128_WMA_SHIFT 0
285 # define R128_WMB_SHIFT 8
286 # define R128_WMC_SHIFT 16
287 # define R128_WB_WM_SHIFT 24
289 #define R128_PM4_BUFFER_DL_RPTR_ADDR 0x070c
290 #define R128_PM4_BUFFER_DL_RPTR 0x0710
291 #define R128_PM4_BUFFER_DL_WPTR 0x0714
292 # define R128_PM4_BUFFER_DL_DONE (1 << 31)
294 #define R128_PM4_VC_FPU_SETUP 0x071c
296 #define R128_PM4_IW_INDOFF 0x0738
297 #define R128_PM4_IW_INDSIZE 0x073c
299 #define R128_PM4_STAT 0x07b8
300 # define R128_PM4_FIFOCNT_MASK 0x0fff
301 # define R128_PM4_BUSY (1 << 16)
302 # define R128_PM4_GUI_ACTIVE (1 << 31)
304 #define R128_PM4_MICROCODE_ADDR 0x07d4
305 #define R128_PM4_MICROCODE_RADDR 0x07d8
306 #define R128_PM4_MICROCODE_DATAH 0x07dc
307 #define R128_PM4_MICROCODE_DATAL 0x07e0
309 #define R128_PM4_BUFFER_ADDR 0x07f0
310 #define R128_PM4_MICRO_CNTL 0x07fc
311 # define R128_PM4_MICRO_FREERUN (1 << 30)
313 #define R128_PM4_FIFO_DATA_EVEN 0x1000
314 #define R128_PM4_FIFO_DATA_ODD 0x1004
317 /* CCE command packets
319 #define R128_CCE_PACKET0 0x00000000
320 #define R128_CCE_PACKET1 0x40000000
321 #define R128_CCE_PACKET2 0x80000000
322 #define R128_CCE_PACKET3 0xC0000000
323 # define R128_CNTL_HOSTDATA_BLT 0x00009400
324 # define R128_CNTL_PAINT_MULTI 0x00009A00
325 # define R128_CNTL_BITBLT_MULTI 0x00009B00
326 # define R128_3D_RNDR_GEN_INDX_PRIM 0x00002300
328 #define R128_CCE_PACKET_MASK 0xC0000000
329 #define R128_CCE_PACKET_COUNT_MASK 0x3fff0000
330 #define R128_CCE_PACKET0_REG_MASK 0x000007ff
331 #define R128_CCE_PACKET1_REG0_MASK 0x000007ff
332 #define R128_CCE_PACKET1_REG1_MASK 0x003ff800
334 #define R128_CCE_VC_CNTL_PRIM_TYPE_NONE 0x00000000
335 #define R128_CCE_VC_CNTL_PRIM_TYPE_POINT 0x00000001
336 #define R128_CCE_VC_CNTL_PRIM_TYPE_LINE 0x00000002
337 #define R128_CCE_VC_CNTL_PRIM_TYPE_POLY_LINE 0x00000003
338 #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_LIST 0x00000004
339 #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_FAN 0x00000005
340 #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_STRIP 0x00000006
341 #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2 0x00000007
342 #define R128_CCE_VC_CNTL_PRIM_WALK_IND 0x00000010
343 #define R128_CCE_VC_CNTL_PRIM_WALK_LIST 0x00000020
344 #define R128_CCE_VC_CNTL_PRIM_WALK_RING 0x00000030
345 #define R128_CCE_VC_CNTL_NUM_SHIFT 16
347 #define R128_DATATYPE_VQ 0
348 #define R128_DATATYPE_CI4 1
349 #define R128_DATATYPE_CI8 2
350 #define R128_DATATYPE_ARGB1555 3
351 #define R128_DATATYPE_RGB565 4
352 #define R128_DATATYPE_RGB888 5
353 #define R128_DATATYPE_ARGB8888 6
354 #define R128_DATATYPE_RGB332 7
355 #define R128_DATATYPE_Y8 8
356 #define R128_DATATYPE_RGB8 9
357 #define R128_DATATYPE_CI16 10
358 #define R128_DATATYPE_YVYU422 11
359 #define R128_DATATYPE_VYUY422 12
360 #define R128_DATATYPE_AYUV444 14
361 #define R128_DATATYPE_ARGB4444 15
364 #define R128_AGP_OFFSET 0x02000000
366 #define R128_WATERMARK_L 16
367 #define R128_WATERMARK_M 8
368 #define R128_WATERMARK_N 8
369 #define R128_WATERMARK_K 128
371 #define R128_MAX_USEC_TIMEOUT 100000 /* 100 ms */
373 #define R128_LAST_FRAME_REG R128_GUI_SCRATCH_REG0
374 #define R128_LAST_DISPATCH_REG R128_GUI_SCRATCH_REG1
375 #define R128_MAX_VB_AGE 0x7fffffff
376 #define R128_MAX_VB_VERTS (0xffff)
378 #define R128_RING_HIGH_MARK 128
380 #define R128_PERFORMANCE_BOXES 0
382 #define R128_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
383 #define R128_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) )
384 #define R128_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
385 #define R128_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
387 #define R128_WRITE_PLL(addr,val) \
389 R128_WRITE8(R128_CLOCK_CNTL_INDEX, \
390 ((addr) & 0x1f) | R128_PLL_WR_EN); \
391 R128_WRITE(R128_CLOCK_CNTL_DATA, (val)); \
394 extern int R128_READ_PLL(drm_device_t *dev, int addr);
397 #define CCE_PACKET0( reg, n ) (R128_CCE_PACKET0 | \
398 ((n) << 16) | ((reg) >> 2))
399 #define CCE_PACKET1( reg0, reg1 ) (R128_CCE_PACKET1 | \
400 (((reg1) >> 2) << 11) | ((reg0) >> 2))
401 #define CCE_PACKET2() (R128_CCE_PACKET2)
402 #define CCE_PACKET3( pkt, n ) (R128_CCE_PACKET3 | \
406 /* ================================================================
410 #define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \
412 drm_r128_ring_buffer_t *ring = &dev_priv->ring; int i; \
413 if ( ring->space < ring->high_mark ) { \
414 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { \
415 r128_update_ring_snapshot( ring ); \
416 if ( ring->space >= ring->high_mark ) \
417 goto __ring_space_done; \
420 DRM_ERROR( "ring space check failed!\n" ); \
421 return DRM_ERR(EBUSY); \
427 #define VB_AGE_TEST_WITH_RETURN( dev_priv ) \
429 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; \
430 if ( sarea_priv->last_dispatch >= R128_MAX_VB_AGE ) { \
431 int __ret = r128_do_cce_idle( dev_priv ); \
432 if ( __ret ) return __ret; \
433 sarea_priv->last_dispatch = 0; \
434 r128_freelist_reset( dev ); \
438 #define R128_WAIT_UNTIL_PAGE_FLIPPED() do { \
439 OUT_RING( CCE_PACKET0( R128_WAIT_UNTIL, 0 ) ); \
440 OUT_RING( R128_EVENT_CRTC_OFFSET ); \
444 /* ================================================================
448 #if defined(__powerpc__)
449 #define r128_flush_write_combine() (void) GET_RING_HEAD( &dev_priv->ring )
451 #define r128_flush_write_combine() DRM_WRITEMEMORYBARRIER()
455 #define R128_VERBOSE 0
457 #define RING_LOCALS \
458 int write; unsigned int tail_mask; volatile u32 *ring;
460 #define BEGIN_RING( n ) do { \
461 if ( R128_VERBOSE ) { \
462 DRM_INFO( "BEGIN_RING( %d ) in %s\n", \
463 (n), __FUNCTION__ ); \
465 if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \
466 r128_wait_ring( dev_priv, (n) * sizeof(u32) ); \
468 dev_priv->ring.space -= (n) * sizeof(u32); \
469 ring = dev_priv->ring.start; \
470 write = dev_priv->ring.tail; \
471 tail_mask = dev_priv->ring.tail_mask; \
474 /* You can set this to zero if you want. If the card locks up, you'll
475 * need to keep this set. It works around a bug in early revs of the
476 * Rage 128 chipset, where the CCE would read 32 dwords past the end of
477 * the ring buffer before wrapping around.
479 #define R128_BROKEN_CCE 1
481 #define ADVANCE_RING() do { \
482 if ( R128_VERBOSE ) { \
483 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \
484 write, dev_priv->ring.tail ); \
486 if ( R128_BROKEN_CCE && write < 32 ) { \
487 memcpy( dev_priv->ring.end, \
488 dev_priv->ring.start, \
489 write * sizeof(u32) ); \
491 r128_flush_write_combine(); \
492 dev_priv->ring.tail = write; \
493 R128_WRITE( R128_PM4_BUFFER_DL_WPTR, write ); \
496 #define OUT_RING( x ) do { \
497 if ( R128_VERBOSE ) { \
498 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \
499 (unsigned int)(x), write ); \
501 ring[write++] = cpu_to_le32( x ); \
502 write &= tail_mask; \
505 #endif /* __R128_DRV_H__ */