2 * RocketPort device driver for Linux
4 * Written by Theodore Ts'o, 1995, 1996, 1997, 1998, 1999, 2000.
6 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2003 by Comtrol, Inc.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of the
11 * License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 * Kernel Synchronization:
26 * This driver has 2 kernel control paths - exception handlers (calls into the driver
27 * from user mode) and the timer bottom half (tasklet). This is a polled driver, interrupts
31 * - rp_table[], accessed through passed "info" pointers, is a global (static) array of
32 * serial port state information and the xmit_buf circular buffer. Protected by
33 * a per port spinlock.
34 * - xmit_flags[], an array of ints indexed by line (port) number, indicating that there
35 * is data to be transmitted. Protected by atomic bit operations.
36 * - rp_num_ports, int indicating number of open ports, protected by atomic operations.
38 * rp_write() and rp_write_char() functions use a per port semaphore to protect against
39 * simultaneous access to the same port by more than one process.
42 /****** Defines ******/
43 #ifdef PCI_NUM_RESOURCES
44 #define PCI_BASE_ADDRESS(dev, r) ((dev)->resource[r].start)
46 #define PCI_BASE_ADDRESS(dev, r) ((dev)->base_address[r])
49 #define ROCKET_PARANOIA_CHECK
50 #define ROCKET_DISABLE_SIMUSAGE
52 #undef ROCKET_SOFT_FLOW
53 #undef ROCKET_DEBUG_OPEN
54 #undef ROCKET_DEBUG_INTR
55 #undef ROCKET_DEBUG_WRITE
56 #undef ROCKET_DEBUG_FLOW
57 #undef ROCKET_DEBUG_THROTTLE
58 #undef ROCKET_DEBUG_WAIT_UNTIL_SENT
59 #undef ROCKET_DEBUG_RECEIVE
60 #undef ROCKET_DEBUG_HANGUP
62 #undef ROCKET_DEBUG_IO
64 #define POLL_PERIOD HZ/100 /* Polling period .01 seconds (10ms) */
66 /****** Kernel includes ******/
69 #include <config/modversions.h>
72 #include <linux/module.h>
73 #include <linux/errno.h>
74 #include <linux/major.h>
75 #include <linux/kernel.h>
76 #include <linux/signal.h>
77 #include <linux/slab.h>
79 #include <linux/sched.h>
80 #include <linux/timer.h>
81 #include <linux/interrupt.h>
82 #include <linux/tty.h>
83 #include <linux/tty_driver.h>
84 #include <linux/tty_flip.h>
85 #include <linux/string.h>
86 #include <linux/fcntl.h>
87 #include <linux/ptrace.h>
88 #include <linux/ioport.h>
89 #include <linux/delay.h>
90 #include <linux/wait.h>
91 #include <linux/pci.h>
92 #include <asm/uaccess.h>
93 #include <asm/atomic.h>
94 #include <asm/bitops.h>
95 #include <linux/spinlock.h>
96 #include <asm/semaphore.h>
97 #include <linux/init.h>
99 /****** RocketPort includes ******/
101 #include "rocket_int.h"
104 #define ROCKET_VERSION "2.09"
105 #define ROCKET_DATE "12-June-2003"
107 /****** RocketPort Local Variables ******/
109 static struct tty_driver *rocket_driver;
111 static struct rocket_version driver_version = {
112 ROCKET_VERSION, ROCKET_DATE
115 static struct r_port *rp_table[MAX_RP_PORTS]; /* The main repository of serial port state information. */
116 static unsigned int xmit_flags[NUM_BOARDS]; /* Bit significant, indicates port had data to transmit. */
117 /* eg. Bit 0 indicates port 0 has xmit data, ... */
118 static atomic_t rp_num_ports_open; /* Number of serial ports open */
119 static struct timer_list rocket_timer;
121 static unsigned long board1; /* ISA addresses, retrieved from rocketport.conf */
122 static unsigned long board2;
123 static unsigned long board3;
124 static unsigned long board4;
125 static unsigned long controller;
126 static unsigned long support_low_speed;
127 static unsigned long modem1;
128 static unsigned long modem2;
129 static unsigned long modem3;
130 static unsigned long modem4;
131 static unsigned long pc104_1[8];
132 static unsigned long pc104_2[8];
133 static unsigned long pc104_3[8];
134 static unsigned long pc104_4[8];
135 static unsigned long *pc104[4] = { pc104_1, pc104_2, pc104_3, pc104_4 };
137 static int rp_baud_base[NUM_BOARDS]; /* Board config info (Someday make a per-board structure) */
138 static unsigned long rcktpt_io_addr[NUM_BOARDS];
139 static int rcktpt_type[NUM_BOARDS];
140 static int is_PCI[NUM_BOARDS];
141 static rocketModel_t rocketModel[NUM_BOARDS];
142 static int max_board;
145 * The following arrays define the interrupt bits corresponding to each AIOP.
146 * These bits are different between the ISA and regular PCI boards and the
147 * Universal PCI boards.
150 static Word_t aiop_intr_bits[AIOP_CTL_SIZE] = {
157 static Word_t upci_aiop_intr_bits[AIOP_CTL_SIZE] = {
158 UPCI_AIOP_INTR_BIT_0,
159 UPCI_AIOP_INTR_BIT_1,
160 UPCI_AIOP_INTR_BIT_2,
165 * Line number is the ttySIx number (x), the Minor number. We
166 * assign them sequentially, starting at zero. The following
167 * array keeps track of the line number assigned to a given board/aiop/channel.
169 static unsigned char lineNumbers[MAX_RP_PORTS];
170 static unsigned long nextLineNumber;
172 /***** RocketPort Static Prototypes *********/
173 static int __init init_ISA(int i);
174 static void rp_wait_until_sent(struct tty_struct *tty, int timeout);
175 static void rp_flush_buffer(struct tty_struct *tty);
176 static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model);
177 static unsigned char GetLineNumber(int ctrl, int aiop, int ch);
178 static unsigned char SetLineNumber(int ctrl, int aiop, int ch);
179 static void rp_start(struct tty_struct *tty);
182 MODULE_AUTHOR("Theodore Ts'o");
183 MODULE_DESCRIPTION("Comtrol RocketPort driver");
184 MODULE_PARM(board1, "i");
185 MODULE_PARM_DESC(board1, "I/O port for (ISA) board #1");
186 MODULE_PARM(board2, "i");
187 MODULE_PARM_DESC(board2, "I/O port for (ISA) board #2");
188 MODULE_PARM(board3, "i");
189 MODULE_PARM_DESC(board3, "I/O port for (ISA) board #3");
190 MODULE_PARM(board4, "i");
191 MODULE_PARM_DESC(board4, "I/O port for (ISA) board #4");
192 MODULE_PARM(controller, "i");
193 MODULE_PARM_DESC(controller, "I/O port for (ISA) rocketport controller");
194 MODULE_PARM(support_low_speed, "i");
195 MODULE_PARM_DESC(support_low_speed, "1 means support 50 baud, 0 means support 460400 baud");
196 MODULE_PARM(modem1, "i");
197 MODULE_PARM_DESC(modem1, "1 means (ISA) board #1 is a RocketModem");
198 MODULE_PARM(modem2, "i");
199 MODULE_PARM_DESC(modem2, "1 means (ISA) board #2 is a RocketModem");
200 MODULE_PARM(modem3, "i");
201 MODULE_PARM_DESC(modem3, "1 means (ISA) board #3 is a RocketModem");
202 MODULE_PARM(modem4, "i");
203 MODULE_PARM_DESC(modem4, "1 means (ISA) board #4 is a RocketModem");
204 MODULE_PARM(pc104_1, "1-8i");
205 MODULE_PARM_DESC(pc104_1, "set interface types for ISA(PC104) board #1 (e.g. pc104_1=232,232,485,485,...");
206 MODULE_PARM(pc104_2, "1-8i");
207 MODULE_PARM_DESC(pc104_2, "set interface types for ISA(PC104) board #2 (e.g. pc104_2=232,232,485,485,...");
208 MODULE_PARM(pc104_3, "1-8i");
209 MODULE_PARM_DESC(pc104_3, "set interface types for ISA(PC104) board #3 (e.g. pc104_3=232,232,485,485,...");
210 MODULE_PARM(pc104_4, "1-8i");
211 MODULE_PARM_DESC(pc104_4, "set interface types for ISA(PC104) board #4 (e.g. pc104_4=232,232,485,485,...");
214 static void rp_cleanup_module(void);
216 module_init(rp_init);
217 module_exit(rp_cleanup_module);
221 #ifdef MODULE_LICENSE
222 MODULE_LICENSE("Dual BSD/GPL");
225 /*************************************************************************/
226 /* Module code starts here */
228 static inline int rocket_paranoia_check(struct r_port *info,
231 #ifdef ROCKET_PARANOIA_CHECK
234 if (info->magic != RPORT_MAGIC) {
235 printk(KERN_INFO "Warning: bad magic number for rocketport struct in %s\n",
244 /* Serial port receive data function. Called (from timer poll) when an AIOPIC signals
245 * that receive data is present on a serial port. Pulls data from FIFO, moves it into the
248 static void rp_do_receive(struct r_port *info,
249 struct tty_struct *tty,
250 CHANNEL_t * cp, unsigned int ChanStatus)
252 unsigned int CharNStat;
253 int ToRecv, wRecv, space, count;
257 ToRecv = sGetRxCnt(cp);
258 space = tty->ldisc.receive_room(tty);
259 if (space > 2 * TTY_FLIPBUF_SIZE)
260 space = 2 * TTY_FLIPBUF_SIZE;
261 cbuf = tty->flip.char_buf;
262 fbuf = tty->flip.flag_buf;
264 #ifdef ROCKET_DEBUG_INTR
265 printk(KERN_INFO "rp_do_receive(%d, %d)...", ToRecv, space);
269 * determine how many we can actually read in. If we can't
270 * read any in then we have a software overrun condition.
279 * if status indicates there are errored characters in the
280 * FIFO, then enter status mode (a word in FIFO holds
281 * character and status).
283 if (ChanStatus & (RXFOVERFL | RXBREAK | RXFRAME | RXPARITY)) {
284 if (!(ChanStatus & STATMODE)) {
285 #ifdef ROCKET_DEBUG_RECEIVE
286 printk(KERN_INFO "Entering STATMODE...");
288 ChanStatus |= STATMODE;
294 * if we previously entered status mode, then read down the
295 * FIFO one word at a time, pulling apart the character and
296 * the status. Update error counters depending on status
298 if (ChanStatus & STATMODE) {
299 #ifdef ROCKET_DEBUG_RECEIVE
300 printk(KERN_INFO "Ignore %x, read %x...", info->ignore_status_mask,
301 info->read_status_mask);
304 CharNStat = sInW(sGetTxRxDataIO(cp));
305 #ifdef ROCKET_DEBUG_RECEIVE
306 printk(KERN_INFO "%x...", CharNStat);
308 if (CharNStat & STMBREAKH)
309 CharNStat &= ~(STMFRAMEH | STMPARITYH);
310 if (CharNStat & info->ignore_status_mask) {
314 CharNStat &= info->read_status_mask;
315 if (CharNStat & STMBREAKH)
317 else if (CharNStat & STMPARITYH)
318 *fbuf++ = TTY_PARITY;
319 else if (CharNStat & STMFRAMEH)
321 else if (CharNStat & STMRCVROVRH)
322 *fbuf++ = TTY_OVERRUN;
325 *cbuf++ = CharNStat & 0xff;
331 * after we've emptied the FIFO in status mode, turn
332 * status mode back off
334 if (sGetRxCnt(cp) == 0) {
335 #ifdef ROCKET_DEBUG_RECEIVE
336 printk(KERN_INFO "Status mode off.\n");
338 sDisRxStatusMode(cp);
342 * we aren't in status mode, so read down the FIFO two
343 * characters at time by doing repeated word IO
348 sInStrW(sGetTxRxDataIO(cp), (unsigned short *) cbuf, wRecv);
350 cbuf[ToRecv - 1] = sInB(sGetTxRxDataIO(cp));
351 memset(fbuf, 0, ToRecv);
356 /* Push the data up to the tty layer */
357 tty->ldisc.receive_buf(tty, tty->flip.char_buf, tty->flip.flag_buf, count);
361 * Serial port transmit data function. Called from the timer polling loop as a
362 * result of a bit set in xmit_flags[], indicating data (from the tty layer) is ready
363 * to be sent out the serial port. Data is buffered in rp_table[line].xmit_buf, it is
364 * moved to the port's xmit FIFO. *info is critical data, protected by spinlocks.
366 static void rp_do_transmit(struct r_port *info)
369 CHANNEL_t *cp = &info->channel;
370 struct tty_struct *tty;
373 #ifdef ROCKET_DEBUG_INTR
374 printk(KERN_INFO "rp_do_transmit ");
379 printk(KERN_INFO "rp: WARNING rp_do_transmit called with info->tty==NULL\n");
380 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
384 spin_lock_irqsave(&info->slock, flags);
386 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
388 /* Loop sending data to FIFO until done or FIFO full */
390 if (tty->stopped || tty->hw_stopped)
392 c = MIN(info->xmit_fifo_room, MIN(info->xmit_cnt, XMIT_BUF_SIZE - info->xmit_tail));
393 if (c <= 0 || info->xmit_fifo_room <= 0)
395 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) (info->xmit_buf + info->xmit_tail), c / 2);
397 sOutB(sGetTxRxDataIO(cp), info->xmit_buf[info->xmit_tail + c - 1]);
398 info->xmit_tail += c;
399 info->xmit_tail &= XMIT_BUF_SIZE - 1;
401 info->xmit_fifo_room -= c;
402 #ifdef ROCKET_DEBUG_INTR
403 printk(KERN_INFO "tx %d chars...", c);
407 if (info->xmit_cnt == 0)
408 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
410 if (info->xmit_cnt < WAKEUP_CHARS) {
411 if ((tty->flags & (1 << TTY_DO_WRITE_WAKEUP)) && tty->ldisc.write_wakeup)
412 (tty->ldisc.write_wakeup) (tty);
413 wake_up_interruptible(&tty->write_wait);
414 #ifdef ROCKETPORT_HAVE_POLL_WAIT
415 wake_up_interruptible(&tty->poll_wait);
419 spin_unlock_irqrestore(&info->slock, flags);
421 #ifdef ROCKET_DEBUG_INTR
422 printk(KERN_INFO "(%d,%d,%d,%d)...", info->xmit_cnt, info->xmit_head,
423 info->xmit_tail, info->xmit_fifo_room);
428 * Called when a serial port signals it has read data in it's RX FIFO.
429 * It checks what interrupts are pending and services them, including
430 * receiving serial data.
432 static void rp_handle_port(struct r_port *info)
435 struct tty_struct *tty;
436 unsigned int IntMask, ChanStatus;
441 if ((info->flags & ROCKET_INITIALIZED) == 0) {
442 printk(KERN_INFO "rp: WARNING: rp_handle_port called with info->flags & NOT_INIT\n");
446 printk(KERN_INFO "rp: WARNING: rp_handle_port called with info->tty==NULL\n");
452 IntMask = sGetChanIntID(cp) & info->intmask;
453 #ifdef ROCKET_DEBUG_INTR
454 printk(KERN_INFO "rp_interrupt %02x...", IntMask);
456 ChanStatus = sGetChanStatus(cp);
457 if (IntMask & RXF_TRIG) { /* Rx FIFO trigger level */
458 rp_do_receive(info, tty, cp, ChanStatus);
460 if (IntMask & DELTA_CD) { /* CD change */
461 #if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_INTR) || defined(ROCKET_DEBUG_HANGUP))
462 printk(KERN_INFO "ttyR%d CD now %s...", info->line,
463 (ChanStatus & CD_ACT) ? "on" : "off");
465 if (!(ChanStatus & CD_ACT) && info->cd_status) {
466 #ifdef ROCKET_DEBUG_HANGUP
467 printk(KERN_INFO "CD drop, calling hangup.\n");
471 info->cd_status = (ChanStatus & CD_ACT) ? 1 : 0;
472 wake_up_interruptible(&info->open_wait);
474 #ifdef ROCKET_DEBUG_INTR
475 if (IntMask & DELTA_CTS) { /* CTS change */
476 printk(KERN_INFO "CTS change...\n");
478 if (IntMask & DELTA_DSR) { /* DSR change */
479 printk(KERN_INFO "DSR change...\n");
485 * The top level polling routine. Repeats every 1/100 HZ (10ms).
487 static void rp_do_poll(unsigned long dummy)
490 int ctrl, aiop, ch, line, i;
491 unsigned int xmitmask;
492 unsigned int CtlMask;
493 unsigned char AiopMask;
496 /* Walk through all the boards (ctrl's) */
497 for (ctrl = 0; ctrl < max_board; ctrl++) {
498 if (rcktpt_io_addr[ctrl] <= 0)
501 /* Get a ptr to the board's control struct */
502 ctlp = sCtlNumToCtlPtr(ctrl);
504 /* Get the interupt status from the board */
506 if (ctlp->BusType == isPCI)
507 CtlMask = sPCIGetControllerIntStatus(ctlp);
510 CtlMask = sGetControllerIntStatus(ctlp);
512 /* Check if any AIOP read bits are set */
513 for (aiop = 0; CtlMask; aiop++) {
514 bit = ctlp->AiopIntrBits[aiop];
517 AiopMask = sGetAiopIntStatus(ctlp, aiop);
519 /* Check if any port read bits are set */
520 for (ch = 0; AiopMask; AiopMask >>= 1, ch++) {
523 /* Get the line number (/dev/ttyRx number). */
524 /* Read the data from the port. */
525 line = GetLineNumber(ctrl, aiop, ch);
526 rp_handle_port(rp_table[line]);
532 xmitmask = xmit_flags[ctrl];
535 * xmit_flags contains bit-significant flags, indicating there is data
536 * to xmit on the port. Bit 0 is port 0 on this board, bit 1 is port
537 * 1, ... (32 total possible). The variable i has the aiop and ch
538 * numbers encoded in it (port 0-7 are aiop0, 8-15 are aiop1, etc).
541 for (i = 0; i < rocketModel[ctrl].numPorts; i++) {
542 if (xmitmask & (1 << i)) {
543 aiop = (i & 0x18) >> 3;
545 line = GetLineNumber(ctrl, aiop, ch);
546 rp_do_transmit(rp_table[line]);
553 * Reset the timer so we get called at the next clock tick (10ms).
555 if (atomic_read(&rp_num_ports_open))
556 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
560 * Initializes the r_port structure for a port, as well as enabling the port on
562 * Inputs: board, aiop, chan numbers
564 static void init_r_port(int board, int aiop, int chan, struct pci_dev *pci_dev)
571 /* Get the next available line number */
572 line = SetLineNumber(board, aiop, chan);
574 ctlp = sCtlNumToCtlPtr(board);
576 /* Get a r_port struct for the port, fill it in and save it globally, indexed by line number */
577 info = kmalloc(sizeof (struct r_port), GFP_KERNEL);
579 printk(KERN_INFO "Couldn't allocate info struct for line #%d\n", line);
582 memset(info, 0, sizeof (struct r_port));
584 info->magic = RPORT_MAGIC;
590 info->closing_wait = 3000;
591 info->close_delay = 50;
592 init_waitqueue_head(&info->open_wait);
593 init_waitqueue_head(&info->close_wait);
594 info->flags &= ~ROCKET_MODE_MASK;
595 switch (pc104[board][line]) {
597 info->flags |= ROCKET_MODE_RS422;
600 info->flags |= ROCKET_MODE_RS485;
604 info->flags |= ROCKET_MODE_RS232;
608 info->intmask = RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR;
609 if (sInitChan(ctlp, &info->channel, aiop, chan) == 0) {
610 printk(KERN_INFO "RocketPort sInitChan(%d, %d, %d) failed!\n", board, aiop, chan);
615 rocketMode = info->flags & ROCKET_MODE_MASK;
617 if ((info->flags & ROCKET_RTS_TOGGLE) || (rocketMode == ROCKET_MODE_RS485))
618 sEnRTSToggle(&info->channel);
620 sDisRTSToggle(&info->channel);
622 if (ctlp->boardType == ROCKET_TYPE_PC104) {
623 switch (rocketMode) {
624 case ROCKET_MODE_RS485:
625 sSetInterfaceMode(&info->channel, InterfaceModeRS485);
627 case ROCKET_MODE_RS422:
628 sSetInterfaceMode(&info->channel, InterfaceModeRS422);
630 case ROCKET_MODE_RS232:
632 if (info->flags & ROCKET_RTS_TOGGLE)
633 sSetInterfaceMode(&info->channel, InterfaceModeRS232T);
635 sSetInterfaceMode(&info->channel, InterfaceModeRS232);
639 spin_lock_init(&info->slock);
640 sema_init(&info->write_sem, 1);
641 rp_table[line] = info;
643 tty_register_device(rocket_driver, line, &pci_dev->dev);
647 * Configures a rocketport port according to its termio settings. Called from
648 * user mode into the driver (exception handler). *info CD manipulation is spinlock protected.
650 static void configure_r_port(struct r_port *info,
651 struct termios *old_termios)
656 int bits, baud, divisor;
659 if (!info->tty || !info->tty->termios)
662 cflag = info->tty->termios->c_cflag;
664 /* Byte size and parity */
665 if ((cflag & CSIZE) == CS8) {
672 if (cflag & CSTOPB) {
679 if (cflag & PARENB) {
682 if (cflag & PARODD) {
692 baud = tty_get_baud_rate(info->tty);
695 divisor = ((rp_baud_base[info->board] + (baud >> 1)) / baud) - 1;
696 if ((divisor >= 8192 || divisor < 0) && old_termios) {
697 info->tty->termios->c_cflag &= ~CBAUD;
698 info->tty->termios->c_cflag |=
699 (old_termios->c_cflag & CBAUD);
700 baud = tty_get_baud_rate(info->tty);
703 divisor = (rp_baud_base[info->board] / baud) - 1;
705 if (divisor >= 8192 || divisor < 0) {
707 divisor = (rp_baud_base[info->board] / baud) - 1;
709 info->cps = baud / bits;
710 sSetBaud(cp, divisor);
712 if (cflag & CRTSCTS) {
713 info->intmask |= DELTA_CTS;
716 info->intmask &= ~DELTA_CTS;
719 if (cflag & CLOCAL) {
720 info->intmask &= ~DELTA_CD;
722 spin_lock_irqsave(&info->slock, flags);
723 if (sGetChanStatus(cp) & CD_ACT)
727 info->intmask |= DELTA_CD;
728 spin_unlock_irqrestore(&info->slock, flags);
732 * Handle software flow control in the board
734 #ifdef ROCKET_SOFT_FLOW
735 if (I_IXON(info->tty)) {
736 sEnTxSoftFlowCtl(cp);
737 if (I_IXANY(info->tty)) {
742 sSetTxXONChar(cp, START_CHAR(info->tty));
743 sSetTxXOFFChar(cp, STOP_CHAR(info->tty));
745 sDisTxSoftFlowCtl(cp);
752 * Set up ignore/read mask words
754 info->read_status_mask = STMRCVROVRH | 0xFF;
755 if (I_INPCK(info->tty))
756 info->read_status_mask |= STMFRAMEH | STMPARITYH;
757 if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
758 info->read_status_mask |= STMBREAKH;
761 * Characters to ignore
763 info->ignore_status_mask = 0;
764 if (I_IGNPAR(info->tty))
765 info->ignore_status_mask |= STMFRAMEH | STMPARITYH;
766 if (I_IGNBRK(info->tty)) {
767 info->ignore_status_mask |= STMBREAKH;
769 * If we're ignoring parity and break indicators,
770 * ignore overruns too. (For real raw support).
772 if (I_IGNPAR(info->tty))
773 info->ignore_status_mask |= STMRCVROVRH;
776 rocketMode = info->flags & ROCKET_MODE_MASK;
778 if ((info->flags & ROCKET_RTS_TOGGLE)
779 || (rocketMode == ROCKET_MODE_RS485))
784 sSetRTS(&info->channel);
786 if (cp->CtlP->boardType == ROCKET_TYPE_PC104) {
787 switch (rocketMode) {
788 case ROCKET_MODE_RS485:
789 sSetInterfaceMode(cp, InterfaceModeRS485);
791 case ROCKET_MODE_RS422:
792 sSetInterfaceMode(cp, InterfaceModeRS422);
794 case ROCKET_MODE_RS232:
796 if (info->flags & ROCKET_RTS_TOGGLE)
797 sSetInterfaceMode(cp, InterfaceModeRS232T);
799 sSetInterfaceMode(cp, InterfaceModeRS232);
805 /* info->count is considered critical, protected by spinlocks. */
806 static int block_til_ready(struct tty_struct *tty, struct file *filp,
809 DECLARE_WAITQUEUE(wait, current);
811 int do_clocal = 0, extra_count = 0;
815 * If the device is in the middle of being closed, then block
816 * until it's done, and then try again.
818 if (tty_hung_up_p(filp))
819 return ((info->flags & ROCKET_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS);
820 if (info->flags & ROCKET_CLOSING) {
821 interruptible_sleep_on(&info->close_wait);
822 return ((info->flags & ROCKET_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS);
826 * If non-blocking mode is set, or the port is not enabled,
827 * then make the check up front and then exit.
829 if ((filp->f_flags & O_NONBLOCK) || (tty->flags & (1 << TTY_IO_ERROR))) {
830 info->flags |= ROCKET_NORMAL_ACTIVE;
833 if (tty->termios->c_cflag & CLOCAL)
837 * Block waiting for the carrier detect and the line to become free. While we are in
838 * this loop, info->count is dropped by one, so that rp_close() knows when to free things.
839 * We restore it upon exit, either normal or abnormal.
842 add_wait_queue(&info->open_wait, &wait);
843 #ifdef ROCKET_DEBUG_OPEN
844 printk(KERN_INFO "block_til_ready before block: ttyR%d, count = %d\n", info->line, info->count);
846 spin_lock_irqsave(&info->slock, flags);
848 #ifdef ROCKET_DISABLE_SIMUSAGE
849 info->flags |= ROCKET_NORMAL_ACTIVE;
851 if (!tty_hung_up_p(filp)) {
856 info->blocked_open++;
858 spin_unlock_irqrestore(&info->slock, flags);
861 if (tty->termios->c_cflag & CBAUD) {
862 sSetDTR(&info->channel);
863 sSetRTS(&info->channel);
865 set_current_state(TASK_INTERRUPTIBLE);
866 if (tty_hung_up_p(filp) || !(info->flags & ROCKET_INITIALIZED)) {
867 if (info->flags & ROCKET_HUP_NOTIFY)
870 retval = -ERESTARTSYS;
873 if (!(info->flags & ROCKET_CLOSING) && (do_clocal || (sGetChanStatusLo(&info->channel) & CD_ACT)))
875 if (signal_pending(current)) {
876 retval = -ERESTARTSYS;
879 #ifdef ROCKET_DEBUG_OPEN
880 printk(KERN_INFO "block_til_ready blocking: ttyR%d, count = %d, flags=0x%0x\n",
881 info->line, info->count, info->flags);
883 schedule(); /* Don't hold spinlock here, will hang PC */
885 current->state = TASK_RUNNING;
886 remove_wait_queue(&info->open_wait, &wait);
888 spin_lock_irqsave(&info->slock, flags);
892 info->blocked_open--;
894 spin_unlock_irqrestore(&info->slock, flags);
896 #ifdef ROCKET_DEBUG_OPEN
897 printk(KERN_INFO "block_til_ready after blocking: ttyR%d, count = %d\n",
898 info->line, info->count);
902 info->flags |= ROCKET_NORMAL_ACTIVE;
907 * Exception handler that opens a serial port. Creates xmit_buf storage, fills in
908 * port's r_port struct. Initializes the port hardware.
910 static int rp_open(struct tty_struct *tty, struct file *filp)
913 int line = 0, retval;
917 line = TTY_GET_LINE(tty);
918 if ((line < 0) || (line >= MAX_RP_PORTS) || ((info = rp_table[line]) == NULL))
921 page = __get_free_page(GFP_KERNEL);
925 if (info->flags & ROCKET_CLOSING) {
926 interruptible_sleep_on(&info->close_wait);
928 return ((info->flags & ROCKET_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS);
932 * We must not sleep from here until the port is marked fully in use.
937 info->xmit_buf = (unsigned char *) page;
939 tty->driver_data = info;
942 if (info->count++ == 0) {
943 atomic_inc(&rp_num_ports_open);
945 #ifdef ROCKET_DEBUG_OPEN
946 printk(KERN_INFO "rocket mod++ = %d...", atomic_read(&rp_num_ports_open));
949 #ifdef ROCKET_DEBUG_OPEN
950 printk(KERN_INFO "rp_open ttyR%d, count=%d\n", info->line, info->count);
954 * Info->count is now 1; so it's safe to sleep now.
956 info->session = current->signal->session;
957 info->pgrp = process_group(current);
959 if ((info->flags & ROCKET_INITIALIZED) == 0) {
961 sSetRxTrigger(cp, TRIG_1);
962 if (sGetChanStatus(cp) & CD_ACT)
966 sDisRxStatusMode(cp);
970 sEnInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
971 sSetRxTrigger(cp, TRIG_1);
974 sDisRxStatusMode(cp);
978 sDisTxSoftFlowCtl(cp);
983 info->flags |= ROCKET_INITIALIZED;
986 * Set up the tty->alt_speed kludge
988 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI)
989 info->tty->alt_speed = 57600;
990 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI)
991 info->tty->alt_speed = 115200;
992 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI)
993 info->tty->alt_speed = 230400;
994 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP)
995 info->tty->alt_speed = 460800;
997 configure_r_port(info, NULL);
998 if (tty->termios->c_cflag & CBAUD) {
1003 /* Starts (or resets) the maint polling loop */
1004 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
1006 retval = block_til_ready(tty, filp, info);
1008 #ifdef ROCKET_DEBUG_OPEN
1009 printk(KERN_INFO "rp_open returning after block_til_ready with %d\n", retval);
1017 * Exception handler that closes a serial port. info->count is considered critical.
1019 static void rp_close(struct tty_struct *tty, struct file *filp)
1021 struct r_port *info = (struct r_port *) tty->driver_data;
1022 unsigned long flags;
1026 if (rocket_paranoia_check(info, "rp_close"))
1029 #ifdef ROCKET_DEBUG_OPEN
1030 printk(KERN_INFO "rp_close ttyR%d, count = %d\n", info->line, info->count);
1033 if (tty_hung_up_p(filp))
1035 spin_lock_irqsave(&info->slock, flags);
1037 if ((tty->count == 1) && (info->count != 1)) {
1039 * Uh, oh. tty->count is 1, which means that the tty
1040 * structure will be freed. Info->count should always
1041 * be one in these conditions. If it's greater than
1042 * one, we've got real problems, since it means the
1043 * serial port won't be shutdown.
1045 printk(KERN_INFO "rp_close: bad serial port count; tty->count is 1, "
1046 "info->count is %d\n", info->count);
1049 if (--info->count < 0) {
1050 printk(KERN_INFO "rp_close: bad serial port count for ttyR%d: %d\n",
1051 info->line, info->count);
1055 spin_unlock_irqrestore(&info->slock, flags);
1058 info->flags |= ROCKET_CLOSING;
1059 spin_unlock_irqrestore(&info->slock, flags);
1061 cp = &info->channel;
1064 * Notify the line discpline to only process XON/XOFF characters
1069 * If transmission was throttled by the application request,
1070 * just flush the xmit buffer.
1072 if (tty->flow_stopped)
1073 rp_flush_buffer(tty);
1076 * Wait for the transmit buffer to clear
1078 if (info->closing_wait != ROCKET_CLOSING_WAIT_NONE)
1079 tty_wait_until_sent(tty, info->closing_wait);
1081 * Before we drop DTR, make sure the UART transmitter
1082 * has completely drained; this is especially
1083 * important if there is a transmit FIFO!
1085 timeout = (sGetTxCnt(cp) + 1) * HZ / info->cps;
1088 rp_wait_until_sent(tty, timeout);
1089 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1092 sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1094 sDisTxSoftFlowCtl(cp);
1102 if (TTY_DRIVER_FLUSH_BUFFER_EXISTS(tty))
1103 TTY_DRIVER_FLUSH_BUFFER(tty);
1104 if (tty->ldisc.flush_buffer)
1105 tty->ldisc.flush_buffer(tty);
1107 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1109 if (info->blocked_open) {
1110 if (info->close_delay) {
1111 current->state = TASK_INTERRUPTIBLE;
1112 schedule_timeout(info->close_delay);
1114 wake_up_interruptible(&info->open_wait);
1116 if (info->xmit_buf) {
1117 free_page((unsigned long) info->xmit_buf);
1121 info->flags &= ~(ROCKET_INITIALIZED | ROCKET_CLOSING | ROCKET_NORMAL_ACTIVE);
1123 wake_up_interruptible(&info->close_wait);
1124 atomic_dec(&rp_num_ports_open);
1126 #ifdef ROCKET_DEBUG_OPEN
1127 printk(KERN_INFO "rocket mod-- = %d...", atomic_read(&rp_num_ports_open));
1128 printk(KERN_INFO "rp_close ttyR%d complete shutdown\n", info->line);
1133 static void rp_set_termios(struct tty_struct *tty,
1134 struct termios *old_termios)
1136 struct r_port *info = (struct r_port *) tty->driver_data;
1140 if (rocket_paranoia_check(info, "rp_set_termios"))
1143 cflag = tty->termios->c_cflag;
1145 if (cflag == old_termios->c_cflag)
1149 * This driver doesn't support CS5 or CS6
1151 if (((cflag & CSIZE) == CS5) || ((cflag & CSIZE) == CS6))
1152 tty->termios->c_cflag =
1153 ((cflag & ~CSIZE) | (old_termios->c_cflag & CSIZE));
1155 configure_r_port(info, old_termios);
1157 cp = &info->channel;
1159 /* Handle transition to B0 status */
1160 if ((old_termios->c_cflag & CBAUD) && !(tty->termios->c_cflag & CBAUD)) {
1165 /* Handle transition away from B0 status */
1166 if (!(old_termios->c_cflag & CBAUD) && (tty->termios->c_cflag & CBAUD)) {
1167 if (!tty->hw_stopped || !(tty->termios->c_cflag & CRTSCTS))
1172 if ((old_termios->c_cflag & CRTSCTS) && !(tty->termios->c_cflag & CRTSCTS)) {
1173 tty->hw_stopped = 0;
1178 static void rp_break(struct tty_struct *tty, int break_state)
1180 struct r_port *info = (struct r_port *) tty->driver_data;
1181 unsigned long flags;
1183 if (rocket_paranoia_check(info, "rp_break"))
1186 spin_lock_irqsave(&info->slock, flags);
1187 if (break_state == -1)
1188 sSendBreak(&info->channel);
1190 sClrBreak(&info->channel);
1191 spin_unlock_irqrestore(&info->slock, flags);
1195 * sGetChanRI used to be a macro in rocket_int.h. When the functionality for
1196 * the UPCI boards was added, it was decided to make this a function because
1197 * the macro was getting too complicated. All cases except the first one
1198 * (UPCIRingInd) are taken directly from the original macro.
1200 static int sGetChanRI(CHANNEL_T * ChP)
1202 CONTROLLER_t *CtlP = ChP->CtlP;
1203 int ChanNum = ChP->ChanNum;
1206 if (CtlP->UPCIRingInd)
1207 RingInd = !(sInB(CtlP->UPCIRingInd) & sBitMapSetTbl[ChanNum]);
1208 else if (CtlP->AltChanRingIndicator)
1209 RingInd = sInB((ByteIO_t) (ChP->ChanStat + 8)) & DSR_ACT;
1210 else if (CtlP->boardType == ROCKET_TYPE_PC104)
1211 RingInd = !(sInB(CtlP->AiopIO[3]) & sBitMapSetTbl[ChanNum]);
1216 /********************************************************************************************/
1217 /* Here are the routines used by rp_ioctl. These are all called from exception handlers. */
1220 * Returns the state of the serial modem control lines. These next 2 functions
1221 * are the way kernel versions > 2.5 handle modem control lines rather than IOCTLs.
1223 static int rp_tiocmget(struct tty_struct *tty, struct file *file)
1225 struct r_port *info = (struct r_port *)tty->driver_data;
1226 unsigned int control, result, ChanStatus;
1228 ChanStatus = sGetChanStatusLo(&info->channel);
1229 control = info->channel.TxControl[3];
1230 result = ((control & SET_RTS) ? TIOCM_RTS : 0) |
1231 ((control & SET_DTR) ? TIOCM_DTR : 0) |
1232 ((ChanStatus & CD_ACT) ? TIOCM_CAR : 0) |
1233 (sGetChanRI(&info->channel) ? TIOCM_RNG : 0) |
1234 ((ChanStatus & DSR_ACT) ? TIOCM_DSR : 0) |
1235 ((ChanStatus & CTS_ACT) ? TIOCM_CTS : 0);
1241 * Sets the modem control lines
1243 static int rp_tiocmset(struct tty_struct *tty, struct file *file,
1244 unsigned int set, unsigned int clear)
1246 struct r_port *info = (struct r_port *)tty->driver_data;
1248 if (set & TIOCM_RTS)
1249 info->channel.TxControl[3] |= SET_RTS;
1250 if (set & TIOCM_DTR)
1251 info->channel.TxControl[3] |= SET_DTR;
1252 if (clear & TIOCM_RTS)
1253 info->channel.TxControl[3] &= ~SET_RTS;
1254 if (clear & TIOCM_DTR)
1255 info->channel.TxControl[3] &= ~SET_DTR;
1257 sOutDW(info->channel.IndexAddr, *(DWord_t *) & (info->channel.TxControl[0]));
1261 static int get_config(struct r_port *info, struct rocket_config *retinfo)
1263 struct rocket_config tmp;
1267 memset(&tmp, 0, sizeof (tmp));
1268 tmp.line = info->line;
1269 tmp.flags = info->flags;
1270 tmp.close_delay = info->close_delay;
1271 tmp.closing_wait = info->closing_wait;
1272 tmp.port = rcktpt_io_addr[(info->line >> 5) & 3];
1274 if (copy_to_user(retinfo, &tmp, sizeof (*retinfo)))
1279 static int set_config(struct r_port *info, struct rocket_config *new_info)
1281 struct rocket_config new_serial;
1283 if (copy_from_user(&new_serial, new_info, sizeof (new_serial)))
1286 #ifdef CAP_SYS_ADMIN
1287 if (!capable(CAP_SYS_ADMIN))
1292 if ((new_serial.flags & ~ROCKET_USR_MASK) != (info->flags & ~ROCKET_USR_MASK))
1294 info->flags = ((info->flags & ~ROCKET_USR_MASK) | (new_serial.flags & ROCKET_USR_MASK));
1295 configure_r_port(info, 0);
1299 info->flags = ((info->flags & ~ROCKET_FLAGS) | (new_serial.flags & ROCKET_FLAGS));
1300 info->close_delay = new_serial.close_delay;
1301 info->closing_wait = new_serial.closing_wait;
1303 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI)
1304 info->tty->alt_speed = 57600;
1305 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI)
1306 info->tty->alt_speed = 115200;
1307 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI)
1308 info->tty->alt_speed = 230400;
1309 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP)
1310 info->tty->alt_speed = 460800;
1312 configure_r_port(info, 0);
1317 * This function fills in a rocket_ports struct with information
1318 * about what boards/ports are in the system. This info is passed
1319 * to user space. See setrocket.c where the info is used to create
1320 * the /dev/ttyRx ports.
1322 static int get_ports(struct r_port *info, struct rocket_ports *retports)
1324 struct rocket_ports tmp;
1329 memset(&tmp, 0, sizeof (tmp));
1330 tmp.tty_major = rocket_driver->major;
1332 for (board = 0; board < 4; board++) {
1333 tmp.rocketModel[board].model = rocketModel[board].model;
1334 strcpy(tmp.rocketModel[board].modelString, rocketModel[board].modelString);
1335 tmp.rocketModel[board].numPorts = rocketModel[board].numPorts;
1336 tmp.rocketModel[board].loadrm2 = rocketModel[board].loadrm2;
1337 tmp.rocketModel[board].startingPortNumber = rocketModel[board].startingPortNumber;
1339 if (copy_to_user(retports, &tmp, sizeof (*retports)))
1344 static int reset_rm2(struct r_port *info, unsigned long arg)
1348 if (copy_from_user(&reset, (void *) arg, sizeof (int)))
1353 if (rcktpt_type[info->board] != ROCKET_TYPE_MODEMII &&
1354 rcktpt_type[info->board] != ROCKET_TYPE_MODEMIII)
1357 if (info->ctlp->BusType == isISA)
1358 sModemReset(info->ctlp, info->chan, reset);
1360 sPCIModemReset(info->ctlp, info->chan, reset);
1365 static int get_version(struct r_port *info, struct rocket_version *retvers)
1367 if (copy_to_user(retvers, &driver_version, sizeof (*retvers)))
1372 /* IOCTL call handler into the driver */
1373 static int rp_ioctl(struct tty_struct *tty, struct file *file,
1374 unsigned int cmd, unsigned long arg)
1376 struct r_port *info = (struct r_port *) tty->driver_data;
1378 if (cmd != RCKP_GET_PORTS && rocket_paranoia_check(info, "rp_ioctl"))
1382 case RCKP_GET_STRUCT:
1383 if (copy_to_user((void *) arg, info, sizeof (struct r_port)))
1386 case RCKP_GET_CONFIG:
1387 return get_config(info, (struct rocket_config *) arg);
1388 case RCKP_SET_CONFIG:
1389 return set_config(info, (struct rocket_config *) arg);
1390 case RCKP_GET_PORTS:
1391 return get_ports(info, (struct rocket_ports *) arg);
1392 case RCKP_RESET_RM2:
1393 return reset_rm2(info, arg);
1394 case RCKP_GET_VERSION:
1395 return get_version(info, (struct rocket_version *) arg);
1397 return -ENOIOCTLCMD;
1402 static void rp_send_xchar(struct tty_struct *tty, char ch)
1404 struct r_port *info = (struct r_port *) tty->driver_data;
1407 if (rocket_paranoia_check(info, "rp_send_xchar"))
1410 cp = &info->channel;
1412 sWriteTxPrioByte(cp, ch);
1414 sWriteTxByte(sGetTxRxDataIO(cp), ch);
1417 static void rp_throttle(struct tty_struct *tty)
1419 struct r_port *info = (struct r_port *) tty->driver_data;
1422 #ifdef ROCKET_DEBUG_THROTTLE
1423 printk(KERN_INFO "throttle %s: %d....\n", tty->name,
1424 tty->ldisc.chars_in_buffer(tty));
1427 if (rocket_paranoia_check(info, "rp_throttle"))
1430 cp = &info->channel;
1432 rp_send_xchar(tty, STOP_CHAR(tty));
1434 sClrRTS(&info->channel);
1437 static void rp_unthrottle(struct tty_struct *tty)
1439 struct r_port *info = (struct r_port *) tty->driver_data;
1441 #ifdef ROCKET_DEBUG_THROTTLE
1442 printk(KERN_INFO "unthrottle %s: %d....\n", tty->name,
1443 tty->ldisc.chars_in_buffer(tty));
1446 if (rocket_paranoia_check(info, "rp_throttle"))
1449 cp = &info->channel;
1451 rp_send_xchar(tty, START_CHAR(tty));
1453 sSetRTS(&info->channel);
1457 * ------------------------------------------------------------
1458 * rp_stop() and rp_start()
1460 * This routines are called before setting or resetting tty->stopped.
1461 * They enable or disable transmitter interrupts, as necessary.
1462 * ------------------------------------------------------------
1464 static void rp_stop(struct tty_struct *tty)
1466 struct r_port *info = (struct r_port *) tty->driver_data;
1468 #ifdef ROCKET_DEBUG_FLOW
1469 printk(KERN_INFO "stop %s: %d %d....\n", tty->name,
1470 info->xmit_cnt, info->xmit_fifo_room);
1473 if (rocket_paranoia_check(info, "rp_stop"))
1476 if (sGetTxCnt(&info->channel))
1477 sDisTransmit(&info->channel);
1480 static void rp_start(struct tty_struct *tty)
1482 struct r_port *info = (struct r_port *) tty->driver_data;
1484 #ifdef ROCKET_DEBUG_FLOW
1485 printk(KERN_INFO "start %s: %d %d....\n", tty->name,
1486 info->xmit_cnt, info->xmit_fifo_room);
1489 if (rocket_paranoia_check(info, "rp_stop"))
1492 sEnTransmit(&info->channel);
1493 set_bit((info->aiop * 8) + info->chan,
1494 (void *) &xmit_flags[info->board]);
1498 * rp_wait_until_sent() --- wait until the transmitter is empty
1500 static void rp_wait_until_sent(struct tty_struct *tty, int timeout)
1502 struct r_port *info = (struct r_port *) tty->driver_data;
1504 unsigned long orig_jiffies;
1505 int check_time, exit_time;
1508 if (rocket_paranoia_check(info, "rp_wait_until_sent"))
1511 cp = &info->channel;
1513 orig_jiffies = jiffies;
1514 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1515 printk(KERN_INFO "In RP_wait_until_sent(%d) (jiff=%lu)...", timeout,
1517 printk(KERN_INFO "cps=%d...", info->cps);
1520 txcnt = sGetTxCnt(cp);
1522 if (sGetChanStatusLo(cp) & TXSHRMT)
1524 check_time = (HZ / info->cps) / 5;
1526 check_time = HZ * txcnt / info->cps;
1529 exit_time = orig_jiffies + timeout - jiffies;
1532 if (exit_time < check_time)
1533 check_time = exit_time;
1535 if (check_time == 0)
1537 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1538 printk(KERN_INFO "txcnt = %d (jiff=%lu,check=%d)...", txcnt, jiffies, check_time);
1540 current->state = TASK_INTERRUPTIBLE;
1541 schedule_timeout(check_time);
1542 if (signal_pending(current))
1545 current->state = TASK_RUNNING;
1546 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1547 printk(KERN_INFO "txcnt = %d (jiff=%lu)...done\n", txcnt, jiffies);
1552 * rp_hangup() --- called by tty_hangup() when a hangup is signaled.
1554 static void rp_hangup(struct tty_struct *tty)
1557 struct r_port *info = (struct r_port *) tty->driver_data;
1559 if (rocket_paranoia_check(info, "rp_hangup"))
1562 #if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_HANGUP))
1563 printk(KERN_INFO "rp_hangup of ttyR%d...", info->line);
1565 rp_flush_buffer(tty);
1566 if (info->flags & ROCKET_CLOSING)
1569 atomic_dec(&rp_num_ports_open);
1570 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1573 info->flags &= ~ROCKET_NORMAL_ACTIVE;
1576 cp = &info->channel;
1579 sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1581 sDisTxSoftFlowCtl(cp);
1583 info->flags &= ~ROCKET_INITIALIZED;
1585 wake_up_interruptible(&info->open_wait);
1589 * Exception handler - write char routine. The RocketPort driver uses a
1590 * double-buffering strategy, with the twist that if the in-memory CPU
1591 * buffer is empty, and there's space in the transmit FIFO, the
1592 * writing routines will write directly to transmit FIFO.
1593 * Write buffer and counters protected by spinlocks
1595 static void rp_put_char(struct tty_struct *tty, unsigned char ch)
1597 struct r_port *info = (struct r_port *) tty->driver_data;
1599 unsigned long flags;
1601 if (rocket_paranoia_check(info, "rp_put_char"))
1604 /* Grab the port write semaphore, locking out other processes that try to write to this port */
1605 down(&info->write_sem);
1607 #ifdef ROCKET_DEBUG_WRITE
1608 printk(KERN_INFO "rp_put_char %c...", ch);
1611 spin_lock_irqsave(&info->slock, flags);
1612 cp = &info->channel;
1614 if (!tty->stopped && !tty->hw_stopped && info->xmit_fifo_room == 0)
1615 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1617 if (tty->stopped || tty->hw_stopped || info->xmit_fifo_room == 0 || info->xmit_cnt != 0) {
1618 info->xmit_buf[info->xmit_head++] = ch;
1619 info->xmit_head &= XMIT_BUF_SIZE - 1;
1621 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1623 sOutB(sGetTxRxDataIO(cp), ch);
1624 info->xmit_fifo_room--;
1626 spin_unlock_irqrestore(&info->slock, flags);
1627 up(&info->write_sem);
1631 * Exception handler - write routine, called when user app writes to the device.
1632 * A per port write semaphore is used to protect from another process writing to
1633 * this port at the same time. This other process could be running on the other CPU
1634 * or get control of the CPU if the copy_from_user() blocks due to a page fault (swapped out).
1635 * Spinlocks protect the info xmit members.
1637 static int rp_write(struct tty_struct *tty, int from_user,
1638 const unsigned char *buf, int count)
1640 struct r_port *info = (struct r_port *) tty->driver_data;
1642 const unsigned char *b;
1644 unsigned long flags;
1646 if (count <= 0 || rocket_paranoia_check(info, "rp_write"))
1649 down_interruptible(&info->write_sem);
1651 #ifdef ROCKET_DEBUG_WRITE
1652 printk(KERN_INFO "rp_write %d chars...", count);
1654 cp = &info->channel;
1656 if (!tty->stopped && !tty->hw_stopped && info->xmit_fifo_room < count)
1657 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1660 * If the write queue for the port is empty, and there is FIFO space, stuff bytes
1661 * into FIFO. Use the write queue for temp storage.
1663 if (!tty->stopped && !tty->hw_stopped && info->xmit_cnt == 0 && info->xmit_fifo_room > 0) {
1664 c = MIN(count, info->xmit_fifo_room);
1667 if (copy_from_user(info->xmit_buf, buf, c)) {
1674 c = MIN(c, info->xmit_fifo_room);
1677 /* Push data into FIFO, 2 bytes at a time */
1678 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) b, c / 2);
1680 /* If there is a byte remaining, write it */
1682 sOutB(sGetTxRxDataIO(cp), b[c - 1]);
1688 spin_lock_irqsave(&info->slock, flags);
1689 info->xmit_fifo_room -= c;
1690 spin_unlock_irqrestore(&info->slock, flags);
1693 /* If count is zero, we wrote it all and are done */
1697 /* Write remaining data into the port's xmit_buf */
1699 if (info->tty == 0) /* Seemingly obligatory check... */
1702 c = MIN(count, MIN(XMIT_BUF_SIZE - info->xmit_cnt - 1, XMIT_BUF_SIZE - info->xmit_head));
1708 if (copy_from_user(info->xmit_buf + info->xmit_head, b, c)) {
1712 memcpy(info->xmit_buf + info->xmit_head, b, c);
1716 spin_lock_irqsave(&info->slock, flags);
1718 (info->xmit_head + c) & (XMIT_BUF_SIZE - 1);
1719 info->xmit_cnt += c;
1720 spin_unlock_irqrestore(&info->slock, flags);
1728 if ((retval > 0) && !tty->stopped && !tty->hw_stopped)
1729 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1732 if (info->xmit_cnt < WAKEUP_CHARS) {
1733 if ((tty->flags & (1 << TTY_DO_WRITE_WAKEUP)) && tty->ldisc.write_wakeup)
1734 (tty->ldisc.write_wakeup) (tty);
1735 wake_up_interruptible(&tty->write_wait);
1736 #ifdef ROCKETPORT_HAVE_POLL_WAIT
1737 wake_up_interruptible(&tty->poll_wait);
1740 up(&info->write_sem);
1745 * Return the number of characters that can be sent. We estimate
1746 * only using the in-memory transmit buffer only, and ignore the
1747 * potential space in the transmit FIFO.
1749 static int rp_write_room(struct tty_struct *tty)
1751 struct r_port *info = (struct r_port *) tty->driver_data;
1754 if (rocket_paranoia_check(info, "rp_write_room"))
1757 ret = XMIT_BUF_SIZE - info->xmit_cnt - 1;
1760 #ifdef ROCKET_DEBUG_WRITE
1761 printk(KERN_INFO "rp_write_room returns %d...", ret);
1767 * Return the number of characters in the buffer. Again, this only
1768 * counts those characters in the in-memory transmit buffer.
1770 static int rp_chars_in_buffer(struct tty_struct *tty)
1772 struct r_port *info = (struct r_port *) tty->driver_data;
1775 if (rocket_paranoia_check(info, "rp_chars_in_buffer"))
1778 cp = &info->channel;
1780 #ifdef ROCKET_DEBUG_WRITE
1781 printk(KERN_INFO "rp_chars_in_buffer returns %d...", info->xmit_cnt);
1783 return info->xmit_cnt;
1787 * Flushes the TX fifo for a port, deletes data in the xmit_buf stored in the
1788 * r_port struct for the port. Note that spinlock are used to protect info members,
1789 * do not call this function if the spinlock is already held.
1791 static void rp_flush_buffer(struct tty_struct *tty)
1793 struct r_port *info = (struct r_port *) tty->driver_data;
1795 unsigned long flags;
1797 if (rocket_paranoia_check(info, "rp_flush_buffer"))
1800 spin_lock_irqsave(&info->slock, flags);
1801 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1802 spin_unlock_irqrestore(&info->slock, flags);
1804 wake_up_interruptible(&tty->write_wait);
1805 #ifdef ROCKETPORT_HAVE_POLL_WAIT
1806 wake_up_interruptible(&tty->poll_wait);
1808 if ((tty->flags & (1 << TTY_DO_WRITE_WAKEUP)) && tty->ldisc.write_wakeup)
1809 (tty->ldisc.write_wakeup) (tty);
1811 cp = &info->channel;
1818 * Called when a PCI card is found. Retrieves and stores model information,
1819 * init's aiopic and serial port hardware.
1820 * Inputs: i is the board number (0-n)
1822 __init int register_PCI(int i, struct pci_dev *dev)
1824 int num_aiops, aiop, max_num_aiops, num_chan, chan;
1825 unsigned int aiopio[MAX_AIOPS_PER_BOARD];
1826 char *str, *board_type;
1830 int altChanRingIndicator = 0;
1831 int ports_per_aiop = 8;
1833 unsigned int class_rev;
1834 WordIO_t ConfigIO = 0;
1835 ByteIO_t UPCIRingInd = 0;
1837 if (!dev || pci_enable_device(dev))
1840 rcktpt_io_addr[i] = pci_resource_start(dev, 0);
1841 ret = pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
1844 printk(KERN_INFO " Error during register_PCI(), unable to read config dword \n");
1848 rcktpt_type[i] = ROCKET_TYPE_NORMAL;
1849 rocketModel[i].loadrm2 = 0;
1850 rocketModel[i].startingPortNumber = nextLineNumber;
1852 /* Depending on the model, set up some config variables */
1853 switch (dev->device) {
1854 case PCI_DEVICE_ID_RP4QUAD:
1858 rocketModel[i].model = MODEL_RP4QUAD;
1859 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/quad cable");
1860 rocketModel[i].numPorts = 4;
1862 case PCI_DEVICE_ID_RP8OCTA:
1865 rocketModel[i].model = MODEL_RP8OCTA;
1866 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/octa cable");
1867 rocketModel[i].numPorts = 8;
1869 case PCI_DEVICE_ID_URP8OCTA:
1872 rocketModel[i].model = MODEL_UPCI_RP8OCTA;
1873 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/octa cable");
1874 rocketModel[i].numPorts = 8;
1876 case PCI_DEVICE_ID_RP8INTF:
1879 rocketModel[i].model = MODEL_RP8INTF;
1880 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/external I/F");
1881 rocketModel[i].numPorts = 8;
1883 case PCI_DEVICE_ID_URP8INTF:
1886 rocketModel[i].model = MODEL_UPCI_RP8INTF;
1887 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/external I/F");
1888 rocketModel[i].numPorts = 8;
1890 case PCI_DEVICE_ID_RP8J:
1893 rocketModel[i].model = MODEL_RP8J;
1894 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/RJ11 connectors");
1895 rocketModel[i].numPorts = 8;
1897 case PCI_DEVICE_ID_RP4J:
1901 rocketModel[i].model = MODEL_RP4J;
1902 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/RJ45 connectors");
1903 rocketModel[i].numPorts = 4;
1905 case PCI_DEVICE_ID_RP8SNI:
1906 str = "8 (DB78 Custom)";
1908 rocketModel[i].model = MODEL_RP8SNI;
1909 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/ custom DB78");
1910 rocketModel[i].numPorts = 8;
1912 case PCI_DEVICE_ID_RP16SNI:
1913 str = "16 (DB78 Custom)";
1915 rocketModel[i].model = MODEL_RP16SNI;
1916 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/ custom DB78");
1917 rocketModel[i].numPorts = 16;
1919 case PCI_DEVICE_ID_RP16INTF:
1922 rocketModel[i].model = MODEL_RP16INTF;
1923 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/external I/F");
1924 rocketModel[i].numPorts = 16;
1926 case PCI_DEVICE_ID_URP16INTF:
1929 rocketModel[i].model = MODEL_UPCI_RP16INTF;
1930 strcpy(rocketModel[i].modelString, "RocketPort UPCI 16 port w/external I/F");
1931 rocketModel[i].numPorts = 16;
1933 case PCI_DEVICE_ID_CRP16INTF:
1936 rocketModel[i].model = MODEL_CPCI_RP16INTF;
1937 strcpy(rocketModel[i].modelString, "RocketPort Compact PCI 16 port w/external I/F");
1938 rocketModel[i].numPorts = 16;
1940 case PCI_DEVICE_ID_RP32INTF:
1943 rocketModel[i].model = MODEL_RP32INTF;
1944 strcpy(rocketModel[i].modelString, "RocketPort 32 port w/external I/F");
1945 rocketModel[i].numPorts = 32;
1947 case PCI_DEVICE_ID_URP32INTF:
1950 rocketModel[i].model = MODEL_UPCI_RP32INTF;
1951 strcpy(rocketModel[i].modelString, "RocketPort UPCI 32 port w/external I/F");
1952 rocketModel[i].numPorts = 32;
1954 case PCI_DEVICE_ID_RPP4:
1955 str = "Plus Quadcable";
1958 altChanRingIndicator++;
1960 rocketModel[i].model = MODEL_RPP4;
1961 strcpy(rocketModel[i].modelString, "RocketPort Plus 4 port");
1962 rocketModel[i].numPorts = 4;
1964 case PCI_DEVICE_ID_RPP8:
1965 str = "Plus Octacable";
1968 altChanRingIndicator++;
1970 rocketModel[i].model = MODEL_RPP8;
1971 strcpy(rocketModel[i].modelString, "RocketPort Plus 8 port");
1972 rocketModel[i].numPorts = 8;
1974 case PCI_DEVICE_ID_RP2_232:
1975 str = "Plus 2 (RS-232)";
1978 altChanRingIndicator++;
1980 rocketModel[i].model = MODEL_RP2_232;
1981 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS232");
1982 rocketModel[i].numPorts = 2;
1984 case PCI_DEVICE_ID_RP2_422:
1985 str = "Plus 2 (RS-422)";
1988 altChanRingIndicator++;
1990 rocketModel[i].model = MODEL_RP2_422;
1991 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS422");
1992 rocketModel[i].numPorts = 2;
1994 case PCI_DEVICE_ID_RP6M:
2000 /* If class_rev is 1, the rocketmodem flash must be loaded. If it is 2 it is a "socketed" version. */
2001 if ((class_rev & 0xFF) == 1) {
2002 rcktpt_type[i] = ROCKET_TYPE_MODEMII;
2003 rocketModel[i].loadrm2 = 1;
2005 rcktpt_type[i] = ROCKET_TYPE_MODEM;
2008 rocketModel[i].model = MODEL_RP6M;
2009 strcpy(rocketModel[i].modelString, "RocketModem 6 port");
2010 rocketModel[i].numPorts = 6;
2012 case PCI_DEVICE_ID_RP4M:
2016 if ((class_rev & 0xFF) == 1) {
2017 rcktpt_type[i] = ROCKET_TYPE_MODEMII;
2018 rocketModel[i].loadrm2 = 1;
2020 rcktpt_type[i] = ROCKET_TYPE_MODEM;
2023 rocketModel[i].model = MODEL_RP4M;
2024 strcpy(rocketModel[i].modelString, "RocketModem 4 port");
2025 rocketModel[i].numPorts = 4;
2028 str = "(unknown/unsupported)";
2034 * Check for UPCI boards.
2037 switch (dev->device) {
2038 case PCI_DEVICE_ID_URP32INTF:
2039 case PCI_DEVICE_ID_URP8INTF:
2040 case PCI_DEVICE_ID_URP16INTF:
2041 case PCI_DEVICE_ID_CRP16INTF:
2042 case PCI_DEVICE_ID_URP8OCTA:
2043 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2044 ConfigIO = pci_resource_start(dev, 1);
2045 if (dev->device == PCI_DEVICE_ID_URP8OCTA) {
2046 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2049 * Check for octa or quad cable.
2052 (sInW(ConfigIO + _PCI_9030_GPIO_CTRL) &
2053 PCI_GPIO_CTRL_8PORT)) {
2056 rocketModel[i].numPorts = 4;
2060 case PCI_DEVICE_ID_UPCI_RM3_8PORT:
2063 rocketModel[i].model = MODEL_UPCI_RM3_8PORT;
2064 strcpy(rocketModel[i].modelString, "RocketModem III 8 port");
2065 rocketModel[i].numPorts = 8;
2066 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2067 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2068 ConfigIO = pci_resource_start(dev, 1);
2069 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2071 case PCI_DEVICE_ID_UPCI_RM3_4PORT:
2074 rocketModel[i].model = MODEL_UPCI_RM3_4PORT;
2075 strcpy(rocketModel[i].modelString, "RocketModem III 4 port");
2076 rocketModel[i].numPorts = 4;
2077 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2078 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2079 ConfigIO = pci_resource_start(dev, 1);
2080 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2086 switch (rcktpt_type[i]) {
2087 case ROCKET_TYPE_MODEM:
2088 board_type = "RocketModem";
2090 case ROCKET_TYPE_MODEMII:
2091 board_type = "RocketModem II";
2093 case ROCKET_TYPE_MODEMIII:
2094 board_type = "RocketModem III";
2097 board_type = "RocketPort";
2102 sClockPrescale = 0x12; /* mod 2 (divide by 3) */
2103 rp_baud_base[i] = 921600;
2106 * If support_low_speed is set, use the slow clock
2107 * prescale, which supports 50 bps
2109 if (support_low_speed) {
2110 /* mod 9 (divide by 10) prescale */
2111 sClockPrescale = 0x19;
2112 rp_baud_base[i] = 230400;
2114 /* mod 4 (devide by 5) prescale */
2115 sClockPrescale = 0x14;
2116 rp_baud_base[i] = 460800;
2120 for (aiop = 0; aiop < max_num_aiops; aiop++)
2121 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x40);
2122 ctlp = sCtlNumToCtlPtr(i);
2123 num_aiops = sPCIInitController(ctlp, i, aiopio, max_num_aiops, ConfigIO, 0, FREQ_DIS, 0, altChanRingIndicator, UPCIRingInd);
2124 for (aiop = 0; aiop < max_num_aiops; aiop++)
2125 ctlp->AiopNumChan[aiop] = ports_per_aiop;
2127 printk("Comtrol PCI controller #%d ID 0x%x found in bus:slot:fn %s at address %04lx, "
2128 "%d AIOP(s) (%s)\n", i, dev->device, pci_name(dev),
2129 rcktpt_io_addr[i], num_aiops, rocketModel[i].modelString);
2130 printk(KERN_INFO "Installing %s, creating /dev/ttyR%d - %ld\n",
2131 rocketModel[i].modelString,
2132 rocketModel[i].startingPortNumber,
2133 rocketModel[i].startingPortNumber +
2134 rocketModel[i].numPorts - 1);
2136 if (num_aiops <= 0) {
2137 rcktpt_io_addr[i] = 0;
2142 /* Reset the AIOPIC, init the serial ports */
2143 for (aiop = 0; aiop < num_aiops; aiop++) {
2144 sResetAiopByNum(ctlp, aiop);
2145 num_chan = ports_per_aiop;
2146 for (chan = 0; chan < num_chan; chan++)
2147 init_r_port(i, aiop, chan, dev);
2150 /* Rocket modems must be reset */
2151 if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) ||
2152 (rcktpt_type[i] == ROCKET_TYPE_MODEMII) ||
2153 (rcktpt_type[i] == ROCKET_TYPE_MODEMIII)) {
2154 num_chan = ports_per_aiop;
2155 for (chan = 0; chan < num_chan; chan++)
2156 sPCIModemReset(ctlp, chan, 1);
2158 for (chan = 0; chan < num_chan; chan++)
2159 sPCIModemReset(ctlp, chan, 0);
2161 rmSpeakerReset(ctlp, rocketModel[i].model);
2167 * Probes for PCI cards, inits them if found
2168 * Input: board_found = number of ISA boards already found, or the
2169 * starting board number
2170 * Returns: Number of PCI boards found
2172 static int __init init_PCI(int boards_found)
2174 struct pci_dev *dev = NULL;
2177 /* Work through the PCI device list, pulling out ours */
2178 while ((dev = pci_find_device(PCI_VENDOR_ID_RP, PCI_ANY_ID, dev))) {
2179 if (register_PCI(count + boards_found, dev))
2185 #endif /* CONFIG_PCI */
2188 * Probes for ISA cards
2189 * Input: i = the board number to look for
2190 * Returns: 1 if board found, 0 else
2192 static int __init init_ISA(int i)
2194 int num_aiops, num_chan = 0, total_num_chan = 0;
2196 unsigned int aiopio[MAX_AIOPS_PER_BOARD];
2200 /* If io_addr is zero, no board configured */
2201 if (rcktpt_io_addr[i] == 0)
2204 /* Reserve the IO region */
2205 if (!request_region(rcktpt_io_addr[i], 64, "Comtrol RocketPort")) {
2206 printk(KERN_INFO "Unable to reserve IO region for configured ISA RocketPort at address 0x%lx, board not installed...\n", rcktpt_io_addr[i]);
2207 rcktpt_io_addr[i] = 0;
2211 ctlp = sCtlNumToCtlPtr(i);
2213 ctlp->boardType = rcktpt_type[i];
2215 switch (rcktpt_type[i]) {
2216 case ROCKET_TYPE_PC104:
2217 type_string = "(PC104)";
2219 case ROCKET_TYPE_MODEM:
2220 type_string = "(RocketModem)";
2222 case ROCKET_TYPE_MODEMII:
2223 type_string = "(RocketModem II)";
2231 * If support_low_speed is set, use the slow clock prescale,
2232 * which supports 50 bps
2234 if (support_low_speed) {
2235 sClockPrescale = 0x19; /* mod 9 (divide by 10) prescale */
2236 rp_baud_base[i] = 230400;
2238 sClockPrescale = 0x14; /* mod 4 (devide by 5) prescale */
2239 rp_baud_base[i] = 460800;
2242 for (aiop = 0; aiop < MAX_AIOPS_PER_BOARD; aiop++)
2243 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x400);
2245 num_aiops = sInitController(ctlp, i, controller + (i * 0x400), aiopio, MAX_AIOPS_PER_BOARD, 0, FREQ_DIS, 0);
2247 if (ctlp->boardType == ROCKET_TYPE_PC104) {
2248 sEnAiop(ctlp, 2); /* only one AIOPIC, but these */
2249 sEnAiop(ctlp, 3); /* CSels used for other stuff */
2252 /* If something went wrong initing the AIOP's release the ISA IO memory */
2253 if (num_aiops <= 0) {
2254 release_region(rcktpt_io_addr[i], 64);
2255 rcktpt_io_addr[i] = 0;
2259 rocketModel[i].startingPortNumber = nextLineNumber;
2261 for (aiop = 0; aiop < num_aiops; aiop++) {
2262 sResetAiopByNum(ctlp, aiop);
2263 sEnAiop(ctlp, aiop);
2264 num_chan = sGetAiopNumChan(ctlp, aiop);
2265 total_num_chan += num_chan;
2266 for (chan = 0; chan < num_chan; chan++)
2267 init_r_port(i, aiop, chan, NULL);
2270 if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) || (rcktpt_type[i] == ROCKET_TYPE_MODEMII)) {
2271 num_chan = sGetAiopNumChan(ctlp, 0);
2272 total_num_chan = num_chan;
2273 for (chan = 0; chan < num_chan; chan++)
2274 sModemReset(ctlp, chan, 1);
2276 for (chan = 0; chan < num_chan; chan++)
2277 sModemReset(ctlp, chan, 0);
2279 strcpy(rocketModel[i].modelString, "RocketModem ISA");
2281 strcpy(rocketModel[i].modelString, "RocketPort ISA");
2283 rocketModel[i].numPorts = total_num_chan;
2284 rocketModel[i].model = MODEL_ISA;
2286 printk(KERN_INFO "RocketPort ISA card #%d found at 0x%lx - %d AIOPs %s\n",
2287 i, rcktpt_io_addr[i], num_aiops, type_string);
2289 printk(KERN_INFO "Installing %s, creating /dev/ttyR%d - %ld\n",
2290 rocketModel[i].modelString,
2291 rocketModel[i].startingPortNumber,
2292 rocketModel[i].startingPortNumber +
2293 rocketModel[i].numPorts - 1);
2298 static struct tty_operations rocket_ops = {
2302 .put_char = rp_put_char,
2303 .write_room = rp_write_room,
2304 .chars_in_buffer = rp_chars_in_buffer,
2305 .flush_buffer = rp_flush_buffer,
2307 .throttle = rp_throttle,
2308 .unthrottle = rp_unthrottle,
2309 .set_termios = rp_set_termios,
2312 .hangup = rp_hangup,
2313 .break_ctl = rp_break,
2314 .send_xchar = rp_send_xchar,
2315 .wait_until_sent = rp_wait_until_sent,
2316 .tiocmget = rp_tiocmget,
2317 .tiocmset = rp_tiocmset,
2321 * The module "startup" routine; it's run when the module is loaded.
2323 int __init rp_init(void)
2325 int retval, pci_boards_found, isa_boards_found, i;
2327 printk(KERN_INFO "RocketPort device driver module, version %s, %s\n",
2328 ROCKET_VERSION, ROCKET_DATE);
2330 rocket_driver = alloc_tty_driver(MAX_RP_PORTS);
2335 * Set up the timer channel.
2337 init_timer(&rocket_timer);
2338 rocket_timer.function = rp_do_poll;
2341 * Initialize the array of pointers to our own internal state
2344 memset(rp_table, 0, sizeof (rp_table));
2345 memset(xmit_flags, 0, sizeof (xmit_flags));
2347 for (i = 0; i < MAX_RP_PORTS; i++)
2350 memset(rocketModel, 0, sizeof (rocketModel));
2353 * If board 1 is non-zero, there is at least one ISA configured. If controller is
2354 * zero, use the default controller IO address of board1 + 0x40.
2357 if (controller == 0)
2358 controller = board1 + 0x40;
2360 controller = 0; /* Used as a flag, meaning no ISA boards */
2363 /* If an ISA card is configured, reserve the 4 byte IO space for the Mudbac controller */
2364 if (controller && (!request_region(controller, 4, "Comtrol RocketPort"))) {
2365 printk(KERN_INFO "Unable to reserve IO region for first configured ISA RocketPort controller 0x%lx. Driver exiting \n", controller);
2369 /* Store ISA variable retrieved from command line or .conf file. */
2370 rcktpt_io_addr[0] = board1;
2371 rcktpt_io_addr[1] = board2;
2372 rcktpt_io_addr[2] = board3;
2373 rcktpt_io_addr[3] = board4;
2375 rcktpt_type[0] = modem1 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2376 rcktpt_type[0] = pc104_1[0] ? ROCKET_TYPE_PC104 : rcktpt_type[0];
2377 rcktpt_type[1] = modem2 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2378 rcktpt_type[1] = pc104_2[0] ? ROCKET_TYPE_PC104 : rcktpt_type[1];
2379 rcktpt_type[2] = modem3 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2380 rcktpt_type[2] = pc104_3[0] ? ROCKET_TYPE_PC104 : rcktpt_type[2];
2381 rcktpt_type[3] = modem4 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2382 rcktpt_type[3] = pc104_4[0] ? ROCKET_TYPE_PC104 : rcktpt_type[3];
2385 * Set up the tty driver structure and then register this
2386 * driver with the tty layer.
2389 rocket_driver->owner = THIS_MODULE;
2390 rocket_driver->flags = TTY_DRIVER_NO_DEVFS;
2391 rocket_driver->devfs_name = "tts/R";
2392 rocket_driver->name = "ttyR";
2393 rocket_driver->driver_name = "Comtrol RocketPort";
2394 rocket_driver->major = TTY_ROCKET_MAJOR;
2395 rocket_driver->minor_start = 0;
2396 rocket_driver->type = TTY_DRIVER_TYPE_SERIAL;
2397 rocket_driver->subtype = SERIAL_TYPE_NORMAL;
2398 rocket_driver->init_termios = tty_std_termios;
2399 rocket_driver->init_termios.c_cflag =
2400 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
2401 #ifdef ROCKET_SOFT_FLOW
2402 rocket_driver->flags |= TTY_DRIVER_REAL_RAW | TTY_DRIVER_NO_DEVFS;
2404 tty_set_operations(rocket_driver, &rocket_ops);
2406 retval = tty_register_driver(rocket_driver);
2408 printk(KERN_INFO "Couldn't install tty RocketPort driver (error %d)\n", -retval);
2409 put_tty_driver(rocket_driver);
2413 #ifdef ROCKET_DEBUG_OPEN
2414 printk(KERN_INFO "RocketPort driver is major %d\n", rocket_driver.major);
2418 * OK, let's probe each of the controllers looking for boards. Any boards found
2419 * will be initialized here.
2421 isa_boards_found = 0;
2422 pci_boards_found = 0;
2424 for (i = 0; i < NUM_BOARDS; i++) {
2430 if (isa_boards_found < NUM_BOARDS)
2431 pci_boards_found = init_PCI(isa_boards_found);
2434 max_board = pci_boards_found + isa_boards_found;
2436 if (max_board == 0) {
2437 printk(KERN_INFO "No rocketport ports found; unloading driver.\n");
2438 del_timer_sync(&rocket_timer);
2439 tty_unregister_driver(rocket_driver);
2440 put_tty_driver(rocket_driver);
2449 static void rp_cleanup_module(void)
2454 del_timer_sync(&rocket_timer);
2456 retval = tty_unregister_driver(rocket_driver);
2458 printk(KERN_INFO "Error %d while trying to unregister "
2459 "rocketport driver\n", -retval);
2460 put_tty_driver(rocket_driver);
2462 for (i = 0; i < MAX_RP_PORTS; i++) {
2467 for (i = 0; i < NUM_BOARDS; i++) {
2468 if (rcktpt_io_addr[i] <= 0 || is_PCI[i])
2470 release_region(rcktpt_io_addr[i], 64);
2473 release_region(controller, 4);
2477 /***********************************************************************
2478 Copyright 1994 Comtrol Corporation.
2479 All Rights Reserved.
2481 The following source code is subject to Comtrol Corporation's
2482 Developer's License Agreement.
2484 This source code is protected by United States copyright law and
2485 international copyright treaties.
2487 This source code may only be used to develop software products that
2488 will operate with Comtrol brand hardware.
2490 You may not reproduce nor distribute this source code in its original
2491 form but must produce a derivative work which includes portions of
2492 this source code only.
2494 The portions of this source code which you use in your derivative
2495 work must bear Comtrol's copyright notice:
2497 Copyright 1994 Comtrol Corporation.
2499 ***********************************************************************/
2509 static Byte_t RData[RDATASIZE] = {
2510 0x00, 0x09, 0xf6, 0x82,
2511 0x02, 0x09, 0x86, 0xfb,
2512 0x04, 0x09, 0x00, 0x0a,
2513 0x06, 0x09, 0x01, 0x0a,
2514 0x08, 0x09, 0x8a, 0x13,
2515 0x0a, 0x09, 0xc5, 0x11,
2516 0x0c, 0x09, 0x86, 0x85,
2517 0x0e, 0x09, 0x20, 0x0a,
2518 0x10, 0x09, 0x21, 0x0a,
2519 0x12, 0x09, 0x41, 0xff,
2520 0x14, 0x09, 0x82, 0x00,
2521 0x16, 0x09, 0x82, 0x7b,
2522 0x18, 0x09, 0x8a, 0x7d,
2523 0x1a, 0x09, 0x88, 0x81,
2524 0x1c, 0x09, 0x86, 0x7a,
2525 0x1e, 0x09, 0x84, 0x81,
2526 0x20, 0x09, 0x82, 0x7c,
2527 0x22, 0x09, 0x0a, 0x0a
2530 static Byte_t RRegData[RREGDATASIZE] = {
2531 0x00, 0x09, 0xf6, 0x82, /* 00: Stop Rx processor */
2532 0x08, 0x09, 0x8a, 0x13, /* 04: Tx software flow control */
2533 0x0a, 0x09, 0xc5, 0x11, /* 08: XON char */
2534 0x0c, 0x09, 0x86, 0x85, /* 0c: XANY */
2535 0x12, 0x09, 0x41, 0xff, /* 10: Rx mask char */
2536 0x14, 0x09, 0x82, 0x00, /* 14: Compare/Ignore #0 */
2537 0x16, 0x09, 0x82, 0x7b, /* 18: Compare #1 */
2538 0x18, 0x09, 0x8a, 0x7d, /* 1c: Compare #2 */
2539 0x1a, 0x09, 0x88, 0x81, /* 20: Interrupt #1 */
2540 0x1c, 0x09, 0x86, 0x7a, /* 24: Ignore/Replace #1 */
2541 0x1e, 0x09, 0x84, 0x81, /* 28: Interrupt #2 */
2542 0x20, 0x09, 0x82, 0x7c, /* 2c: Ignore/Replace #2 */
2543 0x22, 0x09, 0x0a, 0x0a /* 30: Rx FIFO Enable */
2546 CONTROLLER_T sController[CTL_SIZE] = {
2547 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
2548 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
2549 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
2550 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
2551 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
2552 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
2553 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
2554 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}}
2557 Byte_t sBitMapClrTbl[8] = {
2558 0xfe, 0xfd, 0xfb, 0xf7, 0xef, 0xdf, 0xbf, 0x7f
2561 Byte_t sBitMapSetTbl[8] = {
2562 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80
2565 int sClockPrescale = 0x14;
2567 /***************************************************************************
2568 Function: sInitController
2569 Purpose: Initialization of controller global registers and controller
2571 Call: sInitController(CtlP,CtlNum,MudbacIO,AiopIOList,AiopIOListSize,
2572 IRQNum,Frequency,PeriodicOnly)
2573 CONTROLLER_T *CtlP; Ptr to controller structure
2574 int CtlNum; Controller number
2575 ByteIO_t MudbacIO; Mudbac base I/O address.
2576 ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
2577 This list must be in the order the AIOPs will be found on the
2578 controller. Once an AIOP in the list is not found, it is
2579 assumed that there are no more AIOPs on the controller.
2580 int AiopIOListSize; Number of addresses in AiopIOList
2581 int IRQNum; Interrupt Request number. Can be any of the following:
2582 0: Disable global interrupts
2591 Byte_t Frequency: A flag identifying the frequency
2592 of the periodic interrupt, can be any one of the following:
2593 FREQ_DIS - periodic interrupt disabled
2594 FREQ_137HZ - 137 Hertz
2595 FREQ_69HZ - 69 Hertz
2596 FREQ_34HZ - 34 Hertz
2597 FREQ_17HZ - 17 Hertz
2600 If IRQNum is set to 0 the Frequency parameter is
2601 overidden, it is forced to a value of FREQ_DIS.
2602 int PeriodicOnly: TRUE if all interrupts except the periodic
2603 interrupt are to be blocked.
2604 FALSE is both the periodic interrupt and
2605 other channel interrupts are allowed.
2606 If IRQNum is set to 0 the PeriodicOnly parameter is
2607 overidden, it is forced to a value of FALSE.
2608 Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
2609 initialization failed.
2612 If periodic interrupts are to be disabled but AIOP interrupts
2613 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to FALSE.
2615 If interrupts are to be completely disabled set IRQNum to 0.
2617 Setting Frequency to FREQ_DIS and PeriodicOnly to TRUE is an
2618 invalid combination.
2620 This function performs initialization of global interrupt modes,
2621 but it does not actually enable global interrupts. To enable
2622 and disable global interrupts use functions sEnGlobalInt() and
2623 sDisGlobalInt(). Enabling of global interrupts is normally not
2624 done until all other initializations are complete.
2626 Even if interrupts are globally enabled, they must also be
2627 individually enabled for each channel that is to generate
2630 Warnings: No range checking on any of the parameters is done.
2632 No context switches are allowed while executing this function.
2634 After this function all AIOPs on the controller are disabled,
2635 they can be enabled with sEnAiop().
2637 int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
2638 ByteIO_t * AiopIOList, int AiopIOListSize, int IRQNum,
2639 Byte_t Frequency, int PeriodicOnly)
2645 CtlP->AiopIntrBits = aiop_intr_bits;
2646 CtlP->AltChanRingIndicator = 0;
2647 CtlP->CtlNum = CtlNum;
2648 CtlP->CtlID = CTLID_0001; /* controller release 1 */
2649 CtlP->BusType = isISA;
2650 CtlP->MBaseIO = MudbacIO;
2651 CtlP->MReg1IO = MudbacIO + 1;
2652 CtlP->MReg2IO = MudbacIO + 2;
2653 CtlP->MReg3IO = MudbacIO + 3;
2655 CtlP->MReg2 = 0; /* interrupt disable */
2656 CtlP->MReg3 = 0; /* no periodic interrupts */
2658 if (sIRQMap[IRQNum] == 0) { /* interrupts globally disabled */
2659 CtlP->MReg2 = 0; /* interrupt disable */
2660 CtlP->MReg3 = 0; /* no periodic interrupts */
2662 CtlP->MReg2 = sIRQMap[IRQNum]; /* set IRQ number */
2663 CtlP->MReg3 = Frequency; /* set frequency */
2664 if (PeriodicOnly) { /* periodic interrupt only */
2665 CtlP->MReg3 |= PERIODIC_ONLY;
2669 sOutB(CtlP->MReg2IO, CtlP->MReg2);
2670 sOutB(CtlP->MReg3IO, CtlP->MReg3);
2671 sControllerEOI(CtlP); /* clear EOI if warm init */
2674 for (i = done = 0; i < AiopIOListSize; i++) {
2676 CtlP->AiopIO[i] = (WordIO_t) io;
2677 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
2678 sOutB(CtlP->MReg2IO, CtlP->MReg2 | (i & 0x03)); /* AIOP index */
2679 sOutB(MudbacIO, (Byte_t) (io >> 6)); /* set up AIOP I/O in MUDBAC */
2682 sEnAiop(CtlP, i); /* enable the AIOP */
2683 CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
2684 if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
2685 done = 1; /* done looking for AIOPs */
2687 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
2688 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
2689 sOutB(io + _INDX_DATA, sClockPrescale);
2690 CtlP->NumAiop++; /* bump count of AIOPs */
2692 sDisAiop(CtlP, i); /* disable AIOP */
2695 if (CtlP->NumAiop == 0)
2698 return (CtlP->NumAiop);
2701 /***************************************************************************
2702 Function: sPCIInitController
2703 Purpose: Initialization of controller global registers and controller
2705 Call: sPCIInitController(CtlP,CtlNum,AiopIOList,AiopIOListSize,
2706 IRQNum,Frequency,PeriodicOnly)
2707 CONTROLLER_T *CtlP; Ptr to controller structure
2708 int CtlNum; Controller number
2709 ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
2710 This list must be in the order the AIOPs will be found on the
2711 controller. Once an AIOP in the list is not found, it is
2712 assumed that there are no more AIOPs on the controller.
2713 int AiopIOListSize; Number of addresses in AiopIOList
2714 int IRQNum; Interrupt Request number. Can be any of the following:
2715 0: Disable global interrupts
2724 Byte_t Frequency: A flag identifying the frequency
2725 of the periodic interrupt, can be any one of the following:
2726 FREQ_DIS - periodic interrupt disabled
2727 FREQ_137HZ - 137 Hertz
2728 FREQ_69HZ - 69 Hertz
2729 FREQ_34HZ - 34 Hertz
2730 FREQ_17HZ - 17 Hertz
2733 If IRQNum is set to 0 the Frequency parameter is
2734 overidden, it is forced to a value of FREQ_DIS.
2735 int PeriodicOnly: TRUE if all interrupts except the periodic
2736 interrupt are to be blocked.
2737 FALSE is both the periodic interrupt and
2738 other channel interrupts are allowed.
2739 If IRQNum is set to 0 the PeriodicOnly parameter is
2740 overidden, it is forced to a value of FALSE.
2741 Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
2742 initialization failed.
2745 If periodic interrupts are to be disabled but AIOP interrupts
2746 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to FALSE.
2748 If interrupts are to be completely disabled set IRQNum to 0.
2750 Setting Frequency to FREQ_DIS and PeriodicOnly to TRUE is an
2751 invalid combination.
2753 This function performs initialization of global interrupt modes,
2754 but it does not actually enable global interrupts. To enable
2755 and disable global interrupts use functions sEnGlobalInt() and
2756 sDisGlobalInt(). Enabling of global interrupts is normally not
2757 done until all other initializations are complete.
2759 Even if interrupts are globally enabled, they must also be
2760 individually enabled for each channel that is to generate
2763 Warnings: No range checking on any of the parameters is done.
2765 No context switches are allowed while executing this function.
2767 After this function all AIOPs on the controller are disabled,
2768 they can be enabled with sEnAiop().
2770 int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum,
2771 ByteIO_t * AiopIOList, int AiopIOListSize,
2772 WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
2773 int PeriodicOnly, int altChanRingIndicator,
2779 CtlP->AltChanRingIndicator = altChanRingIndicator;
2780 CtlP->UPCIRingInd = UPCIRingInd;
2781 CtlP->CtlNum = CtlNum;
2782 CtlP->CtlID = CTLID_0001; /* controller release 1 */
2783 CtlP->BusType = isPCI; /* controller release 1 */
2787 CtlP->PCIIO = ConfigIO + _PCI_9030_INT_CTRL;
2788 CtlP->PCIIO2 = ConfigIO + _PCI_9030_GPIO_CTRL;
2789 CtlP->AiopIntrBits = upci_aiop_intr_bits;
2793 (WordIO_t) ((ByteIO_t) AiopIOList[0] + _PCI_INT_FUNC);
2794 CtlP->AiopIntrBits = aiop_intr_bits;
2797 sPCIControllerEOI(CtlP); /* clear EOI if warm init */
2800 for (i = 0; i < AiopIOListSize; i++) {
2802 CtlP->AiopIO[i] = (WordIO_t) io;
2803 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
2805 CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
2806 if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
2807 break; /* done looking for AIOPs */
2809 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
2810 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
2811 sOutB(io + _INDX_DATA, sClockPrescale);
2812 CtlP->NumAiop++; /* bump count of AIOPs */
2815 if (CtlP->NumAiop == 0)
2818 return (CtlP->NumAiop);
2821 /***************************************************************************
2822 Function: sReadAiopID
2823 Purpose: Read the AIOP idenfication number directly from an AIOP.
2824 Call: sReadAiopID(io)
2825 ByteIO_t io: AIOP base I/O address
2826 Return: int: Flag AIOPID_XXXX if a valid AIOP is found, where X
2827 is replace by an identifying number.
2828 Flag AIOPID_NULL if no valid AIOP is found
2829 Warnings: No context switches are allowed while executing this function.
2832 int sReadAiopID(ByteIO_t io)
2834 Byte_t AiopID; /* ID byte from AIOP */
2836 sOutB(io + _CMD_REG, RESET_ALL); /* reset AIOP */
2837 sOutB(io + _CMD_REG, 0x0);
2838 AiopID = sInW(io + _CHN_STAT0) & 0x07;
2841 else /* AIOP does not exist */
2845 /***************************************************************************
2846 Function: sReadAiopNumChan
2847 Purpose: Read the number of channels available in an AIOP directly from
2849 Call: sReadAiopNumChan(io)
2850 WordIO_t io: AIOP base I/O address
2851 Return: int: The number of channels available
2852 Comments: The number of channels is determined by write/reads from identical
2853 offsets within the SRAM address spaces for channels 0 and 4.
2854 If the channel 4 space is mirrored to channel 0 it is a 4 channel
2855 AIOP, otherwise it is an 8 channel.
2856 Warnings: No context switches are allowed while executing this function.
2858 int sReadAiopNumChan(WordIO_t io)
2861 static Byte_t R[4] = { 0x00, 0x00, 0x34, 0x12 };
2863 /* write to chan 0 SRAM */
2864 sOutDW((DWordIO_t) io + _INDX_ADDR, *((DWord_t *) & R[0]));
2865 sOutW(io + _INDX_ADDR, 0); /* read from SRAM, chan 0 */
2866 x = sInW(io + _INDX_DATA);
2867 sOutW(io + _INDX_ADDR, 0x4000); /* read from SRAM, chan 4 */
2868 if (x != sInW(io + _INDX_DATA)) /* if different must be 8 chan */
2874 /***************************************************************************
2876 Purpose: Initialization of a channel and channel structure
2877 Call: sInitChan(CtlP,ChP,AiopNum,ChanNum)
2878 CONTROLLER_T *CtlP; Ptr to controller structure
2879 CHANNEL_T *ChP; Ptr to channel structure
2880 int AiopNum; AIOP number within controller
2881 int ChanNum; Channel number within AIOP
2882 Return: int: TRUE if initialization succeeded, FALSE if it fails because channel
2883 number exceeds number of channels available in AIOP.
2884 Comments: This function must be called before a channel can be used.
2885 Warnings: No range checking on any of the parameters is done.
2887 No context switches are allowed while executing this function.
2889 int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
2900 if (ChanNum >= CtlP->AiopNumChan[AiopNum])
2901 return (FALSE); /* exceeds num chans in AIOP */
2903 /* Channel, AIOP, and controller identifiers */
2905 ChP->ChanID = CtlP->AiopID[AiopNum];
2906 ChP->AiopNum = AiopNum;
2907 ChP->ChanNum = ChanNum;
2909 /* Global direct addresses */
2910 AiopIO = CtlP->AiopIO[AiopNum];
2911 ChP->Cmd = (ByteIO_t) AiopIO + _CMD_REG;
2912 ChP->IntChan = (ByteIO_t) AiopIO + _INT_CHAN;
2913 ChP->IntMask = (ByteIO_t) AiopIO + _INT_MASK;
2914 ChP->IndexAddr = (DWordIO_t) AiopIO + _INDX_ADDR;
2915 ChP->IndexData = AiopIO + _INDX_DATA;
2917 /* Channel direct addresses */
2918 ChIOOff = AiopIO + ChP->ChanNum * 2;
2919 ChP->TxRxData = ChIOOff + _TD0;
2920 ChP->ChanStat = ChIOOff + _CHN_STAT0;
2921 ChP->TxRxCount = ChIOOff + _FIFO_CNT0;
2922 ChP->IntID = (ByteIO_t) AiopIO + ChP->ChanNum + _INT_ID0;
2924 /* Initialize the channel from the RData array */
2925 for (i = 0; i < RDATASIZE; i += 4) {
2927 R[1] = RData[i + 1] + 0x10 * ChanNum;
2928 R[2] = RData[i + 2];
2929 R[3] = RData[i + 3];
2930 sOutDW(ChP->IndexAddr, *((DWord_t *) & R[0]));
2934 for (i = 0; i < RREGDATASIZE; i += 4) {
2935 ChR[i] = RRegData[i];
2936 ChR[i + 1] = RRegData[i + 1] + 0x10 * ChanNum;
2937 ChR[i + 2] = RRegData[i + 2];
2938 ChR[i + 3] = RRegData[i + 3];
2941 /* Indexed registers */
2942 ChOff = (Word_t) ChanNum *0x1000;
2944 if (sClockPrescale == 0x14)
2949 ChP->BaudDiv[0] = (Byte_t) (ChOff + _BAUD);
2950 ChP->BaudDiv[1] = (Byte_t) ((ChOff + _BAUD) >> 8);
2951 ChP->BaudDiv[2] = (Byte_t) brd9600;
2952 ChP->BaudDiv[3] = (Byte_t) (brd9600 >> 8);
2953 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->BaudDiv[0]);
2955 ChP->TxControl[0] = (Byte_t) (ChOff + _TX_CTRL);
2956 ChP->TxControl[1] = (Byte_t) ((ChOff + _TX_CTRL) >> 8);
2957 ChP->TxControl[2] = 0;
2958 ChP->TxControl[3] = 0;
2959 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxControl[0]);
2961 ChP->RxControl[0] = (Byte_t) (ChOff + _RX_CTRL);
2962 ChP->RxControl[1] = (Byte_t) ((ChOff + _RX_CTRL) >> 8);
2963 ChP->RxControl[2] = 0;
2964 ChP->RxControl[3] = 0;
2965 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->RxControl[0]);
2967 ChP->TxEnables[0] = (Byte_t) (ChOff + _TX_ENBLS);
2968 ChP->TxEnables[1] = (Byte_t) ((ChOff + _TX_ENBLS) >> 8);
2969 ChP->TxEnables[2] = 0;
2970 ChP->TxEnables[3] = 0;
2971 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxEnables[0]);
2973 ChP->TxCompare[0] = (Byte_t) (ChOff + _TXCMP1);
2974 ChP->TxCompare[1] = (Byte_t) ((ChOff + _TXCMP1) >> 8);
2975 ChP->TxCompare[2] = 0;
2976 ChP->TxCompare[3] = 0;
2977 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxCompare[0]);
2979 ChP->TxReplace1[0] = (Byte_t) (ChOff + _TXREP1B1);
2980 ChP->TxReplace1[1] = (Byte_t) ((ChOff + _TXREP1B1) >> 8);
2981 ChP->TxReplace1[2] = 0;
2982 ChP->TxReplace1[3] = 0;
2983 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxReplace1[0]);
2985 ChP->TxReplace2[0] = (Byte_t) (ChOff + _TXREP2);
2986 ChP->TxReplace2[1] = (Byte_t) ((ChOff + _TXREP2) >> 8);
2987 ChP->TxReplace2[2] = 0;
2988 ChP->TxReplace2[3] = 0;
2989 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxReplace2[0]);
2991 ChP->TxFIFOPtrs = ChOff + _TXF_OUTP;
2992 ChP->TxFIFO = ChOff + _TX_FIFO;
2994 sOutB(ChP->Cmd, (Byte_t) ChanNum | RESTXFCNT); /* apply reset Tx FIFO count */
2995 sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Tx FIFO count */
2996 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
2997 sOutW(ChP->IndexData, 0);
2998 ChP->RxFIFOPtrs = ChOff + _RXF_OUTP;
2999 ChP->RxFIFO = ChOff + _RX_FIFO;
3001 sOutB(ChP->Cmd, (Byte_t) ChanNum | RESRXFCNT); /* apply reset Rx FIFO count */
3002 sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Rx FIFO count */
3003 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
3004 sOutW(ChP->IndexData, 0);
3005 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
3006 sOutW(ChP->IndexData, 0);
3007 ChP->TxPrioCnt = ChOff + _TXP_CNT;
3008 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioCnt);
3009 sOutB(ChP->IndexData, 0);
3010 ChP->TxPrioPtr = ChOff + _TXP_PNTR;
3011 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioPtr);
3012 sOutB(ChP->IndexData, 0);
3013 ChP->TxPrioBuf = ChOff + _TXP_BUF;
3014 sEnRxProcessor(ChP); /* start the Rx processor */
3019 /***************************************************************************
3020 Function: sStopRxProcessor
3021 Purpose: Stop the receive processor from processing a channel.
3022 Call: sStopRxProcessor(ChP)
3023 CHANNEL_T *ChP; Ptr to channel structure
3025 Comments: The receive processor can be started again with sStartRxProcessor().
3026 This function causes the receive processor to skip over the
3027 stopped channel. It does not stop it from processing other channels.
3029 Warnings: No context switches are allowed while executing this function.
3031 Do not leave the receive processor stopped for more than one
3034 After calling this function a delay of 4 uS is required to ensure
3035 that the receive processor is no longer processing this channel.
3037 void sStopRxProcessor(CHANNEL_T * ChP)
3045 sOutDW(ChP->IndexAddr, *(DWord_t *) & R[0]);
3048 /***************************************************************************
3049 Function: sFlushRxFIFO
3050 Purpose: Flush the Rx FIFO
3051 Call: sFlushRxFIFO(ChP)
3052 CHANNEL_T *ChP; Ptr to channel structure
3054 Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
3055 while it is being flushed the receive processor is stopped
3056 and the transmitter is disabled. After these operations a
3057 4 uS delay is done before clearing the pointers to allow
3058 the receive processor to stop. These items are handled inside
3060 Warnings: No context switches are allowed while executing this function.
3062 void sFlushRxFIFO(CHANNEL_T * ChP)
3065 Byte_t Ch; /* channel number within AIOP */
3066 int RxFIFOEnabled; /* TRUE if Rx FIFO enabled */
3068 if (sGetRxCnt(ChP) == 0) /* Rx FIFO empty */
3069 return; /* don't need to flush */
3071 RxFIFOEnabled = FALSE;
3072 if (ChP->R[0x32] == 0x08) { /* Rx FIFO is enabled */
3073 RxFIFOEnabled = TRUE;
3074 sDisRxFIFO(ChP); /* disable it */
3075 for (i = 0; i < 2000 / 200; i++) /* delay 2 uS to allow proc to disable FIFO */
3076 sInB(ChP->IntChan); /* depends on bus i/o timing */
3078 sGetChanStatus(ChP); /* clear any pending Rx errors in chan stat */
3079 Ch = (Byte_t) sGetChanNum(ChP);
3080 sOutB(ChP->Cmd, Ch | RESRXFCNT); /* apply reset Rx FIFO count */
3081 sOutB(ChP->Cmd, Ch); /* remove reset Rx FIFO count */
3082 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
3083 sOutW(ChP->IndexData, 0);
3084 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
3085 sOutW(ChP->IndexData, 0);
3087 sEnRxFIFO(ChP); /* enable Rx FIFO */
3090 /***************************************************************************
3091 Function: sFlushTxFIFO
3092 Purpose: Flush the Tx FIFO
3093 Call: sFlushTxFIFO(ChP)
3094 CHANNEL_T *ChP; Ptr to channel structure
3096 Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
3097 while it is being flushed the receive processor is stopped
3098 and the transmitter is disabled. After these operations a
3099 4 uS delay is done before clearing the pointers to allow
3100 the receive processor to stop. These items are handled inside
3102 Warnings: No context switches are allowed while executing this function.
3104 void sFlushTxFIFO(CHANNEL_T * ChP)
3107 Byte_t Ch; /* channel number within AIOP */
3108 int TxEnabled; /* TRUE if transmitter enabled */
3110 if (sGetTxCnt(ChP) == 0) /* Tx FIFO empty */
3111 return; /* don't need to flush */
3114 if (ChP->TxControl[3] & TX_ENABLE) {
3116 sDisTransmit(ChP); /* disable transmitter */
3118 sStopRxProcessor(ChP); /* stop Rx processor */
3119 for (i = 0; i < 4000 / 200; i++) /* delay 4 uS to allow proc to stop */
3120 sInB(ChP->IntChan); /* depends on bus i/o timing */
3121 Ch = (Byte_t) sGetChanNum(ChP);
3122 sOutB(ChP->Cmd, Ch | RESTXFCNT); /* apply reset Tx FIFO count */
3123 sOutB(ChP->Cmd, Ch); /* remove reset Tx FIFO count */
3124 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
3125 sOutW(ChP->IndexData, 0);
3127 sEnTransmit(ChP); /* enable transmitter */
3128 sStartRxProcessor(ChP); /* restart Rx processor */
3131 /***************************************************************************
3132 Function: sWriteTxPrioByte
3133 Purpose: Write a byte of priority transmit data to a channel
3134 Call: sWriteTxPrioByte(ChP,Data)
3135 CHANNEL_T *ChP; Ptr to channel structure
3136 Byte_t Data; The transmit data byte
3138 Return: int: 1 if the bytes is successfully written, otherwise 0.
3140 Comments: The priority byte is transmitted before any data in the Tx FIFO.
3142 Warnings: No context switches are allowed while executing this function.
3144 int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data)
3146 Byte_t DWBuf[4]; /* buffer for double word writes */
3147 Word_t *WordPtr; /* must be far because Win SS != DS */
3148 register DWordIO_t IndexAddr;
3150 if (sGetTxCnt(ChP) > 1) { /* write it to Tx priority buffer */
3151 IndexAddr = ChP->IndexAddr;
3152 sOutW((WordIO_t) IndexAddr, ChP->TxPrioCnt); /* get priority buffer status */
3153 if (sInB((ByteIO_t) ChP->IndexData) & PRI_PEND) /* priority buffer busy */
3154 return (0); /* nothing sent */
3156 WordPtr = (Word_t *) (&DWBuf[0]);
3157 *WordPtr = ChP->TxPrioBuf; /* data byte address */
3159 DWBuf[2] = Data; /* data byte value */
3160 sOutDW(IndexAddr, *((DWord_t *) (&DWBuf[0]))); /* write it out */
3162 *WordPtr = ChP->TxPrioCnt; /* Tx priority count address */
3164 DWBuf[2] = PRI_PEND + 1; /* indicate 1 byte pending */
3165 DWBuf[3] = 0; /* priority buffer pointer */
3166 sOutDW(IndexAddr, *((DWord_t *) (&DWBuf[0]))); /* write it out */
3167 } else { /* write it to Tx FIFO */
3169 sWriteTxByte(sGetTxRxDataIO(ChP), Data);
3171 return (1); /* 1 byte sent */
3174 /***************************************************************************
3175 Function: sEnInterrupts
3176 Purpose: Enable one or more interrupts for a channel
3177 Call: sEnInterrupts(ChP,Flags)
3178 CHANNEL_T *ChP; Ptr to channel structure
3179 Word_t Flags: Interrupt enable flags, can be any combination
3180 of the following flags:
3181 TXINT_EN: Interrupt on Tx FIFO empty
3182 RXINT_EN: Interrupt on Rx FIFO at trigger level (see
3184 SRCINT_EN: Interrupt on SRC (Special Rx Condition)
3185 MCINT_EN: Interrupt on modem input change
3186 CHANINT_EN: Allow channel interrupt signal to the AIOP's
3187 Interrupt Channel Register.
3189 Comments: If an interrupt enable flag is set in Flags, that interrupt will be
3190 enabled. If an interrupt enable flag is not set in Flags, that
3191 interrupt will not be changed. Interrupts can be disabled with
3192 function sDisInterrupts().
3194 This function sets the appropriate bit for the channel in the AIOP's
3195 Interrupt Mask Register if the CHANINT_EN flag is set. This allows
3196 this channel's bit to be set in the AIOP's Interrupt Channel Register.
3198 Interrupts must also be globally enabled before channel interrupts
3199 will be passed on to the host. This is done with function
3202 In some cases it may be desirable to disable interrupts globally but
3203 enable channel interrupts. This would allow the global interrupt
3204 status register to be used to determine which AIOPs need service.
3206 void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags)
3208 Byte_t Mask; /* Interrupt Mask Register */
3210 ChP->RxControl[2] |=
3211 ((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3213 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->RxControl[0]);
3215 ChP->TxControl[2] |= ((Byte_t) Flags & TXINT_EN);
3217 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxControl[0]);
3219 if (Flags & CHANINT_EN) {
3220 Mask = sInB(ChP->IntMask) | sBitMapSetTbl[ChP->ChanNum];
3221 sOutB(ChP->IntMask, Mask);
3225 /***************************************************************************
3226 Function: sDisInterrupts
3227 Purpose: Disable one or more interrupts for a channel
3228 Call: sDisInterrupts(ChP,Flags)
3229 CHANNEL_T *ChP; Ptr to channel structure
3230 Word_t Flags: Interrupt flags, can be any combination
3231 of the following flags:
3232 TXINT_EN: Interrupt on Tx FIFO empty
3233 RXINT_EN: Interrupt on Rx FIFO at trigger level (see
3235 SRCINT_EN: Interrupt on SRC (Special Rx Condition)
3236 MCINT_EN: Interrupt on modem input change
3237 CHANINT_EN: Disable channel interrupt signal to the
3238 AIOP's Interrupt Channel Register.
3240 Comments: If an interrupt flag is set in Flags, that interrupt will be
3241 disabled. If an interrupt flag is not set in Flags, that
3242 interrupt will not be changed. Interrupts can be enabled with
3243 function sEnInterrupts().
3245 This function clears the appropriate bit for the channel in the AIOP's
3246 Interrupt Mask Register if the CHANINT_EN flag is set. This blocks
3247 this channel's bit from being set in the AIOP's Interrupt Channel
3250 void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags)
3252 Byte_t Mask; /* Interrupt Mask Register */
3254 ChP->RxControl[2] &=
3255 ~((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3256 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->RxControl[0]);
3257 ChP->TxControl[2] &= ~((Byte_t) Flags & TXINT_EN);
3258 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxControl[0]);
3260 if (Flags & CHANINT_EN) {
3261 Mask = sInB(ChP->IntMask) & sBitMapClrTbl[ChP->ChanNum];
3262 sOutB(ChP->IntMask, Mask);
3266 void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode)
3268 sOutB(ChP->CtlP->AiopIO[2], (mode & 0x18) | ChP->ChanNum);
3272 * Not an official SSCI function, but how to reset RocketModems.
3275 void sModemReset(CONTROLLER_T * CtlP, int chan, int on)
3280 addr = CtlP->AiopIO[0] + 0x400;
3281 val = sInB(CtlP->MReg3IO);
3282 /* if AIOP[1] is not enabled, enable it */
3283 if ((val & 2) == 0) {
3284 val = sInB(CtlP->MReg2IO);
3285 sOutB(CtlP->MReg2IO, (val & 0xfc) | (1 & 0x03));
3286 sOutB(CtlP->MBaseIO, (unsigned char) (addr >> 6));
3292 sOutB(addr + chan, 0); /* apply or remove reset */
3297 * Not an official SSCI function, but how to reset RocketModems.
3300 void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on)
3304 addr = CtlP->AiopIO[0] + 0x40; /* 2nd AIOP */
3307 sOutB(addr + chan, 0); /* apply or remove reset */
3310 /* Resets the speaker controller on RocketModem II and III devices */
3311 static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model)
3315 /* RocketModem II speaker control is at the 8th port location of offset 0x40 */
3316 if ((model == MODEL_RP4M) || (model == MODEL_RP6M)) {
3317 addr = CtlP->AiopIO[0] + 0x4F;
3321 /* RocketModem III speaker control is at the 1st port location of offset 0x80 */
3322 if ((model == MODEL_UPCI_RM3_8PORT)
3323 || (model == MODEL_UPCI_RM3_4PORT)) {
3324 addr = CtlP->AiopIO[0] + 0x88;
3329 /* Returns the line number given the controller (board), aiop and channel number */
3330 static unsigned char GetLineNumber(int ctrl, int aiop, int ch)
3332 return lineNumbers[(ctrl << 5) | (aiop << 3) | ch];
3336 * Stores the line number associated with a given controller (board), aiop
3337 * and channel number.
3338 * Returns: The line number assigned
3340 static unsigned char SetLineNumber(int ctrl, int aiop, int ch)
3342 lineNumbers[(ctrl << 5) | (aiop << 3) | ch] = nextLineNumber++;
3343 return (nextLineNumber - 1);