drivers/i2c/busses/i2c-mpc.c

   1 /*
   2  * (C) Copyright 2003-2004
   3  * Humboldt Solutions Ltd, adrian@humboldt.co.uk.
   4
   5  * This is a combined i2c adapter and algorithm driver for the
   6  * MPC107/Tsi107 PowerPC northbridge and processors that include
   7  * the same I2C unit (8240, 8245, 85xx).
   8  *
   9  * Release 0.6
  10  *
  11  * This file is licensed under the terms of the GNU General Public
  12  * License version 2. This program is licensed "as is" without any
  13  * warranty of any kind, whether express or implied.
  14  */
  15
  16 #include <linux/config.h>
  17 #include <linux/kernel.h>
  18 #include <linux/module.h>
  19 #include <linux/sched.h>
  20 #include <linux/init.h>
  21 #include <linux/pci.h>
  22 #include <asm/io.h>
  23 #include <asm/ocp.h>
  24 #include <linux/i2c.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/delay.h>
  27
  28 #define MPC_I2C_ADDR  0x00
  29 #define MPC_I2C_FDR     0x04
  30 #define MPC_I2C_CR      0x08
  31 #define MPC_I2C_SR      0x0c
  32 #define MPC_I2C_DR      0x10
  33 #define MPC_I2C_DFSRR 0x14
  34 #define MPC_I2C_REGION 0x20
  35
  36 #define CCR_MEN  0x80
  37 #define CCR_MIEN 0x40
  38 #define CCR_MSTA 0x20
  39 #define CCR_MTX  0x10
  40 #define CCR_TXAK 0x08
  41 #define CCR_RSTA 0x04
  42
  43 #define CSR_MCF  0x80
  44 #define CSR_MAAS 0x40
  45 #define CSR_MBB  0x20
  46 #define CSR_MAL  0x10
  47 #define CSR_SRW  0x04
  48 #define CSR_MIF  0x02
  49 #define CSR_RXAK 0x01
  50
  51 struct mpc_i2c {
  52         char *base;
  53         struct ocp_def *ocpdef;
  54         u32 interrupt;
  55         wait_queue_head_t queue;
  56         struct i2c_adapter adap;
  57 };
  58
  59 static __inline__ void writeccr(struct mpc_i2c *i2c, u32 x)
  60 {
  61         writeb(x, i2c->base + MPC_I2C_CR);
  62 }
  63
  64 static irqreturn_t mpc_i2c_isr(int irq, void *dev_id, struct pt_regs *regs)
  65 {
  66         struct mpc_i2c *i2c = dev_id;
  67         if (readb(i2c->base + MPC_I2C_SR) & CSR_MIF) {
  68                 /* Read again to allow register to stabilise */
  69                 i2c->interrupt = readb(i2c->base + MPC_I2C_SR);
  70                 writeb(0, i2c->base + MPC_I2C_SR);
  71                 wake_up_interruptible(&i2c->queue);
  72         }
  73         return IRQ_HANDLED;
  74 }
  75
  76 static int i2c_wait(struct mpc_i2c *i2c, unsigned timeout, int writing)
  77 {
  78         DECLARE_WAITQUEUE(wait, current);
  79         unsigned long orig_jiffies = jiffies;
  80         u32 x;
  81         int result = 0;
  82
  83         if (i2c->ocpdef->irq == OCP_IRQ_NA) {
  84                 while (!(readb(i2c->base + MPC_I2C_SR) & CSR_MIF)) {
  85                         schedule();
  86                         if (time_after(jiffies, orig_jiffies + timeout)) {
  87                                 pr_debug("I2C: timeout\n");
  88                                 result = -EIO;
  89                                 break;
  90                         }
  91                 }
  92                 x = readb(i2c->base + MPC_I2C_SR);
  93                 writeb(0, i2c->base + MPC_I2C_SR);
  94         } else {
  95                 set_current_state(TASK_INTERRUPTIBLE);
  96                 add_wait_queue(&i2c->queue, &wait);
  97                 while (!(i2c->interrupt & CSR_MIF)) {
  98                         if (signal_pending(current)) {
  99                                 pr_debug("I2C: Interrupted\n");
 100                                 result = -EINTR;
 101                                 break;
 102                         }
 103                         if (time_after(jiffies, orig_jiffies + timeout)) {
 104                                 pr_debug("I2C: timeout\n");
 105                                 result = -EIO;
 106                                 break;
 107                         }
 108                         msleep_interruptible(jiffies_to_msecs(timeout));
 109                 }
 110                 set_current_state(TASK_RUNNING);
 111                 remove_wait_queue(&i2c->queue, &wait);
 112                 x = i2c->interrupt;
 113                 i2c->interrupt = 0;
 114         }
 115
 116         if (result < -0)
 117                 return result;
 118
 119         if (!(x & CSR_MCF)) {
 120                 pr_debug("I2C: unfinished\n");
 121                 return -EIO;
 122         }
 123
 124         if (x & CSR_MAL) {
 125                 pr_debug("I2C: MAL\n");
 126                 return -EIO;
 127         }
 128
 129         if (writing && (x & CSR_RXAK)) {
 130                 pr_debug("I2C: No RXAK\n");
 131                 /* generate stop */
 132                 writeccr(i2c, CCR_MEN);
 133                 return -EIO;
 134         }
 135         return 0;
 136 }
 137
 138 static void mpc_i2c_setclock(struct mpc_i2c *i2c)
 139 {
 140         struct ocp_fs_i2c_data *i2c_data = i2c->ocpdef->additions;
 141         /* Set clock and filters */
 142         if (i2c_data && (i2c_data->flags & FS_I2C_SEPARATE_DFSRR)) {
 143                 writeb(0x31, i2c->base + MPC_I2C_FDR);
 144                 writeb(0x10, i2c->base + MPC_I2C_DFSRR);
 145         } else if (i2c_data && (i2c_data->flags & FS_I2C_CLOCK_5200))
 146                 writeb(0x3f, i2c->base + MPC_I2C_FDR);
 147         else
 148                 writel(0x1031, i2c->base + MPC_I2C_FDR);
 149 }
 150
 151 static void mpc_i2c_start(struct mpc_i2c *i2c)
 152 {
 153         /* Clear arbitration */
 154         writeb(0, i2c->base + MPC_I2C_SR);
 155         /* Start with MEN */
 156         writeccr(i2c, CCR_MEN);
 157 }
 158
 159 static void mpc_i2c_stop(struct mpc_i2c *i2c)
 160 {
 161         writeccr(i2c, CCR_MEN);
 162 }
 163
 164 static int mpc_write(struct mpc_i2c *i2c, int target,
 165                      const u8 * data, int length, int restart)
 166 {
 167         int i;
 168         unsigned timeout = HZ;
 169         u32 flags = restart ? CCR_RSTA : 0;
 170
 171         /* Start with MEN */
 172         if (!restart)
 173                 writeccr(i2c, CCR_MEN);
 174         /* Start as master */
 175         writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
 176         /* Write target byte */
 177         writeb((target << 1), i2c->base + MPC_I2C_DR);
 178
 179         if (i2c_wait(i2c, timeout, 1) < 0)
 180                 return -1;
 181
 182         for (i = 0; i < length; i++) {
 183                 /* Write data byte */
 184                 writeb(data[i], i2c->base + MPC_I2C_DR);
 185
 186                 if (i2c_wait(i2c, timeout, 1) < 0)
 187                         return -1;
 188         }
 189
 190         return 0;
 191 }
 192
 193 static int mpc_read(struct mpc_i2c *i2c, int target,
 194                     u8 * data, int length, int restart)
 195 {
 196         unsigned timeout = HZ;
 197         int i;
 198         u32 flags = restart ? CCR_RSTA : 0;
 199
 200         /* Start with MEN */
 201         if (!restart)
 202                 writeccr(i2c, CCR_MEN);
 203         /* Switch to read - restart */
 204         writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
 205         /* Write target address byte - this time with the read flag set */
 206         writeb((target << 1) | 1, i2c->base + MPC_I2C_DR);
 207
 208         if (i2c_wait(i2c, timeout, 1) < 0)
 209                 return -1;
 210
 211         if (length) {
 212                 if (length == 1)
 213                         writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_TXAK);
 214                 else
 215                         writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA);
 216                 /* Dummy read */
 217                 readb(i2c->base + MPC_I2C_DR);
 218         }
 219
 220         for (i = 0; i < length; i++) {
 221                 if (i2c_wait(i2c, timeout, 0) < 0)
 222                         return -1;
 223
 224                 /* Generate txack on next to last byte */
 225                 if (i == length - 2)
 226                         writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_TXAK);
 227                 /* Generate stop on last byte */
 228                 if (i == length - 1)
 229                         writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_TXAK);
 230                 data[i] = readb(i2c->base + MPC_I2C_DR);
 231         }
 232
 233         return length;
 234 }
 235
 236 static int mpc_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 237 {
 238         struct i2c_msg *pmsg;
 239         int i;
 240         int ret = 0;
 241         unsigned long orig_jiffies = jiffies;
 242         struct mpc_i2c *i2c = i2c_get_adapdata(adap);
 243
 244         mpc_i2c_start(i2c);
 245
 246         /* Allow bus up to 1s to become not busy */
 247         while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) {
 248                 if (signal_pending(current)) {
 249                         pr_debug("I2C: Interrupted\n");
 250                         return -EINTR;
 251                 }
 252                 if (time_after(jiffies, orig_jiffies + HZ)) {
 253                         pr_debug("I2C: timeout\n");
 254                         return -EIO;
 255                 }
 256                 schedule();
 257         }
 258
 259         for (i = 0; ret >= 0 && i < num; i++) {
 260                 pmsg = &msgs[i];
 261                 pr_debug("Doing %s %d bytes to 0x%02x - %d of %d messages\n",
 262                          pmsg->flags & I2C_M_RD ? "read" : "write",
 263                          pmsg->len, pmsg->addr, i + 1, num);
 264                 if (pmsg->flags & I2C_M_RD)
 265                         ret =
 266                             mpc_read(i2c, pmsg->addr, pmsg->buf, pmsg->len, i);
 267                 else
 268                         ret =
 269                             mpc_write(i2c, pmsg->addr, pmsg->buf, pmsg->len, i);
 270         }
 271         mpc_i2c_stop(i2c);
 272         return (ret < 0) ? ret : num;
 273 }
 274
 275 static u32 mpc_functionality(struct i2c_adapter *adap)
 276 {
 277         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 278 }
 279
 280 static struct i2c_algorithm mpc_algo = {
 281         .name = "MPC algorithm",
 282         .id = I2C_ALGO_MPC107,
 283         .master_xfer = mpc_xfer,
 284         .functionality = mpc_functionality,
 285 };
 286
 287 static struct i2c_adapter mpc_ops = {
 288         .owner = THIS_MODULE,
 289         .name = "MPC adapter",
 290         .id = I2C_ALGO_MPC107 | I2C_HW_MPC107,
 291         .algo = &mpc_algo,
 292         .class = I2C_CLASS_HWMON,
 293         .timeout = 1,
 294         .retries = 1
 295 };
 296
 297 static int __devinit mpc_i2c_probe(struct ocp_device *ocp)
 298 {
 299         int result = 0;
 300         struct mpc_i2c *i2c;
 301
 302         if (!(i2c = kmalloc(sizeof(*i2c), GFP_KERNEL))) {
 303                 return -ENOMEM;
 304         }
 305         i2c->ocpdef = ocp->def;
 306         init_waitqueue_head(&i2c->queue);
 307
 308         if (!request_mem_region(ocp->def->paddr, MPC_I2C_REGION, "i2c-mpc")) {
 309                 printk(KERN_ERR "i2c-mpc - resource unavailable\n");
 310                 return -ENODEV;
 311         }
 312
 313         i2c->base = ioremap(ocp->def->paddr, MPC_I2C_REGION);
 314
 315         if (!i2c->base) {
 316                 printk(KERN_ERR "i2c-mpc - failed to map controller\n");
 317                 result = -ENOMEM;
 318                 goto fail_map;
 319         }
 320
 321         if (ocp->def->irq != OCP_IRQ_NA)
 322                 if ((result = request_irq(ocp->def->irq, mpc_i2c_isr,
 323                                           0, "i2c-mpc", i2c)) < 0) {
 324                         printk(KERN_ERR
 325                                "i2c-mpc - failed to attach interrupt\n");
 326                         goto fail_irq;
 327                 }
 328
 329         i2c->adap = mpc_ops;
 330         i2c_set_adapdata(&i2c->adap, i2c);
 331         if ((result = i2c_add_adapter(&i2c->adap)) < 0) {
 332                 printk(KERN_ERR "i2c-mpc - failed to add adapter\n");
 333                 goto fail_add;
 334         }
 335
 336         mpc_i2c_setclock(i2c);
 337         ocp_set_drvdata(ocp, i2c);
 338         return result;
 339
 340       fail_add:
 341         if (ocp->def->irq != OCP_IRQ_NA)
 342                 free_irq(ocp->def->irq, 0);
 343       fail_irq:
 344         iounmap(i2c->base);
 345       fail_map:
 346         release_mem_region(ocp->def->paddr, MPC_I2C_REGION);
 347         kfree(i2c);
 348         return result;
 349 }
 350 static void __devexit mpc_i2c_remove(struct ocp_device *ocp)
 351 {
 352         struct mpc_i2c *i2c = ocp_get_drvdata(ocp);
 353         ocp_set_drvdata(ocp, NULL);
 354         i2c_del_adapter(&i2c->adap);
 355
 356         if (ocp->def->irq != OCP_IRQ_NA)
 357                 free_irq(i2c->ocpdef->irq, i2c);
 358         iounmap(i2c->base);
 359         release_mem_region(i2c->ocpdef->paddr, MPC_I2C_REGION);
 360         kfree(i2c);
 361 }
 362
 363 static struct ocp_device_id mpc_iic_ids[] __devinitdata = {
 364         {.vendor = OCP_VENDOR_FREESCALE,.function = OCP_FUNC_IIC},
 365         {.vendor = OCP_VENDOR_INVALID}
 366 };
 367
 368 MODULE_DEVICE_TABLE(ocp, mpc_iic_ids);
 369
 370 static struct ocp_driver mpc_iic_driver = {
 371         .name = "iic",
 372         .id_table = mpc_iic_ids,
 373         .probe = mpc_i2c_probe,
 374         .remove = __devexit_p(mpc_i2c_remove)
 375 };
 376
 377 static int __init iic_init(void)
 378 {
 379         return ocp_register_driver(&mpc_iic_driver);
 380 }
 381
 382 static void __exit iic_exit(void)
 383 {
 384         ocp_unregister_driver(&mpc_iic_driver);
 385 }
 386
 387 module_init(iic_init);
 388 module_exit(iic_exit);
 389
 390 MODULE_AUTHOR("Adrian Cox <adrian@humboldt.co.uk>");
 391 MODULE_DESCRIPTION
 392     ("I2C-Bus adapter for MPC107 bridge and MPC824x/85xx/52xx processors");
 393 MODULE_LICENSE("GPL");