2 * linux/drivers/ide/pci/hpt34x.c Version 0.40 Sept 10, 2002
4 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
5 * May be copied or modified under the terms of the GNU General Public License
8 * 00:12.0 Unknown mass storage controller:
9 * Triones Technologies, Inc.
10 * Unknown device 0003 (rev 01)
12 * hde: UDMA 2 (0x0000 0x0002) (0x0000 0x0010)
13 * hdf: UDMA 2 (0x0002 0x0012) (0x0010 0x0030)
14 * hde: DMA 2 (0x0000 0x0002) (0x0000 0x0010)
15 * hdf: DMA 2 (0x0002 0x0012) (0x0010 0x0030)
16 * hdg: DMA 1 (0x0012 0x0052) (0x0030 0x0070)
17 * hdh: DMA 1 (0x0052 0x0252) (0x0070 0x00f0)
21 * Since there are two cards that report almost identically,
22 * the only discernable difference is the values reported in pcicmd.
23 * Booting-BIOS card or HPT363 :: pcicmd == 0x07
24 * Non-bootable card or HPT343 :: pcicmd == 0x05
27 #include <linux/config.h>
28 #include <linux/module.h>
29 #include <linux/types.h>
30 #include <linux/kernel.h>
31 #include <linux/delay.h>
32 #include <linux/timer.h>
34 #include <linux/ioport.h>
35 #include <linux/blkdev.h>
36 #include <linux/hdreg.h>
37 #include <linux/interrupt.h>
38 #include <linux/pci.h>
39 #include <linux/init.h>
40 #include <linux/ide.h>
47 #if defined(DISPLAY_HPT34X_TIMINGS) && defined(CONFIG_PROC_FS)
48 #include <linux/stat.h>
49 #include <linux/proc_fs.h>
51 static u8 hpt34x_proc = 0;
53 #define HPT34X_MAX_DEVS 8
54 static struct pci_dev *hpt34x_devs[HPT34X_MAX_DEVS];
55 static int n_hpt34x_devs;
57 static int hpt34x_get_info (char *buffer, char **addr, off_t offset, int count)
64 for (i = 0; i < n_hpt34x_devs; i++) {
65 struct pci_dev *dev = hpt34x_devs[i];
66 unsigned long bibma = pci_resource_start(dev, 4);
70 * at that point bibma+0x2 et bibma+0xa are byte registers
73 c0 = inb_p((u16)bibma + 0x02);
74 c1 = inb_p((u16)bibma + 0x0a);
75 p += sprintf(p, "\nController: %d\n", i);
76 p += sprintf(p, "--------------- Primary Channel "
77 "---------------- Secondary Channel "
79 p += sprintf(p, " %sabled "
81 (c0&0x80) ? "dis" : " en",
82 (c1&0x80) ? "dis" : " en");
83 p += sprintf(p, "--------------- drive0 --------- drive1 "
84 "-------- drive0 ---------- drive1 ------\n");
85 p += sprintf(p, "DMA enabled: %s %s"
87 (c0&0x20) ? "yes" : "no ",
88 (c0&0x40) ? "yes" : "no ",
89 (c1&0x20) ? "yes" : "no ",
90 (c1&0x40) ? "yes" : "no " );
92 p += sprintf(p, "UDMA\n");
93 p += sprintf(p, "DMA\n");
94 p += sprintf(p, "PIO\n");
96 p += sprintf(p, "\n");
98 /* p - buffer must be less than 4k! */
99 len = (p - buffer) - offset;
100 *addr = buffer + offset;
102 return len > count ? count : len;
104 #endif /* defined(DISPLAY_HPT34X_TIMINGS) && defined(CONFIG_PROC_FS) */
106 static u8 hpt34x_ratemask (ide_drive_t *drive)
111 static void hpt34x_clear_chipset (ide_drive_t *drive)
113 struct pci_dev *dev = HWIF(drive)->pci_dev;
114 u32 reg1 = 0, tmp1 = 0, reg2 = 0, tmp2 = 0;
116 pci_read_config_dword(dev, 0x44, ®1);
117 pci_read_config_dword(dev, 0x48, ®2);
118 tmp1 = ((0x00 << (3*drive->dn)) | (reg1 & ~(7 << (3*drive->dn))));
119 tmp2 = (reg2 & ~(0x11 << drive->dn));
120 pci_write_config_dword(dev, 0x44, tmp1);
121 pci_write_config_dword(dev, 0x48, tmp2);
124 static int hpt34x_tune_chipset (ide_drive_t *drive, u8 xferspeed)
126 struct pci_dev *dev = HWIF(drive)->pci_dev;
127 u8 speed = ide_rate_filter(hpt34x_ratemask(drive), xferspeed);
128 u32 reg1= 0, tmp1 = 0, reg2 = 0, tmp2 = 0;
129 u8 hi_speed, lo_speed;
131 SPLIT_BYTE(speed, hi_speed, lo_speed);
134 hi_speed = (hi_speed & 4) ? 0x01 : 0x10;
140 pci_read_config_dword(dev, 0x44, ®1);
141 pci_read_config_dword(dev, 0x48, ®2);
142 tmp1 = ((lo_speed << (3*drive->dn)) | (reg1 & ~(7 << (3*drive->dn))));
143 tmp2 = ((hi_speed << drive->dn) | reg2);
144 pci_write_config_dword(dev, 0x44, tmp1);
145 pci_write_config_dword(dev, 0x48, tmp2);
147 #if HPT343_DEBUG_DRIVE_INFO
148 printk("%s: %s drive%d (0x%04x 0x%04x) (0x%04x 0x%04x)" \
149 " (0x%02x 0x%02x)\n",
150 drive->name, ide_xfer_verbose(speed),
151 drive->dn, reg1, tmp1, reg2, tmp2,
153 #endif /* HPT343_DEBUG_DRIVE_INFO */
155 return(ide_config_drive_speed(drive, speed));
158 static void hpt34x_tune_drive (ide_drive_t *drive, u8 pio)
160 pio = ide_get_best_pio_mode(drive, pio, 5, NULL);
161 hpt34x_clear_chipset(drive);
162 (void) hpt34x_tune_chipset(drive, (XFER_PIO_0 + pio));
166 * This allows the configuration of ide_pci chipset registers
167 * for cards that learn about the drive's UDMA, DMA, PIO capabilities
168 * after the drive is reported by the OS. Initially for designed for
169 * HPT343 UDMA chipset by HighPoint|Triones Technologies, Inc.
172 static int config_chipset_for_dma (ide_drive_t *drive)
174 u8 speed = ide_dma_speed(drive, hpt34x_ratemask(drive));
179 hpt34x_clear_chipset(drive);
180 (void) hpt34x_tune_chipset(drive, speed);
181 return ide_dma_enable(drive);
184 static int hpt34x_config_drive_xfer_rate (ide_drive_t *drive)
186 ide_hwif_t *hwif = HWIF(drive);
187 struct hd_driveid *id = drive->id;
189 drive->init_speed = 0;
191 if (id && (id->capability & 1) && drive->autodma) {
192 /* Consult the list of known "bad" drives */
193 if (__ide_dma_bad_drive(drive))
195 if (id->field_valid & 4) {
196 if (id->dma_ultra & hwif->ultra_mask) {
197 /* Force if Capable UltraDMA */
198 int dma = config_chipset_for_dma(drive);
199 if ((id->field_valid & 2) && dma)
202 } else if (id->field_valid & 2) {
204 if ((id->dma_mword & hwif->mwdma_mask) ||
205 (id->dma_1word & hwif->swdma_mask)) {
206 /* Force if Capable regular DMA modes */
207 if (!config_chipset_for_dma(drive))
210 } else if (__ide_dma_good_drive(drive) &&
211 (id->eide_dma_time < 150)) {
212 /* Consult the list of known "good" drives */
213 if (!config_chipset_for_dma(drive))
218 #ifndef CONFIG_HPT34X_AUTODMA
219 return hwif->ide_dma_off_quietly(drive);
221 return hwif->ide_dma_on(drive);
223 } else if ((id->capability & 8) || (id->field_valid & 2)) {
226 hpt34x_tune_drive(drive, 255);
227 return hwif->ide_dma_off_quietly(drive);
229 /* IORDY not supported */
234 * If the BIOS does not set the IO base addaress to XX00, 343 will fail.
236 #define HPT34X_PCI_INIT_REG 0x80
238 static unsigned int __devinit init_chipset_hpt34x(struct pci_dev *dev, const char *name)
241 unsigned long hpt34xIoBase = pci_resource_start(dev, 4);
242 unsigned long hpt_addr[4] = { 0x20, 0x34, 0x28, 0x3c };
243 unsigned long hpt_addr_len[4] = { 7, 3, 7, 3 };
247 local_irq_save(flags);
249 pci_write_config_byte(dev, HPT34X_PCI_INIT_REG, 0x00);
250 pci_read_config_word(dev, PCI_COMMAND, &cmd);
252 if (cmd & PCI_COMMAND_MEMORY) {
253 if (pci_resource_start(dev, PCI_ROM_RESOURCE)) {
254 pci_write_config_byte(dev, PCI_ROM_ADDRESS,
255 dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
256 printk(KERN_INFO "HPT345: ROM enabled at 0x%08lx\n",
257 dev->resource[PCI_ROM_RESOURCE].start);
259 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xF0);
261 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20);
265 * Since 20-23 can be assigned and are R/W, we correct them.
267 pci_write_config_word(dev, PCI_COMMAND, cmd & ~PCI_COMMAND_IO);
269 dev->resource[i].start = (hpt34xIoBase + hpt_addr[i]);
270 dev->resource[i].end = dev->resource[i].start + hpt_addr_len[i];
271 dev->resource[i].flags = IORESOURCE_IO;
272 pci_write_config_dword(dev,
273 (PCI_BASE_ADDRESS_0 + (i * 4)),
274 dev->resource[i].start);
276 pci_write_config_word(dev, PCI_COMMAND, cmd);
278 local_irq_restore(flags);
280 #if defined(DISPLAY_HPT34X_TIMINGS) && defined(CONFIG_PROC_FS)
281 hpt34x_devs[n_hpt34x_devs++] = dev;
285 ide_pci_create_host_proc("hpt34x", hpt34x_get_info);
287 #endif /* DISPLAY_HPT34X_TIMINGS && CONFIG_PROC_FS */
292 static void __devinit init_hwif_hpt34x(ide_hwif_t *hwif)
298 hwif->tuneproc = &hpt34x_tune_drive;
299 hwif->speedproc = &hpt34x_tune_chipset;
301 hwif->drives[0].autotune = 1;
302 hwif->drives[1].autotune = 1;
304 pci_read_config_word(hwif->pci_dev, PCI_COMMAND, &pcicmd);
309 hwif->ultra_mask = 0x07;
310 hwif->mwdma_mask = 0x07;
311 hwif->swdma_mask = 0x07;
313 hwif->ide_dma_check = &hpt34x_config_drive_xfer_rate;
315 hwif->autodma = (pcicmd & PCI_COMMAND_MEMORY) ? 1 : 0;
316 hwif->drives[0].autodma = hwif->autodma;
317 hwif->drives[1].autodma = hwif->autodma;
320 static int __devinit hpt34x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
322 ide_pci_device_t *d = &hpt34x_chipsets[id->driver_data];
323 static char *chipset_names[] = {"HPT343", "HPT345"};
326 pci_read_config_word(dev, PCI_COMMAND, &pcicmd);
328 d->name = chipset_names[(pcicmd & PCI_COMMAND_MEMORY) ? 1 : 0];
329 d->bootable = (pcicmd & PCI_COMMAND_MEMORY) ? OFF_BOARD : NEVER_BOARD;
331 ide_setup_pci_device(dev, d);
335 static struct pci_device_id hpt34x_pci_tbl[] = {
336 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT343, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
339 MODULE_DEVICE_TABLE(pci, hpt34x_pci_tbl);
341 static struct pci_driver driver = {
342 .name = "HPT34x IDE",
343 .id_table = hpt34x_pci_tbl,
344 .probe = hpt34x_init_one,
347 static int hpt34x_ide_init(void)
349 return ide_pci_register_driver(&driver);
352 module_init(hpt34x_ide_init);
354 MODULE_AUTHOR("Andre Hedrick");
355 MODULE_DESCRIPTION("PCI driver module for Highpoint 34x IDE");
356 MODULE_LICENSE("GPL");