drivers/ide/pci/hpt366.c

   1 /*
   2  * linux/drivers/ide/pci/hpt366.c               Version 0.34    Sept 17, 2002
   3  *
   4  * Copyright (C) 1999-2003              Andre Hedrick <andre@linux-ide.org>
   5  * Portions Copyright (C) 2001          Sun Microsystems, Inc.
   6  *
   7  * Thanks to HighPoint Technologies for their assistance, and hardware.
   8  * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his
   9  * donation of an ABit BP6 mainboard, processor, and memory acellerated
  10  * development and support.
  11  *
  12  * Note that final HPT370 support was done by force extraction of GPL.
  13  *
  14  * - add function for getting/setting power status of drive
  15  * - the HPT370's state machine can get confused. reset it before each dma
  16  *   xfer to prevent that from happening.
  17  * - reset state engine whenever we get an error.
  18  * - check for busmaster state at end of dma.
  19  * - use new highpoint timings.
  20  * - detect bus speed using highpoint register.
  21  * - use pll if we don't have a clock table. added a 66MHz table that's
  22  *   just 2x the 33MHz table.
  23  * - removed turnaround. NOTE: we never want to switch between pll and
  24  *   pci clocks as the chip can glitch in those cases. the highpoint
  25  *   approved workaround slows everything down too much to be useful. in
  26  *   addition, we would have to serialize access to each chip.
  27  *      Adrian Sun <a.sun@sun.com>
  28  *
  29  * add drive timings for 66MHz PCI bus,
  30  * fix ATA Cable signal detection, fix incorrect /proc info
  31  * add /proc display for per-drive PIO/DMA/UDMA mode and
  32  * per-channel ATA-33/66 Cable detect.
  33  *      Duncan Laurie <void@sun.com>
  34  *
  35  * fixup /proc output for multiple controllers
  36  *      Tim Hockin <thockin@sun.com>
  37  *
  38  * On hpt366:
  39  * Reset the hpt366 on error, reset on dma
  40  * Fix disabling Fast Interrupt hpt366.
  41  *      Mike Waychison <crlf@sun.com>
  42  */
  43
  44
  45 #include <linux/config.h>
  46 #include <linux/types.h>
  47 #include <linux/module.h>
  48 #include <linux/kernel.h>
  49 #include <linux/delay.h>
  50 #include <linux/timer.h>
  51 #include <linux/mm.h>
  52 #include <linux/ioport.h>
  53 #include <linux/blkdev.h>
  54 #include <linux/hdreg.h>
  55
  56 #include <linux/interrupt.h>
  57 #include <linux/pci.h>
  58 #include <linux/init.h>
  59 #include <linux/ide.h>
  60
  61 #include <asm/uaccess.h>
  62 #include <asm/io.h>
  63 #include <asm/irq.h>
  64
  65 #include "hpt366.h"
  66
  67 #if defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS)
  68 #include <linux/stat.h>
  69 #include <linux/proc_fs.h>
  70 #endif  /* defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS) */
  71
  72 static unsigned int hpt_revision(struct pci_dev *dev);
  73 static unsigned int hpt_minimum_revision(struct pci_dev *dev, int revision);
  74
  75 #if defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS)
  76
  77 static u8 hpt366_proc = 0;
  78 static struct pci_dev *hpt_devs[HPT366_MAX_DEVS];
  79 static int n_hpt_devs;
  80
  81 static int hpt366_get_info (char *buffer, char **addr, off_t offset, int count)
  82 {
  83         char *p = buffer;
  84         char *chipset_nums[] = {"366", "366",  "368",
  85                                 "370", "370A", "372",
  86                                 "302", "371",  "374" };
  87         int i, len;
  88
  89         p += sprintf(p, "\n                             "
  90                 "HighPoint HPT366/368/370/372/374\n");
  91         for (i = 0; i < n_hpt_devs; i++) {
  92                 struct pci_dev *dev = hpt_devs[i];
  93                 unsigned long iobase = dev->resource[4].start;
  94                 u32 class_rev = hpt_revision(dev);
  95                 u8 c0, c1;
  96
  97                 p += sprintf(p, "\nController: %d\n", i);
  98                 p += sprintf(p, "Chipset: HPT%s\n", chipset_nums[class_rev]);
  99                 p += sprintf(p, "--------------- Primary Channel "
 100                                 "--------------- Secondary Channel "
 101                                 "--------------\n");
 102
 103                 /* get the bus master status registers */
 104                 c0 = inb(iobase + 0x2);
 105                 c1 = inb(iobase + 0xa);
 106                 p += sprintf(p, "Enabled:        %s"
 107                                 "                             %s\n",
 108                         (c0 & 0x80) ? "no" : "yes",
 109                         (c1 & 0x80) ? "no" : "yes");
 110 #if 0
 111                 if (hpt_minimum_revision(dev, 3)) {
 112                         u8 cbl;
 113                         cbl = inb(iobase + 0x7b);
 114                         outb(cbl | 1, iobase + 0x7b);
 115                         outb(cbl & ~1, iobase + 0x7b);
 116                         cbl = inb(iobase + 0x7a);
 117                         p += sprintf(p, "Cable:          ATA-%d"
 118                                         "                          ATA-%d\n",
 119                                 (cbl & 0x02) ? 33 : 66,
 120                                 (cbl & 0x01) ? 33 : 66);
 121                         p += sprintf(p, "\n");
 122                 }
 123 #endif
 124                 p += sprintf(p, "--------------- drive0 --------- drive1 "
 125                                 "------- drive0 ---------- drive1 -------\n");
 126                 p += sprintf(p, "DMA capable:    %s              %s"
 127                                 "            %s               %s\n",
 128                         (c0 & 0x20) ? "yes" : "no ",
 129                         (c0 & 0x40) ? "yes" : "no ",
 130                         (c1 & 0x20) ? "yes" : "no ",
 131                         (c1 & 0x40) ? "yes" : "no ");
 132
 133                 {
 134                         u8 c2, c3;
 135                         /* older revs don't have these registers mapped
 136                          * into io space */
 137                         pci_read_config_byte(dev, 0x43, &c0);
 138                         pci_read_config_byte(dev, 0x47, &c1);
 139                         pci_read_config_byte(dev, 0x4b, &c2);
 140                         pci_read_config_byte(dev, 0x4f, &c3);
 141
 142                         p += sprintf(p, "Mode:           %s             %s"
 143                                         "           %s              %s\n",
 144                                 (c0 & 0x10) ? "UDMA" : (c0 & 0x20) ? "DMA " :
 145                                         (c0 & 0x80) ? "PIO " : "off ",
 146                                 (c1 & 0x10) ? "UDMA" : (c1 & 0x20) ? "DMA " :
 147                                         (c1 & 0x80) ? "PIO " : "off ",
 148                                 (c2 & 0x10) ? "UDMA" : (c2 & 0x20) ? "DMA " :
 149                                         (c2 & 0x80) ? "PIO " : "off ",
 150                                 (c3 & 0x10) ? "UDMA" : (c3 & 0x20) ? "DMA " :
 151                                         (c3 & 0x80) ? "PIO " : "off ");
 152                 }
 153         }
 154         p += sprintf(p, "\n");
 155
 156         /* p - buffer must be less than 4k! */
 157         len = (p - buffer) - offset;
 158         *addr = buffer + offset;
 159
 160         return len > count ? count : len;
 161 }
 162 #endif  /* defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS) */
 163
 164 static u32 hpt_revision (struct pci_dev *dev)
 165 {
 166         u32 class_rev;
 167         pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
 168         class_rev &= 0xff;
 169
 170         switch(dev->device) {
 171                 case PCI_DEVICE_ID_TTI_HPT374:
 172                         class_rev = PCI_DEVICE_ID_TTI_HPT374; break;
 173                 case PCI_DEVICE_ID_TTI_HPT371:
 174                         class_rev = PCI_DEVICE_ID_TTI_HPT371; break;
 175                 case PCI_DEVICE_ID_TTI_HPT302:
 176                         class_rev = PCI_DEVICE_ID_TTI_HPT302; break;
 177                 case PCI_DEVICE_ID_TTI_HPT372:
 178                         class_rev = PCI_DEVICE_ID_TTI_HPT372; break;
 179                 default:
 180                         break;
 181         }
 182         return class_rev;
 183 }
 184
 185 static u32 hpt_minimum_revision (struct pci_dev *dev, int revision)
 186 {
 187         unsigned int class_rev = hpt_revision(dev);
 188         revision--;
 189         return ((int) (class_rev > revision) ? 1 : 0);
 190 }
 191
 192 static int check_in_drive_lists(ide_drive_t *drive, const char **list);
 193
 194 static u8 hpt3xx_ratemask (ide_drive_t *drive)
 195 {
 196         struct pci_dev *dev     = HWIF(drive)->pci_dev;
 197         u8 mode                 = 0;
 198
 199         if (hpt_minimum_revision(dev, 8)) {             /* HPT374 */
 200                 mode = (HPT374_ALLOW_ATA133_6) ? 4 : 3;
 201         } else if (hpt_minimum_revision(dev, 7)) {      /* HPT371 */
 202                 mode = (HPT371_ALLOW_ATA133_6) ? 4 : 3;
 203         } else if (hpt_minimum_revision(dev, 6)) {      /* HPT302 */
 204                 mode = (HPT302_ALLOW_ATA133_6) ? 4 : 3;
 205         } else if (hpt_minimum_revision(dev, 5)) {      /* HPT372 */
 206                 mode = (HPT372_ALLOW_ATA133_6) ? 4 : 3;
 207         } else if (hpt_minimum_revision(dev, 4)) {      /* HPT370A */
 208                 mode = (HPT370_ALLOW_ATA100_5) ? 3 : 2;
 209         } else if (hpt_minimum_revision(dev, 3)) {      /* HPT370 */
 210                 mode = (HPT370_ALLOW_ATA100_5) ? 3 : 2;
 211                 mode = (check_in_drive_lists(drive, bad_ata33)) ? 0 : mode;
 212         } else {                                /* HPT366 and HPT368 */
 213                 mode = (check_in_drive_lists(drive, bad_ata33)) ? 0 : 2;
 214         }
 215         if (!eighty_ninty_three(drive) && (mode))
 216                 mode = min(mode, (u8)1);
 217         return mode;
 218 }
 219
 220 static u8 hpt3xx_ratefilter (ide_drive_t *drive, u8 speed)
 221 {
 222         struct pci_dev *dev     = HWIF(drive)->pci_dev;
 223         u8 mode                 = hpt3xx_ratemask(drive);
 224
 225         if (drive->media != ide_disk)
 226                 return min(speed, (u8)XFER_PIO_4);
 227
 228         switch(mode) {
 229                 case 0x04:
 230                         speed = min(speed, (u8)XFER_UDMA_6);
 231                         break;
 232                 case 0x03:
 233                         speed = min(speed, (u8)XFER_UDMA_5);
 234                         if (hpt_minimum_revision(dev, 5))
 235                                 break;
 236                         if (check_in_drive_lists(drive, bad_ata100_5))
 237                                 speed = min(speed, (u8)XFER_UDMA_4);
 238                         break;
 239                 case 0x02:
 240                         speed = min(speed, (u8)XFER_UDMA_4);
 241         /*
 242          * CHECK ME, Does this need to be set to 5 ??
 243          */
 244                         if (hpt_minimum_revision(dev, 3))
 245                                 break;
 246                         if ((check_in_drive_lists(drive, bad_ata66_4)) ||
 247                             (!(HPT366_ALLOW_ATA66_4)))
 248                                 speed = min(speed, (u8)XFER_UDMA_3);
 249                         if ((check_in_drive_lists(drive, bad_ata66_3)) ||
 250                             (!(HPT366_ALLOW_ATA66_3)))
 251                                 speed = min(speed, (u8)XFER_UDMA_2);
 252                         break;
 253                 case 0x01:
 254                         speed = min(speed, (u8)XFER_UDMA_2);
 255         /*
 256          * CHECK ME, Does this need to be set to 5 ??
 257          */
 258                         if (hpt_minimum_revision(dev, 3))
 259                                 break;
 260                         if (check_in_drive_lists(drive, bad_ata33))
 261                                 speed = min(speed, (u8)XFER_MW_DMA_2);
 262                         break;
 263                 case 0x00:
 264                 default:
 265                         speed = min(speed, (u8)XFER_MW_DMA_2);
 266                         break;
 267         }
 268         return speed;
 269 }
 270
 271 static int check_in_drive_lists (ide_drive_t *drive, const char **list)
 272 {
 273         struct hd_driveid *id = drive->id;
 274
 275         if (quirk_drives == list) {
 276                 while (*list)
 277                         if (strstr(id->model, *list++))
 278                                 return 1;
 279         } else {
 280                 while (*list)
 281                         if (!strcmp(*list++,id->model))
 282                                 return 1;
 283         }
 284         return 0;
 285 }
 286
 287 static unsigned int pci_bus_clock_list (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
 288 {
 289         for ( ; chipset_table->xfer_speed ; chipset_table++)
 290                 if (chipset_table->xfer_speed == speed)
 291                         return chipset_table->chipset_settings;
 292         return chipset_table->chipset_settings;
 293 }
 294
 295 static int hpt36x_tune_chipset(ide_drive_t *drive, u8 xferspeed)
 296 {
 297         struct pci_dev *dev     = HWIF(drive)->pci_dev;
 298         u8 speed                = hpt3xx_ratefilter(drive, xferspeed);
 299 //      u8 speed                = ide_rate_filter(hpt3xx_ratemask(drive), xferspeed);
 300         u8 regtime              = (drive->select.b.unit & 0x01) ? 0x44 : 0x40;
 301         u8 regfast              = (HWIF(drive)->channel) ? 0x55 : 0x51;
 302         u8 drive_fast           = 0;
 303         u32 reg1 = 0, reg2      = 0;
 304
 305         /*
 306          * Disable the "fast interrupt" prediction.
 307          */
 308         pci_read_config_byte(dev, regfast, &drive_fast);
 309 #if 0
 310         if (drive_fast & 0x02)
 311                 pci_write_config_byte(dev, regfast, drive_fast & ~0x20);
 312 #else
 313         if (drive_fast & 0x80)
 314                 pci_write_config_byte(dev, regfast, drive_fast & ~0x80);
 315 #endif
 316
 317         reg2 = pci_bus_clock_list(speed,
 318                 (struct chipset_bus_clock_list_entry *) pci_get_drvdata(dev));
 319         /*
 320          * Disable on-chip PIO FIFO/buffer
 321          *  (to avoid problems handling I/O errors later)
 322          */
 323         pci_read_config_dword(dev, regtime, &reg1);
 324         if (speed >= XFER_MW_DMA_0) {
 325                 reg2 = (reg2 & ~0xc0000000) | (reg1 & 0xc0000000);
 326         } else {
 327                 reg2 = (reg2 & ~0x30070000) | (reg1 & 0x30070000);
 328         }
 329         reg2 &= ~0x80000000;
 330
 331         pci_write_config_dword(dev, regtime, reg2);
 332
 333         return ide_config_drive_speed(drive, speed);
 334 }
 335
 336 static int hpt370_tune_chipset(ide_drive_t *drive, u8 xferspeed)
 337 {
 338         struct pci_dev *dev = HWIF(drive)->pci_dev;
 339         u8 speed        = hpt3xx_ratefilter(drive, xferspeed);
 340 //      u8 speed        = ide_rate_filter(hpt3xx_ratemask(drive), xferspeed);
 341         u8 regfast      = (HWIF(drive)->channel) ? 0x55 : 0x51;
 342         u8 drive_pci    = 0x40 + (drive->dn * 4);
 343         u8 new_fast     = 0, drive_fast = 0;
 344         u32 list_conf   = 0, drive_conf = 0;
 345         u32 conf_mask   = (speed >= XFER_MW_DMA_0) ? 0xc0000000 : 0x30070000;
 346
 347         /*
 348          * Disable the "fast interrupt" prediction.
 349          * don't holdoff on interrupts. (== 0x01 despite what the docs say)
 350          */
 351         pci_read_config_byte(dev, regfast, &drive_fast);
 352         new_fast = drive_fast;
 353         if (new_fast & 0x02)
 354                 new_fast &= ~0x02;
 355
 356 #ifdef HPT_DELAY_INTERRUPT
 357         if (new_fast & 0x01)
 358                 new_fast &= ~0x01;
 359 #else
 360         if ((new_fast & 0x01) == 0)
 361                 new_fast |= 0x01;
 362 #endif
 363         if (new_fast != drive_fast)
 364                 pci_write_config_byte(dev, regfast, new_fast);
 365
 366         list_conf = pci_bus_clock_list(speed,
 367                                        (struct chipset_bus_clock_list_entry *)
 368                                        pci_get_drvdata(dev));
 369
 370         pci_read_config_dword(dev, drive_pci, &drive_conf);
 371         list_conf = (list_conf & ~conf_mask) | (drive_conf & conf_mask);
 372
 373         if (speed < XFER_MW_DMA_0) {
 374                 list_conf &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
 375         }
 376
 377         pci_write_config_dword(dev, drive_pci, list_conf);
 378
 379         return ide_config_drive_speed(drive, speed);
 380 }
 381
 382 static int hpt372_tune_chipset(ide_drive_t *drive, u8 xferspeed)
 383 {
 384         struct pci_dev *dev     = HWIF(drive)->pci_dev;
 385         u8 speed        = hpt3xx_ratefilter(drive, xferspeed);
 386 //      u8 speed        = ide_rate_filter(hpt3xx_ratemask(drive), xferspeed);
 387         u8 regfast      = (HWIF(drive)->channel) ? 0x55 : 0x51;
 388         u8 drive_fast   = 0, drive_pci = 0x40 + (drive->dn * 4);
 389         u32 list_conf   = 0, drive_conf = 0;
 390         u32 conf_mask   = (speed >= XFER_MW_DMA_0) ? 0xc0000000 : 0x30070000;
 391
 392         /*
 393          * Disable the "fast interrupt" prediction.
 394          * don't holdoff on interrupts. (== 0x01 despite what the docs say)
 395          */
 396         pci_read_config_byte(dev, regfast, &drive_fast);
 397         drive_fast &= ~0x07;
 398         pci_write_config_byte(dev, regfast, drive_fast);
 399
 400         list_conf = pci_bus_clock_list(speed,
 401                         (struct chipset_bus_clock_list_entry *)
 402                                         pci_get_drvdata(dev));
 403         pci_read_config_dword(dev, drive_pci, &drive_conf);
 404         list_conf = (list_conf & ~conf_mask) | (drive_conf & conf_mask);
 405         if (speed < XFER_MW_DMA_0)
 406                 list_conf &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
 407         pci_write_config_dword(dev, drive_pci, list_conf);
 408
 409         return ide_config_drive_speed(drive, speed);
 410 }
 411
 412 static int hpt3xx_tune_chipset (ide_drive_t *drive, u8 speed)
 413 {
 414         struct pci_dev *dev     = HWIF(drive)->pci_dev;
 415
 416         if (hpt_minimum_revision(dev, 8))
 417                 return hpt372_tune_chipset(drive, speed); /* not a typo */
 418 #if 0
 419         else if (hpt_minimum_revision(dev, 7))
 420                 hpt371_tune_chipset(drive, speed);
 421         else if (hpt_minimum_revision(dev, 6))
 422                 hpt302_tune_chipset(drive, speed);
 423 #endif
 424         else if (hpt_minimum_revision(dev, 5))
 425                 return hpt372_tune_chipset(drive, speed);
 426         else if (hpt_minimum_revision(dev, 3))
 427                 return hpt370_tune_chipset(drive, speed);
 428         else    /* hpt368: hpt_minimum_revision(dev, 2) */
 429                 return hpt36x_tune_chipset(drive, speed);
 430 }
 431
 432 static void hpt3xx_tune_drive (ide_drive_t *drive, u8 pio)
 433 {
 434         pio = ide_get_best_pio_mode(drive, 255, pio, NULL);
 435         (void) hpt3xx_tune_chipset(drive, (XFER_PIO_0 + pio));
 436 }
 437
 438 /*
 439  * This allows the configuration of ide_pci chipset registers
 440  * for cards that learn about the drive's UDMA, DMA, PIO capabilities
 441  * after the drive is reported by the OS.  Initially for designed for
 442  * HPT366 UDMA chipset by HighPoint|Triones Technologies, Inc.
 443  *
 444  * check_in_drive_lists(drive, bad_ata66_4)
 445  * check_in_drive_lists(drive, bad_ata66_3)
 446  * check_in_drive_lists(drive, bad_ata33)
 447  *
 448  */
 449 static int config_chipset_for_dma (ide_drive_t *drive)
 450 {
 451         u8 speed = ide_dma_speed(drive, hpt3xx_ratemask(drive));
 452
 453         if (!(speed))
 454                 return 0;
 455
 456         (void) hpt3xx_tune_chipset(drive, speed);
 457         return ide_dma_enable(drive);
 458 }
 459
 460 static int hpt3xx_quirkproc (ide_drive_t *drive)
 461 {
 462         return ((int) check_in_drive_lists(drive, quirk_drives));
 463 }
 464
 465 static void hpt3xx_intrproc (ide_drive_t *drive)
 466 {
 467         ide_hwif_t *hwif = HWIF(drive);
 468
 469         if (drive->quirk_list)
 470                 return;
 471         /* drives in the quirk_list may not like intr setups/cleanups */
 472         hwif->OUTB(drive->ctl|2, IDE_CONTROL_REG);
 473 }
 474
 475 static void hpt3xx_maskproc (ide_drive_t *drive, int mask)
 476 {
 477         struct pci_dev *dev = HWIF(drive)->pci_dev;
 478
 479         if (drive->quirk_list) {
 480                 if (hpt_minimum_revision(dev,3)) {
 481                         u8 reg5a = 0;
 482                         pci_read_config_byte(dev, 0x5a, &reg5a);
 483                         if (((reg5a & 0x10) >> 4) != mask)
 484                                 pci_write_config_byte(dev, 0x5a, mask ? (reg5a | 0x10) : (reg5a & ~0x10));
 485                 } else {
 486                         if (mask) {
 487                                 disable_irq(HWIF(drive)->irq);
 488                         } else {
 489                                 enable_irq(HWIF(drive)->irq);
 490                         }
 491                 }
 492         } else {
 493                 if (IDE_CONTROL_REG)
 494                         HWIF(drive)->OUTB(mask ? (drive->ctl | 2) :
 495                                                  (drive->ctl & ~2),
 496                                                  IDE_CONTROL_REG);
 497         }
 498 }
 499
 500 static int hpt366_config_drive_xfer_rate (ide_drive_t *drive)
 501 {
 502         ide_hwif_t *hwif        = HWIF(drive);
 503         struct hd_driveid *id   = drive->id;
 504
 505         drive->init_speed = 0;
 506
 507         if (id && (id->capability & 1) && drive->autodma) {
 508                 /* Consult the list of known "bad" drives */
 509                 if (__ide_dma_bad_drive(drive))
 510                         goto fast_ata_pio;
 511                 if (id->field_valid & 4) {
 512                         if (id->dma_ultra & hwif->ultra_mask) {
 513                                 /* Force if Capable UltraDMA */
 514                                 int dma = config_chipset_for_dma(drive);
 515                                 if ((id->field_valid & 2) && !dma)
 516                                         goto try_dma_modes;
 517                         }
 518                 } else if (id->field_valid & 2) {
 519 try_dma_modes:
 520                         if (id->dma_mword & hwif->mwdma_mask) {
 521                                 /* Force if Capable regular DMA modes */
 522                                 if (!config_chipset_for_dma(drive))
 523                                         goto no_dma_set;
 524                         }
 525                 } else if (__ide_dma_good_drive(drive) &&
 526                            (id->eide_dma_time < 150)) {
 527                         /* Consult the list of known "good" drives */
 528                         if (!config_chipset_for_dma(drive))
 529                                 goto no_dma_set;
 530                 } else {
 531                         goto fast_ata_pio;
 532                 }
 533                 return hwif->ide_dma_on(drive);
 534         } else if ((id->capability & 8) || (id->field_valid & 2)) {
 535 fast_ata_pio:
 536 no_dma_set:
 537                 hpt3xx_tune_drive(drive, 5);
 538                 return hwif->ide_dma_off_quietly(drive);
 539         }
 540         /* IORDY not supported */
 541         return 0;
 542 }
 543
 544 /*
 545  * This is specific to the HPT366 UDMA bios chipset
 546  * by HighPoint|Triones Technologies, Inc.
 547  */
 548 static int hpt366_ide_dma_lostirq (ide_drive_t *drive)
 549 {
 550         struct pci_dev *dev     = HWIF(drive)->pci_dev;
 551         u8 reg50h = 0, reg52h = 0, reg5ah = 0;
 552
 553         pci_read_config_byte(dev, 0x50, &reg50h);
 554         pci_read_config_byte(dev, 0x52, &reg52h);
 555         pci_read_config_byte(dev, 0x5a, &reg5ah);
 556         printk("%s: (%s)  reg50h=0x%02x, reg52h=0x%02x, reg5ah=0x%02x\n",
 557                 drive->name, __FUNCTION__, reg50h, reg52h, reg5ah);
 558         if (reg5ah & 0x10)
 559                 pci_write_config_byte(dev, 0x5a, reg5ah & ~0x10);
 560 #if 0
 561         /* how about we flush and reset, mmmkay? */
 562         pci_write_config_byte(dev, 0x51, 0x1F);
 563         /* fall through to a reset */
 564         case ide_dma_begin:
 565         case ide_dma_end:
 566         /* reset the chips state over and over.. */
 567         pci_write_config_byte(dev, 0x51, 0x13);
 568 #endif
 569         return __ide_dma_lostirq(drive);
 570 }
 571
 572 static void hpt370_clear_engine (ide_drive_t *drive)
 573 {
 574         u8 regstate = HWIF(drive)->channel ? 0x54 : 0x50;
 575         pci_write_config_byte(HWIF(drive)->pci_dev, regstate, 0x37);
 576         udelay(10);
 577 }
 578
 579 static int hpt370_ide_dma_begin (ide_drive_t *drive)
 580 {
 581 #ifdef HPT_RESET_STATE_ENGINE
 582         hpt370_clear_engine(drive);
 583 #endif
 584         return __ide_dma_begin(drive);
 585 }
 586
 587 static int hpt370_ide_dma_end (ide_drive_t *drive)
 588 {
 589         ide_hwif_t *hwif        = HWIF(drive);
 590         u8 dma_stat             = hwif->INB(hwif->dma_status);
 591
 592         if (dma_stat & 0x01) {
 593                 /* wait a little */
 594                 udelay(20);
 595                 dma_stat = hwif->INB(hwif->dma_status);
 596         }
 597         if ((dma_stat & 0x01) != 0)
 598                 /* fallthrough */
 599                 (void) HWIF(drive)->ide_dma_timeout(drive);
 600
 601         return __ide_dma_end(drive);
 602 }
 603
 604 static void hpt370_lostirq_timeout (ide_drive_t *drive)
 605 {
 606         ide_hwif_t *hwif        = HWIF(drive);
 607         u8 bfifo = 0, reginfo   = hwif->channel ? 0x56 : 0x52;
 608         u8 dma_stat = 0, dma_cmd = 0;
 609
 610         pci_read_config_byte(HWIF(drive)->pci_dev, reginfo, &bfifo);
 611         printk("%s: %d bytes in FIFO\n", drive->name, bfifo);
 612         hpt370_clear_engine(drive);
 613         /* get dma command mode */
 614         dma_cmd = hwif->INB(hwif->dma_command);
 615         /* stop dma */
 616         hwif->OUTB(dma_cmd & ~0x1, hwif->dma_command);
 617         dma_stat = hwif->INB(hwif->dma_status);
 618         /* clear errors */
 619         hwif->OUTB(dma_stat | 0x6, hwif->dma_status);
 620 }
 621
 622 static int hpt370_ide_dma_timeout (ide_drive_t *drive)
 623 {
 624         hpt370_lostirq_timeout(drive);
 625         hpt370_clear_engine(drive);
 626         return __ide_dma_timeout(drive);
 627 }
 628
 629 static int hpt370_ide_dma_lostirq (ide_drive_t *drive)
 630 {
 631         hpt370_lostirq_timeout(drive);
 632         hpt370_clear_engine(drive);
 633         return __ide_dma_lostirq(drive);
 634 }
 635
 636 /* returns 1 if DMA IRQ issued, 0 otherwise */
 637 static int hpt374_ide_dma_test_irq(ide_drive_t *drive)
 638 {
 639         ide_hwif_t *hwif        = HWIF(drive);
 640         u16 bfifo               = 0;
 641         u8 reginfo              = hwif->channel ? 0x56 : 0x52;
 642         u8 dma_stat;
 643
 644         pci_read_config_word(hwif->pci_dev, reginfo, &bfifo);
 645         if (bfifo & 0x1FF) {
 646 //              printk("%s: %d bytes in FIFO\n", drive->name, bfifo);
 647                 return 0;
 648         }
 649
 650         dma_stat = hwif->INB(hwif->dma_status);
 651         /* return 1 if INTR asserted */
 652         if ((dma_stat & 4) == 4)
 653                 return 1;
 654
 655         if (!drive->waiting_for_dma)
 656                 printk(KERN_WARNING "%s: (%s) called while not waiting\n",
 657                                 drive->name, __FUNCTION__);
 658         return 0;
 659 }
 660
 661 static int hpt374_ide_dma_end (ide_drive_t *drive)
 662 {
 663         struct pci_dev *dev     = HWIF(drive)->pci_dev;
 664         ide_hwif_t *hwif        = HWIF(drive);
 665         u8 msc_stat = 0, mscreg = hwif->channel ? 0x54 : 0x50;
 666         u8 bwsr_stat = 0, bwsr_mask = hwif->channel ? 0x02 : 0x01;
 667
 668         pci_read_config_byte(dev, 0x6a, &bwsr_stat);
 669         pci_read_config_byte(dev, mscreg, &msc_stat);
 670         if ((bwsr_stat & bwsr_mask) == bwsr_mask)
 671                 pci_write_config_byte(dev, mscreg, msc_stat|0x30);
 672         return __ide_dma_end(drive);
 673 }
 674
 675 /*
 676  * Since SUN Cobalt is attempting to do this operation, I should disclose
 677  * this has been a long time ago Thu Jul 27 16:40:57 2000 was the patch date
 678  * HOTSWAP ATA Infrastructure.
 679  */
 680
 681 static void hpt3xx_reset (ide_drive_t *drive)
 682 {
 683 #if 0
 684         unsigned long high_16   = pci_resource_start(HWIF(drive)->pci_dev, 4);
 685         u8 reset        = (HWIF(drive)->channel) ? 0x80 : 0x40;
 686         u8 reg59h       = 0;
 687
 688         pci_read_config_byte(HWIF(drive)->pci_dev, 0x59, &reg59h);
 689         pci_write_config_byte(HWIF(drive)->pci_dev, 0x59, reg59h|reset);
 690         pci_write_config_byte(HWIF(drive)->pci_dev, 0x59, reg59h);
 691 #endif
 692 }
 693
 694 static int hpt3xx_tristate (ide_drive_t * drive, int state)
 695 {
 696         ide_hwif_t *hwif        = HWIF(drive);
 697         struct pci_dev *dev     = hwif->pci_dev;
 698         u8 reg59h = 0, reset    = (hwif->channel) ? 0x80 : 0x40;
 699         u8 regXXh = 0, state_reg= (hwif->channel) ? 0x57 : 0x53;
 700
 701         if (!hwif)
 702                 return -EINVAL;
 703
 704 //      hwif->bus_state = state;
 705
 706         pci_read_config_byte(dev, 0x59, &reg59h);
 707         pci_read_config_byte(dev, state_reg, &regXXh);
 708
 709         if (state) {
 710                 (void) ide_do_reset(drive);
 711                 pci_write_config_byte(dev, state_reg, regXXh|0x80);
 712                 pci_write_config_byte(dev, 0x59, reg59h|reset);
 713         } else {
 714                 pci_write_config_byte(dev, 0x59, reg59h & ~(reset));
 715                 pci_write_config_byte(dev, state_reg, regXXh & ~(0x80));
 716                 (void) ide_do_reset(drive);
 717         }
 718         return 0;
 719 }
 720
 721 /*
 722  * set/get power state for a drive.
 723  * turning the power off does the following things:
 724  *   1) soft-reset the drive
 725  *   2) tri-states the ide bus
 726  *
 727  * when we turn things back on, we need to re-initialize things.
 728  */
 729 #define TRISTATE_BIT  0x8000
 730 static int hpt370_busproc(ide_drive_t * drive, int state)
 731 {
 732         ide_hwif_t *hwif        = HWIF(drive);
 733         struct pci_dev *dev     = hwif->pci_dev;
 734         u8 tristate = 0, resetmask = 0, bus_reg = 0;
 735         u16 tri_reg;
 736
 737         if (!hwif)
 738                 return -EINVAL;
 739
 740         hwif->bus_state = state;
 741
 742         if (hwif->channel) {
 743                 /* secondary channel */
 744                 tristate = 0x56;
 745                 resetmask = 0x80;
 746         } else {
 747                 /* primary channel */
 748                 tristate = 0x52;
 749                 resetmask = 0x40;
 750         }
 751
 752         /* grab status */
 753         pci_read_config_word(dev, tristate, &tri_reg);
 754         pci_read_config_byte(dev, 0x59, &bus_reg);
 755
 756         /* set the state. we don't set it if we don't need to do so.
 757          * make sure that the drive knows that it has failed if it's off */
 758         switch (state) {
 759         case BUSSTATE_ON:
 760                 hwif->drives[0].failures = 0;
 761                 hwif->drives[1].failures = 0;
 762                 if ((bus_reg & resetmask) == 0)
 763                         return 0;
 764                 tri_reg &= ~TRISTATE_BIT;
 765                 bus_reg &= ~resetmask;
 766                 break;
 767         case BUSSTATE_OFF:
 768                 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
 769                 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
 770                 if ((tri_reg & TRISTATE_BIT) == 0 && (bus_reg & resetmask))
 771                         return 0;
 772                 tri_reg &= ~TRISTATE_BIT;
 773                 bus_reg |= resetmask;
 774                 break;
 775         case BUSSTATE_TRISTATE:
 776                 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
 777                 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
 778                 if ((tri_reg & TRISTATE_BIT) && (bus_reg & resetmask))
 779                         return 0;
 780                 tri_reg |= TRISTATE_BIT;
 781                 bus_reg |= resetmask;
 782                 break;
 783         }
 784         pci_write_config_byte(dev, 0x59, bus_reg);
 785         pci_write_config_word(dev, tristate, tri_reg);
 786
 787         return 0;
 788 }
 789
 790 static int __devinit init_hpt37x(struct pci_dev *dev)
 791 {
 792         int adjust, i;
 793         u16 freq;
 794         u32 pll;
 795         u8 reg5bh;
 796
 797 #if 1
 798         u8 reg5ah = 0;
 799         pci_read_config_byte(dev, 0x5a, &reg5ah);
 800         /* interrupt force enable */
 801         pci_write_config_byte(dev, 0x5a, (reg5ah & ~0x10));
 802 #endif
 803
 804         /*
 805          * default to pci clock. make sure MA15/16 are set to output
 806          * to prevent drives having problems with 40-pin cables.
 807          */
 808         pci_write_config_byte(dev, 0x5b, 0x23);
 809
 810         /*
 811          * set up the PLL. we need to adjust it so that it's stable.
 812          * freq = Tpll * 192 / Tpci
 813          */
 814         pci_read_config_word(dev, 0x78, &freq);
 815         freq &= 0x1FF;
 816         if (freq < 0xa0) {
 817                 pll = F_LOW_PCI_33;
 818                 if (hpt_minimum_revision(dev,8))
 819                         pci_set_drvdata(dev, (void *) thirty_three_base_hpt374);
 820                 else if (hpt_minimum_revision(dev,5))
 821                         pci_set_drvdata(dev, (void *) thirty_three_base_hpt372);
 822                 else if (hpt_minimum_revision(dev,4))
 823                         pci_set_drvdata(dev, (void *) thirty_three_base_hpt370a);
 824                 else
 825                         pci_set_drvdata(dev, (void *) thirty_three_base_hpt370);
 826                 printk("HPT37X: using 33MHz PCI clock\n");
 827         } else if (freq < 0xb0) {
 828                 pll = F_LOW_PCI_40;
 829         } else if (freq < 0xc8) {
 830                 pll = F_LOW_PCI_50;
 831                 if (hpt_minimum_revision(dev,8))
 832                         pci_set_drvdata(dev, NULL);
 833                 else if (hpt_minimum_revision(dev,5))
 834                         pci_set_drvdata(dev, (void *) fifty_base_hpt372);
 835                 else if (hpt_minimum_revision(dev,4))
 836                         pci_set_drvdata(dev, (void *) fifty_base_hpt370a);
 837                 else
 838                         pci_set_drvdata(dev, (void *) fifty_base_hpt370a);
 839                 printk("HPT37X: using 50MHz PCI clock\n");
 840         } else {
 841                 pll = F_LOW_PCI_66;
 842                 if (hpt_minimum_revision(dev,8))
 843                 {
 844                         printk(KERN_ERR "HPT37x: 66MHz timings are not supported.\n");
 845                         pci_set_drvdata(dev, NULL);
 846                 }
 847                 else if (hpt_minimum_revision(dev,5))
 848                         pci_set_drvdata(dev, (void *) sixty_six_base_hpt372);
 849                 else if (hpt_minimum_revision(dev,4))
 850                         pci_set_drvdata(dev, (void *) sixty_six_base_hpt370a);
 851                 else
 852                         pci_set_drvdata(dev, (void *) sixty_six_base_hpt370);
 853                 printk("HPT37X: using 66MHz PCI clock\n");
 854         }
 855
 856         /*
 857          * only try the pll if we don't have a table for the clock
 858          * speed that we're running at. NOTE: the internal PLL will
 859          * result in slow reads when using a 33MHz PCI clock. we also
 860          * don't like to use the PLL because it will cause glitches
 861          * on PRST/SRST when the HPT state engine gets reset.
 862          */
 863         if (pci_get_drvdata(dev))
 864                 goto init_hpt37X_done;
 865
 866         /*
 867          * adjust PLL based upon PCI clock, enable it, and wait for
 868          * stabilization.
 869          */
 870         adjust = 0;
 871         freq = (pll < F_LOW_PCI_50) ? 2 : 4;
 872         while (adjust++ < 6) {
 873                 pci_write_config_dword(dev, 0x5c, (freq + pll) << 16 |
 874                                        pll | 0x100);
 875
 876                 /* wait for clock stabilization */
 877                 for (i = 0; i < 0x50000; i++) {
 878                         pci_read_config_byte(dev, 0x5b, &reg5bh);
 879                         if (reg5bh & 0x80) {
 880                                 /* spin looking for the clock to destabilize */
 881                                 for (i = 0; i < 0x1000; ++i) {
 882                                         pci_read_config_byte(dev, 0x5b,
 883                                                              &reg5bh);
 884                                         if ((reg5bh & 0x80) == 0)
 885                                                 goto pll_recal;
 886                                 }
 887                                 pci_read_config_dword(dev, 0x5c, &pll);
 888                                 pci_write_config_dword(dev, 0x5c,
 889                                                        pll & ~0x100);
 890                                 pci_write_config_byte(dev, 0x5b, 0x21);
 891                                 if (hpt_minimum_revision(dev,8))
 892                                         pci_set_drvdata(dev, (void *) fifty_base_hpt370a);
 893                                 else if (hpt_minimum_revision(dev,5))
 894                                         pci_set_drvdata(dev, (void *) fifty_base_hpt372);
 895                                 else if (hpt_minimum_revision(dev,4))
 896                                         pci_set_drvdata(dev, (void *) fifty_base_hpt370a);
 897                                 else
 898                                         pci_set_drvdata(dev, (void *) fifty_base_hpt370a);
 899                                 printk("HPT37X: using 50MHz internal PLL\n");
 900                                 goto init_hpt37X_done;
 901                         }
 902                 }
 903 pll_recal:
 904                 if (adjust & 1)
 905                         pll -= (adjust >> 1);
 906                 else
 907                         pll += (adjust >> 1);
 908         }
 909
 910 init_hpt37X_done:
 911         /* reset state engine */
 912         pci_write_config_byte(dev, 0x50, 0x37);
 913         pci_write_config_byte(dev, 0x54, 0x37);
 914         udelay(100);
 915         return 0;
 916 }
 917
 918 static int __devinit init_hpt366(struct pci_dev *dev)
 919 {
 920         u32 reg1        = 0;
 921         u8 drive_fast   = 0;
 922
 923         /*
 924          * Disable the "fast interrupt" prediction.
 925          */
 926         pci_read_config_byte(dev, 0x51, &drive_fast);
 927         if (drive_fast & 0x80)
 928                 pci_write_config_byte(dev, 0x51, drive_fast & ~0x80);
 929         pci_read_config_dword(dev, 0x40, &reg1);
 930
 931         /* detect bus speed by looking at control reg timing: */
 932         switch((reg1 >> 8) & 7) {
 933                 case 5:
 934                         pci_set_drvdata(dev, (void *) forty_base_hpt366);
 935                         break;
 936                 case 9:
 937                         pci_set_drvdata(dev, (void *) twenty_five_base_hpt366);
 938                         break;
 939                 case 7:
 940                 default:
 941                         pci_set_drvdata(dev, (void *) thirty_three_base_hpt366);
 942                         break;
 943         }
 944
 945         if (!pci_get_drvdata(dev))
 946         {
 947                 printk(KERN_ERR "hpt366: unknown bus timing.\n");
 948                 pci_set_drvdata(dev, NULL);
 949         }
 950         return 0;
 951 }
 952
 953 static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const char *name)
 954 {
 955         int ret = 0;
 956         u8 test = 0;
 957
 958         if (dev->resource[PCI_ROM_RESOURCE].start)
 959                 pci_write_config_byte(dev, PCI_ROM_ADDRESS,
 960                         dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
 961
 962         pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &test);
 963         if (test != (L1_CACHE_BYTES / 4))
 964                 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE,
 965                         (L1_CACHE_BYTES / 4));
 966
 967         pci_read_config_byte(dev, PCI_LATENCY_TIMER, &test);
 968         if (test != 0x78)
 969                 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
 970
 971         pci_read_config_byte(dev, PCI_MIN_GNT, &test);
 972         if (test != 0x08)
 973                 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
 974
 975         pci_read_config_byte(dev, PCI_MAX_LAT, &test);
 976         if (test != 0x08)
 977                 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
 978
 979         if (hpt_minimum_revision(dev, 3)) {
 980                 ret = init_hpt37x(dev);
 981         } else {
 982                 ret =init_hpt366(dev);
 983         }
 984         if (ret)
 985                 return ret;
 986
 987 #if defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS)
 988         hpt_devs[n_hpt_devs++] = dev;
 989
 990         if (!hpt366_proc) {
 991                 hpt366_proc = 1;
 992                 ide_pci_create_host_proc("hpt366", hpt366_get_info);
 993         }
 994 #endif /* DISPLAY_HPT366_TIMINGS && CONFIG_PROC_FS */
 995
 996         return dev->irq;
 997 }
 998
 999 static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
1000 {
1001         struct pci_dev *dev             = hwif->pci_dev;
1002         u8 ata66 = 0, regmask           = (hwif->channel) ? 0x01 : 0x02;
1003
1004         hwif->tuneproc                  = &hpt3xx_tune_drive;
1005         hwif->speedproc                 = &hpt3xx_tune_chipset;
1006         hwif->quirkproc                 = &hpt3xx_quirkproc;
1007         hwif->intrproc                  = &hpt3xx_intrproc;
1008         hwif->maskproc                  = &hpt3xx_maskproc;
1009
1010         /*
1011          * The HPT37x uses the CBLID pins as outputs for MA15/MA16
1012          * address lines to access an external eeprom.  To read valid
1013          * cable detect state the pins must be enabled as inputs.
1014          */
1015         if (hpt_minimum_revision(dev, 8) && PCI_FUNC(dev->devfn) & 1) {
1016                 /*
1017                  * HPT374 PCI function 1
1018                  * - set bit 15 of reg 0x52 to enable TCBLID as input
1019                  * - set bit 15 of reg 0x56 to enable FCBLID as input
1020                  */
1021                 u16 mcr3, mcr6;
1022                 pci_read_config_word(dev, 0x52, &mcr3);
1023                 pci_read_config_word(dev, 0x56, &mcr6);
1024                 pci_write_config_word(dev, 0x52, mcr3 | 0x8000);
1025                 pci_write_config_word(dev, 0x56, mcr6 | 0x8000);
1026                 /* now read cable id register */
1027                 pci_read_config_byte(dev, 0x5a, &ata66);
1028                 pci_write_config_word(dev, 0x52, mcr3);
1029                 pci_write_config_word(dev, 0x56, mcr6);
1030         } else if (hpt_minimum_revision(dev, 3)) {
1031                 /*
1032                  * HPT370/372 and 374 pcifn 0
1033                  * - clear bit 0 of 0x5b to enable P/SCBLID as inputs
1034                  */
1035                 u8 scr2;
1036                 pci_read_config_byte(dev, 0x5b, &scr2);
1037                 pci_write_config_byte(dev, 0x5b, scr2 & ~1);
1038                 /* now read cable id register */
1039                 pci_read_config_byte(dev, 0x5a, &ata66);
1040                 pci_write_config_byte(dev, 0x5b, scr2);
1041         } else {
1042                 pci_read_config_byte(dev, 0x5a, &ata66);
1043         }
1044
1045 #ifdef DEBUG
1046         printk("HPT366: reg5ah=0x%02x ATA-%s Cable Port%d\n",
1047                 ata66, (ata66 & regmask) ? "33" : "66",
1048                 PCI_FUNC(hwif->pci_dev->devfn));
1049 #endif /* DEBUG */
1050
1051 #ifdef HPT_SERIALIZE_IO
1052         /* serialize access to this device */
1053         if (hwif->mate)
1054                 hwif->serialized = hwif->mate->serialized = 1;
1055 #endif
1056
1057         if (hpt_minimum_revision(dev,3)) {
1058                 u8 reg5ah = 0;
1059                         pci_write_config_byte(dev, 0x5a, reg5ah & ~0x10);
1060                 /*
1061                  * set up ioctl for power status.
1062                  * note: power affects both
1063                  * drives on each channel
1064                  */
1065                 hwif->resetproc = &hpt3xx_reset;
1066                 hwif->busproc   = &hpt370_busproc;
1067 //              hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
1068         } else if (hpt_minimum_revision(dev,2)) {
1069                 hwif->resetproc = &hpt3xx_reset;
1070                 hwif->busproc   = &hpt3xx_tristate;
1071         } else {
1072                 hwif->resetproc = &hpt3xx_reset;
1073                 hwif->busproc   = &hpt3xx_tristate;
1074         }
1075
1076         if (!hwif->dma_base) {
1077                 hwif->drives[0].autotune = 1;
1078                 hwif->drives[1].autotune = 1;
1079                 return;
1080         }
1081
1082         hwif->ultra_mask = 0x7f;
1083         hwif->mwdma_mask = 0x07;
1084
1085         if (!(hwif->udma_four))
1086                 hwif->udma_four = ((ata66 & regmask) ? 0 : 1);
1087         hwif->ide_dma_check = &hpt366_config_drive_xfer_rate;
1088
1089         if (hpt_minimum_revision(dev,8)) {
1090                 hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq;
1091                 hwif->ide_dma_end = &hpt374_ide_dma_end;
1092         } else if (hpt_minimum_revision(dev,5)) {
1093                 hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq;
1094                 hwif->ide_dma_end = &hpt374_ide_dma_end;
1095         } else if (hpt_minimum_revision(dev,3)) {
1096                 hwif->ide_dma_begin = &hpt370_ide_dma_begin;
1097                 hwif->ide_dma_end = &hpt370_ide_dma_end;
1098                 hwif->ide_dma_timeout = &hpt370_ide_dma_timeout;
1099                 hwif->ide_dma_lostirq = &hpt370_ide_dma_lostirq;
1100         } else if (hpt_minimum_revision(dev,2))
1101                 hwif->ide_dma_lostirq = &hpt366_ide_dma_lostirq;
1102         else
1103                 hwif->ide_dma_lostirq = &hpt366_ide_dma_lostirq;
1104
1105         if (!noautodma)
1106                 hwif->autodma = 1;
1107         hwif->drives[0].autodma = hwif->autodma;
1108         hwif->drives[1].autodma = hwif->autodma;
1109 }
1110
1111 static void __devinit init_dma_hpt366(ide_hwif_t *hwif, unsigned long dmabase)
1112 {
1113         u8 masterdma    = 0, slavedma = 0;
1114         u8 dma_new      = 0, dma_old = 0;
1115         u8 primary      = hwif->channel ? 0x4b : 0x43;
1116         u8 secondary    = hwif->channel ? 0x4f : 0x47;
1117         unsigned long flags;
1118
1119         if (!dmabase)
1120                 return;
1121
1122         if(pci_get_drvdata(hwif->pci_dev) == NULL)
1123         {
1124                 printk(KERN_WARNING "hpt: no known IDE timings, disabling DMA.\n");
1125                 return;
1126         }
1127
1128         dma_old = hwif->INB(dmabase+2);
1129
1130         local_irq_save(flags);
1131
1132         dma_new = dma_old;
1133         pci_read_config_byte(hwif->pci_dev, primary, &masterdma);
1134         pci_read_config_byte(hwif->pci_dev, secondary, &slavedma);
1135
1136         if (masterdma & 0x30)   dma_new |= 0x20;
1137         if (slavedma & 0x30)    dma_new |= 0x40;
1138         if (dma_new != dma_old)
1139                 hwif->OUTB(dma_new, dmabase+2);
1140
1141         local_irq_restore(flags);
1142
1143         ide_setup_dma(hwif, dmabase, 8);
1144 }
1145
1146 static void __devinit init_setup_hpt374(struct pci_dev *dev, ide_pci_device_t *d)
1147 {
1148         struct pci_dev *findev = NULL;
1149
1150         if (PCI_FUNC(dev->devfn) & 1)
1151                 return;
1152
1153         while ((findev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, findev)) != NULL) {
1154                 if ((findev->vendor == dev->vendor) &&
1155                     (findev->device == dev->device) &&
1156                     ((findev->devfn - dev->devfn) == 1) &&
1157                     (PCI_FUNC(findev->devfn) & 1)) {
1158                         if (findev->irq != dev->irq) {
1159                                 /* FIXME: we need a core pci_set_interrupt() */
1160                                 findev->irq = dev->irq;
1161                                 printk(KERN_WARNING "%s: pci-config space interrupt "
1162                                         "fixed.\n", d->name);
1163                         }
1164                         ide_setup_pci_devices(dev, findev, d);
1165                         return;
1166                 }
1167         }
1168         ide_setup_pci_device(dev, d);
1169 }
1170
1171 static void __devinit init_setup_hpt37x(struct pci_dev *dev, ide_pci_device_t *d)
1172 {
1173         ide_setup_pci_device(dev, d);
1174 }
1175
1176 static void __devinit init_setup_hpt366(struct pci_dev *dev, ide_pci_device_t *d)
1177 {
1178         struct pci_dev *findev = NULL;
1179         u8 pin1 = 0, pin2 = 0;
1180         unsigned int class_rev;
1181         char *chipset_names[] = {"HPT366", "HPT366",  "HPT368",
1182                                  "HPT370", "HPT370A", "HPT372"};
1183
1184         if (PCI_FUNC(dev->devfn) & 1)
1185                 return;
1186
1187         pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
1188         class_rev &= 0xff;
1189
1190         strcpy(d->name, chipset_names[class_rev]);
1191
1192         switch(class_rev) {
1193                 case 5:
1194                 case 4:
1195                 case 3: ide_setup_pci_device(dev, d);
1196                         return;
1197                 default:        break;
1198         }
1199
1200         d->channels = 1;
1201
1202         pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1);
1203         while ((findev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, findev)) != NULL) {
1204                 if ((findev->vendor == dev->vendor) &&
1205                     (findev->device == dev->device) &&
1206                     ((findev->devfn - dev->devfn) == 1) &&
1207                     (PCI_FUNC(findev->devfn) & 1)) {
1208                         pci_read_config_byte(findev, PCI_INTERRUPT_PIN, &pin2);
1209                         if ((pin1 != pin2) && (dev->irq == findev->irq)) {
1210                                 d->bootable = ON_BOARD;
1211                                 printk("%s: onboard version of chipset, "
1212                                         "pin1=%d pin2=%d\n", d->name,
1213                                         pin1, pin2);
1214                         }
1215                         ide_setup_pci_devices(dev, findev, d);
1216                         return;
1217                 }
1218         }
1219         ide_setup_pci_device(dev, d);
1220 }
1221
1222
1223 /**
1224  *      hpt366_init_one -       called when an HPT366 is found
1225  *      @dev: the hpt366 device
1226  *      @id: the matching pci id
1227  *
1228  *      Called when the PCI registration layer (or the IDE initialization)
1229  *      finds a device matching our IDE device tables.
1230  */
1231
1232 static int __devinit hpt366_init_one(struct pci_dev *dev, const struct pci_device_id *id)
1233 {
1234         ide_pci_device_t *d = &hpt366_chipsets[id->driver_data];
1235
1236         d->init_setup(dev, d);
1237         return 0;
1238 }
1239
1240 static struct pci_device_id hpt366_pci_tbl[] = {
1241         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT366, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1242         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
1243         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT302, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
1244         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
1245         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT374, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
1246         { 0, },
1247 };
1248 MODULE_DEVICE_TABLE(pci, hpt366_pci_tbl);
1249
1250 static struct pci_driver driver = {
1251         .name           = "HPT366 IDE",
1252         .id_table       = hpt366_pci_tbl,
1253         .probe          = hpt366_init_one,
1254 };
1255
1256 static int hpt366_ide_init(void)
1257 {
1258         return ide_pci_register_driver(&driver);
1259 }
1260
1261 module_init(hpt366_ide_init);
1262
1263 MODULE_AUTHOR("Andre Hedrick");
1264 MODULE_DESCRIPTION("PCI driver module for Highpoint HPT366 IDE");
1265 MODULE_LICENSE("GPL");