drivers/ide/pci/hpt366.c

   1 /*
   2  * linux/drivers/ide/pci/hpt366.c               Version 0.36    April 25, 2003
   3  *
   4  * Copyright (C) 1999-2003              Andre Hedrick <andre@linux-ide.org>
   5  * Portions Copyright (C) 2001          Sun Microsystems, Inc.
   6  * Portions Copyright (C) 2003          Red Hat Inc
   7  *
   8  * Thanks to HighPoint Technologies for their assistance, and hardware.
   9  * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his
  10  * donation of an ABit BP6 mainboard, processor, and memory acellerated
  11  * development and support.
  12  *
  13  *
  14  * Highpoint have their own driver (source except for the raid part)
  15  * available from http://www.highpoint-tech.com/hpt3xx-opensource-v131.tgz
  16  * This may be useful to anyone wanting to work on the mainstream hpt IDE.
  17  *
  18  * Note that final HPT370 support was done by force extraction of GPL.
  19  *
  20  * - add function for getting/setting power status of drive
  21  * - the HPT370's state machine can get confused. reset it before each dma
  22  *   xfer to prevent that from happening.
  23  * - reset state engine whenever we get an error.
  24  * - check for busmaster state at end of dma.
  25  * - use new highpoint timings.
  26  * - detect bus speed using highpoint register.
  27  * - use pll if we don't have a clock table. added a 66MHz table that's
  28  *   just 2x the 33MHz table.
  29  * - removed turnaround. NOTE: we never want to switch between pll and
  30  *   pci clocks as the chip can glitch in those cases. the highpoint
  31  *   approved workaround slows everything down too much to be useful. in
  32  *   addition, we would have to serialize access to each chip.
  33  *      Adrian Sun <a.sun@sun.com>
  34  *
  35  * add drive timings for 66MHz PCI bus,
  36  * fix ATA Cable signal detection, fix incorrect /proc info
  37  * add /proc display for per-drive PIO/DMA/UDMA mode and
  38  * per-channel ATA-33/66 Cable detect.
  39  *      Duncan Laurie <void@sun.com>
  40  *
  41  * fixup /proc output for multiple controllers
  42  *      Tim Hockin <thockin@sun.com>
  43  *
  44  * On hpt366:
  45  * Reset the hpt366 on error, reset on dma
  46  * Fix disabling Fast Interrupt hpt366.
  47  *      Mike Waychison <crlf@sun.com>
  48  *
  49  * Added support for 372N clocking and clock switching. The 372N needs
  50  * different clocks on read/write. This requires overloading rw_disk and
  51  * other deeply crazy things. Thanks to <http://www.hoerstreich.de> for
  52  * keeping me sane.
  53  *              Alan Cox <alan@redhat.com>
  54  *
  55  */
  56
  57
  58 #include <linux/config.h>
  59 #include <linux/types.h>
  60 #include <linux/module.h>
  61 #include <linux/kernel.h>
  62 #include <linux/delay.h>
  63 #include <linux/timer.h>
  64 #include <linux/mm.h>
  65 #include <linux/ioport.h>
  66 #include <linux/blkdev.h>
  67 #include <linux/hdreg.h>
  68
  69 #include <linux/interrupt.h>
  70 #include <linux/pci.h>
  71 #include <linux/init.h>
  72 #include <linux/ide.h>
  73
  74 #include <asm/uaccess.h>
  75 #include <asm/io.h>
  76 #include <asm/irq.h>
  77
  78 #include "hpt366.h"
  79
  80 /*
  81  *      Hold all the highpoint quirks and revision information in one
  82  *      place.
  83  */
  84
  85 struct hpt_info
  86 {
  87         u8 max_mode;            /* Speeds allowed */
  88         int revision;           /* Chipset revision */
  89         int flags;              /* Chipset properties */
  90 #define PLL_MODE        1
  91 #define IS_372N         2
  92                                 /* Speed table */
  93         struct chipset_bus_clock_list_entry *speed;
  94 };
  95
  96 /*
  97  *      This wants fixing so that we do everything not by classrev
  98  *      (which breaks on the newest chips) but by creating an
  99  *      enumeration of chip variants and using that
 100  */
 101
 102 static __devinit u32 hpt_revision (struct pci_dev *dev)
 103 {
 104         u32 class_rev;
 105         pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
 106         class_rev &= 0xff;
 107
 108         switch(dev->device) {
 109                 /* Remap new 372N onto 372 */
 110                 case PCI_DEVICE_ID_TTI_HPT372N:
 111                         class_rev = PCI_DEVICE_ID_TTI_HPT372; break;
 112                 case PCI_DEVICE_ID_TTI_HPT374:
 113                         class_rev = PCI_DEVICE_ID_TTI_HPT374; break;
 114                 case PCI_DEVICE_ID_TTI_HPT371:
 115                         class_rev = PCI_DEVICE_ID_TTI_HPT371; break;
 116                 case PCI_DEVICE_ID_TTI_HPT302:
 117                         class_rev = PCI_DEVICE_ID_TTI_HPT302; break;
 118                 case PCI_DEVICE_ID_TTI_HPT372:
 119                         class_rev = PCI_DEVICE_ID_TTI_HPT372; break;
 120                 default:
 121                         break;
 122         }
 123         return class_rev;
 124 }
 125
 126 static int check_in_drive_lists(ide_drive_t *drive, const char **list);
 127
 128 static u8 hpt3xx_ratemask (ide_drive_t *drive)
 129 {
 130         ide_hwif_t *hwif        = drive->hwif;
 131         struct hpt_info *info   = ide_get_hwifdata(hwif);
 132         u8 mode                 = 0;
 133
 134         /* FIXME: TODO - move this to set info->mode once at boot */
 135
 136         if (info->revision >= 8) {              /* HPT374 */
 137                 mode = (HPT374_ALLOW_ATA133_6) ? 4 : 3;
 138         } else if (info->revision >= 7) {       /* HPT371 */
 139                 mode = (HPT371_ALLOW_ATA133_6) ? 4 : 3;
 140         } else if (info->revision >= 6) {       /* HPT302 */
 141                 mode = (HPT302_ALLOW_ATA133_6) ? 4 : 3;
 142         } else if (info->revision >= 5) {       /* HPT372 */
 143                 mode = (HPT372_ALLOW_ATA133_6) ? 4 : 3;
 144         } else if (info->revision >= 4) {       /* HPT370A */
 145                 mode = (HPT370_ALLOW_ATA100_5) ? 3 : 2;
 146         } else if (info->revision >= 3) {       /* HPT370 */
 147                 mode = (HPT370_ALLOW_ATA100_5) ? 3 : 2;
 148                 mode = (check_in_drive_lists(drive, bad_ata33)) ? 0 : mode;
 149         } else {                                /* HPT366 and HPT368 */
 150                 mode = (check_in_drive_lists(drive, bad_ata33)) ? 0 : 2;
 151         }
 152         if (!eighty_ninty_three(drive) && mode)
 153                 mode = min(mode, (u8)1);
 154         return mode;
 155 }
 156
 157 /*
 158  *      Note for the future; the SATA hpt37x we must set
 159  *      either PIO or UDMA modes 0,4,5
 160  */
 161
 162 static u8 hpt3xx_ratefilter (ide_drive_t *drive, u8 speed)
 163 {
 164         ide_hwif_t *hwif        = drive->hwif;
 165         struct hpt_info *info   = ide_get_hwifdata(hwif);
 166         u8 mode                 = hpt3xx_ratemask(drive);
 167
 168         if (drive->media != ide_disk)
 169                 return min(speed, (u8)XFER_PIO_4);
 170
 171         switch(mode) {
 172                 case 0x04:
 173                         speed = min(speed, (u8)XFER_UDMA_6);
 174                         break;
 175                 case 0x03:
 176                         speed = min(speed, (u8)XFER_UDMA_5);
 177                         if (info->revision >= 5)
 178                                 break;
 179                         if (check_in_drive_lists(drive, bad_ata100_5))
 180                                 speed = min(speed, (u8)XFER_UDMA_4);
 181                         break;
 182                 case 0x02:
 183                         speed = min(speed, (u8)XFER_UDMA_4);
 184         /*
 185          * CHECK ME, Does this need to be set to 5 ??
 186          */
 187                         if (info->revision >= 3)
 188                                 break;
 189                         if ((check_in_drive_lists(drive, bad_ata66_4)) ||
 190                             (!(HPT366_ALLOW_ATA66_4)))
 191                                 speed = min(speed, (u8)XFER_UDMA_3);
 192                         if ((check_in_drive_lists(drive, bad_ata66_3)) ||
 193                             (!(HPT366_ALLOW_ATA66_3)))
 194                                 speed = min(speed, (u8)XFER_UDMA_2);
 195                         break;
 196                 case 0x01:
 197                         speed = min(speed, (u8)XFER_UDMA_2);
 198         /*
 199          * CHECK ME, Does this need to be set to 5 ??
 200          */
 201                         if (info->revision >= 3)
 202                                 break;
 203                         if (check_in_drive_lists(drive, bad_ata33))
 204                                 speed = min(speed, (u8)XFER_MW_DMA_2);
 205                         break;
 206                 case 0x00:
 207                 default:
 208                         speed = min(speed, (u8)XFER_MW_DMA_2);
 209                         break;
 210         }
 211         return speed;
 212 }
 213
 214 static int check_in_drive_lists (ide_drive_t *drive, const char **list)
 215 {
 216         struct hd_driveid *id = drive->id;
 217
 218         if (quirk_drives == list) {
 219                 while (*list)
 220                         if (strstr(id->model, *list++))
 221                                 return 1;
 222         } else {
 223                 while (*list)
 224                         if (!strcmp(*list++,id->model))
 225                                 return 1;
 226         }
 227         return 0;
 228 }
 229
 230 static unsigned int pci_bus_clock_list (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
 231 {
 232         for ( ; chipset_table->xfer_speed ; chipset_table++)
 233                 if (chipset_table->xfer_speed == speed)
 234                         return chipset_table->chipset_settings;
 235         return chipset_table->chipset_settings;
 236 }
 237
 238 static int hpt36x_tune_chipset(ide_drive_t *drive, u8 xferspeed)
 239 {
 240         ide_hwif_t *hwif        = drive->hwif;
 241         struct pci_dev *dev     = hwif->pci_dev;
 242         struct hpt_info *info   = ide_get_hwifdata(hwif);
 243         u8 speed                = hpt3xx_ratefilter(drive, xferspeed);
 244         u8 regtime              = (drive->select.b.unit & 0x01) ? 0x44 : 0x40;
 245         u8 regfast              = (hwif->channel) ? 0x55 : 0x51;
 246         u8 drive_fast           = 0;
 247         u32 reg1 = 0, reg2      = 0;
 248
 249         /*
 250          * Disable the "fast interrupt" prediction.
 251          */
 252         pci_read_config_byte(dev, regfast, &drive_fast);
 253         if (drive_fast & 0x80)
 254                 pci_write_config_byte(dev, regfast, drive_fast & ~0x80);
 255
 256         reg2 = pci_bus_clock_list(speed, info->speed);
 257
 258         /*
 259          * Disable on-chip PIO FIFO/buffer
 260          *  (to avoid problems handling I/O errors later)
 261          */
 262         pci_read_config_dword(dev, regtime, &reg1);
 263         if (speed >= XFER_MW_DMA_0) {
 264                 reg2 = (reg2 & ~0xc0000000) | (reg1 & 0xc0000000);
 265         } else {
 266                 reg2 = (reg2 & ~0x30070000) | (reg1 & 0x30070000);
 267         }
 268         reg2 &= ~0x80000000;
 269
 270         pci_write_config_dword(dev, regtime, reg2);
 271
 272         return ide_config_drive_speed(drive, speed);
 273 }
 274
 275 static int hpt370_tune_chipset(ide_drive_t *drive, u8 xferspeed)
 276 {
 277         ide_hwif_t *hwif        = drive->hwif;
 278         struct pci_dev *dev = hwif->pci_dev;
 279         struct hpt_info *info   = ide_get_hwifdata(hwif);
 280         u8 speed        = hpt3xx_ratefilter(drive, xferspeed);
 281         u8 regfast      = (drive->hwif->channel) ? 0x55 : 0x51;
 282         u8 drive_pci    = 0x40 + (drive->dn * 4);
 283         u8 new_fast     = 0, drive_fast = 0;
 284         u32 list_conf   = 0, drive_conf = 0;
 285         u32 conf_mask   = (speed >= XFER_MW_DMA_0) ? 0xc0000000 : 0x30070000;
 286
 287         /*
 288          * Disable the "fast interrupt" prediction.
 289          * don't holdoff on interrupts. (== 0x01 despite what the docs say)
 290          */
 291         pci_read_config_byte(dev, regfast, &drive_fast);
 292         new_fast = drive_fast;
 293         if (new_fast & 0x02)
 294                 new_fast &= ~0x02;
 295
 296 #ifdef HPT_DELAY_INTERRUPT
 297         if (new_fast & 0x01)
 298                 new_fast &= ~0x01;
 299 #else
 300         if ((new_fast & 0x01) == 0)
 301                 new_fast |= 0x01;
 302 #endif
 303         if (new_fast != drive_fast)
 304                 pci_write_config_byte(dev, regfast, new_fast);
 305
 306         list_conf = pci_bus_clock_list(speed, info->speed);
 307
 308         pci_read_config_dword(dev, drive_pci, &drive_conf);
 309         list_conf = (list_conf & ~conf_mask) | (drive_conf & conf_mask);
 310
 311         if (speed < XFER_MW_DMA_0)
 312                 list_conf &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
 313         pci_write_config_dword(dev, drive_pci, list_conf);
 314
 315         return ide_config_drive_speed(drive, speed);
 316 }
 317
 318 static int hpt372_tune_chipset(ide_drive_t *drive, u8 xferspeed)
 319 {
 320         ide_hwif_t *hwif        = drive->hwif;
 321         struct pci_dev *dev     = hwif->pci_dev;
 322         struct hpt_info *info   = ide_get_hwifdata(hwif);
 323         u8 speed        = hpt3xx_ratefilter(drive, xferspeed);
 324         u8 regfast      = (drive->hwif->channel) ? 0x55 : 0x51;
 325         u8 drive_fast   = 0, drive_pci = 0x40 + (drive->dn * 4);
 326         u32 list_conf   = 0, drive_conf = 0;
 327         u32 conf_mask   = (speed >= XFER_MW_DMA_0) ? 0xc0000000 : 0x30070000;
 328
 329         /*
 330          * Disable the "fast interrupt" prediction.
 331          * don't holdoff on interrupts. (== 0x01 despite what the docs say)
 332          */
 333         pci_read_config_byte(dev, regfast, &drive_fast);
 334         drive_fast &= ~0x07;
 335         pci_write_config_byte(dev, regfast, drive_fast);
 336
 337         list_conf = pci_bus_clock_list(speed, info->speed);
 338         pci_read_config_dword(dev, drive_pci, &drive_conf);
 339         list_conf = (list_conf & ~conf_mask) | (drive_conf & conf_mask);
 340         if (speed < XFER_MW_DMA_0)
 341                 list_conf &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
 342         pci_write_config_dword(dev, drive_pci, list_conf);
 343
 344         return ide_config_drive_speed(drive, speed);
 345 }
 346
 347 static int hpt3xx_tune_chipset (ide_drive_t *drive, u8 speed)
 348 {
 349         ide_hwif_t *hwif        = drive->hwif;
 350         struct hpt_info *info   = ide_get_hwifdata(hwif);
 351
 352         if (info->revision >= 8)
 353                 return hpt372_tune_chipset(drive, speed); /* not a typo */
 354         else if (info->revision >= 5)
 355                 return hpt372_tune_chipset(drive, speed);
 356         else if (info->revision >= 3)
 357                 return hpt370_tune_chipset(drive, speed);
 358         else    /* hpt368: hpt_minimum_revision(dev, 2) */
 359                 return hpt36x_tune_chipset(drive, speed);
 360 }
 361
 362 static void hpt3xx_tune_drive (ide_drive_t *drive, u8 pio)
 363 {
 364         pio = ide_get_best_pio_mode(drive, 255, pio, NULL);
 365         (void) hpt3xx_tune_chipset(drive, (XFER_PIO_0 + pio));
 366 }
 367
 368 /*
 369  * This allows the configuration of ide_pci chipset registers
 370  * for cards that learn about the drive's UDMA, DMA, PIO capabilities
 371  * after the drive is reported by the OS.  Initially for designed for
 372  * HPT366 UDMA chipset by HighPoint|Triones Technologies, Inc.
 373  *
 374  * check_in_drive_lists(drive, bad_ata66_4)
 375  * check_in_drive_lists(drive, bad_ata66_3)
 376  * check_in_drive_lists(drive, bad_ata33)
 377  *
 378  */
 379 static int config_chipset_for_dma (ide_drive_t *drive)
 380 {
 381         u8 speed = ide_dma_speed(drive, hpt3xx_ratemask(drive));
 382         ide_hwif_t *hwif = drive->hwif;
 383         struct hpt_info *info   = ide_get_hwifdata(hwif);
 384
 385         if (!speed)
 386                 return 0;
 387
 388         /* If we don't have any timings we can't do a lot */
 389         if (info->speed == NULL)
 390                 return 0;
 391
 392         (void) hpt3xx_tune_chipset(drive, speed);
 393         return ide_dma_enable(drive);
 394 }
 395
 396 static int hpt3xx_quirkproc (ide_drive_t *drive)
 397 {
 398         return ((int) check_in_drive_lists(drive, quirk_drives));
 399 }
 400
 401 static void hpt3xx_intrproc (ide_drive_t *drive)
 402 {
 403         ide_hwif_t *hwif = drive->hwif;
 404
 405         if (drive->quirk_list)
 406                 return;
 407         /* drives in the quirk_list may not like intr setups/cleanups */
 408         hwif->OUTB(drive->ctl|2, IDE_CONTROL_REG);
 409 }
 410
 411 static void hpt3xx_maskproc (ide_drive_t *drive, int mask)
 412 {
 413         ide_hwif_t *hwif = drive->hwif;
 414         struct hpt_info *info = ide_get_hwifdata(hwif);
 415         struct pci_dev *dev = hwif->pci_dev;
 416
 417         if (drive->quirk_list) {
 418                 if (info->revision >= 3) {
 419                         u8 reg5a = 0;
 420                         pci_read_config_byte(dev, 0x5a, &reg5a);
 421                         if (((reg5a & 0x10) >> 4) != mask)
 422                                 pci_write_config_byte(dev, 0x5a, mask ? (reg5a | 0x10) : (reg5a & ~0x10));
 423                 } else {
 424                         if (mask) {
 425                                 disable_irq(hwif->irq);
 426                         } else {
 427                                 enable_irq(hwif->irq);
 428                         }
 429                 }
 430         } else {
 431                 if (IDE_CONTROL_REG)
 432                         hwif->OUTB(mask ? (drive->ctl | 2) :
 433                                                  (drive->ctl & ~2),
 434                                                  IDE_CONTROL_REG);
 435         }
 436 }
 437
 438 static int hpt366_config_drive_xfer_rate (ide_drive_t *drive)
 439 {
 440         ide_hwif_t *hwif        = drive->hwif;
 441         struct hd_driveid *id   = drive->id;
 442
 443         drive->init_speed = 0;
 444
 445         if ((id->capability & 1) && drive->autodma) {
 446
 447                 if (ide_use_dma(drive)) {
 448                         if (config_chipset_for_dma(drive))
 449                                 return hwif->ide_dma_on(drive);
 450                 }
 451
 452                 goto fast_ata_pio;
 453
 454         } else if ((id->capability & 8) || (id->field_valid & 2)) {
 455 fast_ata_pio:
 456                 hpt3xx_tune_drive(drive, 5);
 457                 return hwif->ide_dma_off_quietly(drive);
 458         }
 459         /* IORDY not supported */
 460         return 0;
 461 }
 462
 463 /*
 464  * This is specific to the HPT366 UDMA bios chipset
 465  * by HighPoint|Triones Technologies, Inc.
 466  */
 467 static int hpt366_ide_dma_lostirq (ide_drive_t *drive)
 468 {
 469         struct pci_dev *dev     = HWIF(drive)->pci_dev;
 470         u8 reg50h = 0, reg52h = 0, reg5ah = 0;
 471
 472         pci_read_config_byte(dev, 0x50, &reg50h);
 473         pci_read_config_byte(dev, 0x52, &reg52h);
 474         pci_read_config_byte(dev, 0x5a, &reg5ah);
 475         printk("%s: (%s)  reg50h=0x%02x, reg52h=0x%02x, reg5ah=0x%02x\n",
 476                 drive->name, __FUNCTION__, reg50h, reg52h, reg5ah);
 477         if (reg5ah & 0x10)
 478                 pci_write_config_byte(dev, 0x5a, reg5ah & ~0x10);
 479         return __ide_dma_lostirq(drive);
 480 }
 481
 482 static void hpt370_clear_engine (ide_drive_t *drive)
 483 {
 484         u8 regstate = HWIF(drive)->channel ? 0x54 : 0x50;
 485         pci_write_config_byte(HWIF(drive)->pci_dev, regstate, 0x37);
 486         udelay(10);
 487 }
 488
 489 static void hpt370_ide_dma_start(ide_drive_t *drive)
 490 {
 491 #ifdef HPT_RESET_STATE_ENGINE
 492         hpt370_clear_engine(drive);
 493 #endif
 494         ide_dma_start(drive);
 495 }
 496
 497 static int hpt370_ide_dma_end (ide_drive_t *drive)
 498 {
 499         ide_hwif_t *hwif        = HWIF(drive);
 500         u8 dma_stat             = hwif->INB(hwif->dma_status);
 501
 502         if (dma_stat & 0x01) {
 503                 /* wait a little */
 504                 udelay(20);
 505                 dma_stat = hwif->INB(hwif->dma_status);
 506         }
 507         if ((dma_stat & 0x01) != 0)
 508                 /* fallthrough */
 509                 (void) HWIF(drive)->ide_dma_timeout(drive);
 510
 511         return __ide_dma_end(drive);
 512 }
 513
 514 static void hpt370_lostirq_timeout (ide_drive_t *drive)
 515 {
 516         ide_hwif_t *hwif        = HWIF(drive);
 517         u8 bfifo = 0, reginfo   = hwif->channel ? 0x56 : 0x52;
 518         u8 dma_stat = 0, dma_cmd = 0;
 519
 520         pci_read_config_byte(HWIF(drive)->pci_dev, reginfo, &bfifo);
 521         printk(KERN_DEBUG "%s: %d bytes in FIFO\n", drive->name, bfifo);
 522         hpt370_clear_engine(drive);
 523         /* get dma command mode */
 524         dma_cmd = hwif->INB(hwif->dma_command);
 525         /* stop dma */
 526         hwif->OUTB(dma_cmd & ~0x1, hwif->dma_command);
 527         dma_stat = hwif->INB(hwif->dma_status);
 528         /* clear errors */
 529         hwif->OUTB(dma_stat | 0x6, hwif->dma_status);
 530 }
 531
 532 static int hpt370_ide_dma_timeout (ide_drive_t *drive)
 533 {
 534         hpt370_lostirq_timeout(drive);
 535         hpt370_clear_engine(drive);
 536         return __ide_dma_timeout(drive);
 537 }
 538
 539 static int hpt370_ide_dma_lostirq (ide_drive_t *drive)
 540 {
 541         hpt370_lostirq_timeout(drive);
 542         hpt370_clear_engine(drive);
 543         return __ide_dma_lostirq(drive);
 544 }
 545
 546 /* returns 1 if DMA IRQ issued, 0 otherwise */
 547 static int hpt374_ide_dma_test_irq(ide_drive_t *drive)
 548 {
 549         ide_hwif_t *hwif        = HWIF(drive);
 550         u16 bfifo               = 0;
 551         u8 reginfo              = hwif->channel ? 0x56 : 0x52;
 552         u8 dma_stat;
 553
 554         pci_read_config_word(hwif->pci_dev, reginfo, &bfifo);
 555         if (bfifo & 0x1FF) {
 556 //              printk("%s: %d bytes in FIFO\n", drive->name, bfifo);
 557                 return 0;
 558         }
 559
 560         dma_stat = hwif->INB(hwif->dma_status);
 561         /* return 1 if INTR asserted */
 562         if ((dma_stat & 4) == 4)
 563                 return 1;
 564
 565         if (!drive->waiting_for_dma)
 566                 printk(KERN_WARNING "%s: (%s) called while not waiting\n",
 567                                 drive->name, __FUNCTION__);
 568         return 0;
 569 }
 570
 571 static int hpt374_ide_dma_end (ide_drive_t *drive)
 572 {
 573         struct pci_dev *dev     = HWIF(drive)->pci_dev;
 574         ide_hwif_t *hwif        = HWIF(drive);
 575         u8 msc_stat = 0, mscreg = hwif->channel ? 0x54 : 0x50;
 576         u8 bwsr_stat = 0, bwsr_mask = hwif->channel ? 0x02 : 0x01;
 577
 578         pci_read_config_byte(dev, 0x6a, &bwsr_stat);
 579         pci_read_config_byte(dev, mscreg, &msc_stat);
 580         if ((bwsr_stat & bwsr_mask) == bwsr_mask)
 581                 pci_write_config_byte(dev, mscreg, msc_stat|0x30);
 582         return __ide_dma_end(drive);
 583 }
 584
 585 /**
 586  *      hpt372n_set_clock       -       perform clock switching dance
 587  *      @drive: Drive to switch
 588  *      @mode: Switching mode (0x21 for write, 0x23 otherwise)
 589  *
 590  *      Switch the DPLL clock on the HPT372N devices. This is a
 591  *      right mess.
 592  */
 593
 594 static void hpt372n_set_clock(ide_drive_t *drive, int mode)
 595 {
 596         ide_hwif_t *hwif        = HWIF(drive);
 597
 598         /* FIXME: should we check for DMA active and BUG() */
 599         /* Tristate the bus */
 600         outb(0x80, hwif->dma_base+0x73);
 601         outb(0x80, hwif->dma_base+0x77);
 602
 603         /* Switch clock and reset channels */
 604         outb(mode, hwif->dma_base+0x7B);
 605         outb(0xC0, hwif->dma_base+0x79);
 606
 607         /* Reset state machines */
 608         outb(0x37, hwif->dma_base+0x70);
 609         outb(0x37, hwif->dma_base+0x74);
 610
 611         /* Complete reset */
 612         outb(0x00, hwif->dma_base+0x79);
 613
 614         /* Reconnect channels to bus */
 615         outb(0x00, hwif->dma_base+0x73);
 616         outb(0x00, hwif->dma_base+0x77);
 617 }
 618
 619 /**
 620  *      hpt372n_rw_disk         -       wrapper for I/O
 621  *      @drive: drive for command
 622  *      @rq: block request structure
 623  *      @block: block number
 624  *
 625  *      This is called when a disk I/O is issued to the 372N instead
 626  *      of the default functionality. We need it because of the clock
 627  *      switching
 628  *
 629  */
 630
 631 static ide_startstop_t hpt372n_rw_disk(ide_drive_t *drive, struct request *rq, sector_t block)
 632 {
 633         int wantclock;
 634
 635         if(rq_data_dir(rq) == READ)
 636                 wantclock = 0x21;
 637         else
 638                 wantclock = 0x23;
 639
 640         if(HWIF(drive)->config_data != wantclock)
 641         {
 642                 hpt372n_set_clock(drive, wantclock);
 643                 HWIF(drive)->config_data = wantclock;
 644         }
 645         return __ide_do_rw_disk(drive, rq, block);
 646 }
 647
 648 /*
 649  * Since SUN Cobalt is attempting to do this operation, I should disclose
 650  * this has been a long time ago Thu Jul 27 16:40:57 2000 was the patch date
 651  * HOTSWAP ATA Infrastructure.
 652  */
 653
 654 static void hpt3xx_reset (ide_drive_t *drive)
 655 {
 656 }
 657
 658 static int hpt3xx_tristate (ide_drive_t * drive, int state)
 659 {
 660         ide_hwif_t *hwif        = HWIF(drive);
 661         struct pci_dev *dev     = hwif->pci_dev;
 662         u8 reg59h = 0, reset    = (hwif->channel) ? 0x80 : 0x40;
 663         u8 regXXh = 0, state_reg= (hwif->channel) ? 0x57 : 0x53;
 664
 665         pci_read_config_byte(dev, 0x59, &reg59h);
 666         pci_read_config_byte(dev, state_reg, &regXXh);
 667
 668         if (state) {
 669                 (void) ide_do_reset(drive);
 670                 pci_write_config_byte(dev, state_reg, regXXh|0x80);
 671                 pci_write_config_byte(dev, 0x59, reg59h|reset);
 672         } else {
 673                 pci_write_config_byte(dev, 0x59, reg59h & ~(reset));
 674                 pci_write_config_byte(dev, state_reg, regXXh & ~(0x80));
 675                 (void) ide_do_reset(drive);
 676         }
 677         return 0;
 678 }
 679
 680 /*
 681  * set/get power state for a drive.
 682  * turning the power off does the following things:
 683  *   1) soft-reset the drive
 684  *   2) tri-states the ide bus
 685  *
 686  * when we turn things back on, we need to re-initialize things.
 687  */
 688 #define TRISTATE_BIT  0x8000
 689 static int hpt370_busproc(ide_drive_t * drive, int state)
 690 {
 691         ide_hwif_t *hwif        = drive->hwif;
 692         struct pci_dev *dev     = hwif->pci_dev;
 693         u8 tristate = 0, resetmask = 0, bus_reg = 0;
 694         u16 tri_reg;
 695
 696         hwif->bus_state = state;
 697
 698         if (hwif->channel) {
 699                 /* secondary channel */
 700                 tristate = 0x56;
 701                 resetmask = 0x80;
 702         } else {
 703                 /* primary channel */
 704                 tristate = 0x52;
 705                 resetmask = 0x40;
 706         }
 707
 708         /* grab status */
 709         pci_read_config_word(dev, tristate, &tri_reg);
 710         pci_read_config_byte(dev, 0x59, &bus_reg);
 711
 712         /* set the state. we don't set it if we don't need to do so.
 713          * make sure that the drive knows that it has failed if it's off */
 714         switch (state) {
 715         case BUSSTATE_ON:
 716                 hwif->drives[0].failures = 0;
 717                 hwif->drives[1].failures = 0;
 718                 if ((bus_reg & resetmask) == 0)
 719                         return 0;
 720                 tri_reg &= ~TRISTATE_BIT;
 721                 bus_reg &= ~resetmask;
 722                 break;
 723         case BUSSTATE_OFF:
 724                 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
 725                 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
 726                 if ((tri_reg & TRISTATE_BIT) == 0 && (bus_reg & resetmask))
 727                         return 0;
 728                 tri_reg &= ~TRISTATE_BIT;
 729                 bus_reg |= resetmask;
 730                 break;
 731         case BUSSTATE_TRISTATE:
 732                 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
 733                 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
 734                 if ((tri_reg & TRISTATE_BIT) && (bus_reg & resetmask))
 735                         return 0;
 736                 tri_reg |= TRISTATE_BIT;
 737                 bus_reg |= resetmask;
 738                 break;
 739         }
 740         pci_write_config_byte(dev, 0x59, bus_reg);
 741         pci_write_config_word(dev, tristate, tri_reg);
 742
 743         return 0;
 744 }
 745
 746 static void __devinit hpt366_clocking(ide_hwif_t *hwif)
 747 {
 748         u32 reg1        = 0;
 749         struct hpt_info *info = ide_get_hwifdata(hwif);
 750
 751         pci_read_config_dword(hwif->pci_dev, 0x40, &reg1);
 752
 753         /* detect bus speed by looking at control reg timing: */
 754         switch((reg1 >> 8) & 7) {
 755                 case 5:
 756                         info->speed = forty_base_hpt366;
 757                         break;
 758                 case 9:
 759                         info->speed = twenty_five_base_hpt366;
 760                         break;
 761                 case 7:
 762                 default:
 763                         info->speed = thirty_three_base_hpt366;
 764                         break;
 765         }
 766 }
 767
 768 static void __devinit hpt37x_clocking(ide_hwif_t *hwif)
 769 {
 770         struct hpt_info *info = ide_get_hwifdata(hwif);
 771         struct pci_device *dev = hwif->pci_dev;
 772         int adjust, i;
 773         u16 freq;
 774         u32 pll;
 775         u8 reg5bh;
 776
 777         /*
 778          * default to pci clock. make sure MA15/16 are set to output
 779          * to prevent drives having problems with 40-pin cables. Needed
 780          * for some drives such as IBM-DTLA which will not enter ready
 781          * state on reset when PDIAG is a input.
 782          *
 783          * ToDo: should we set 0x21 when using PLL mode ?
 784          */
 785         pci_write_config_byte(dev, 0x5b, 0x23);
 786
 787         /*
 788          * set up the PLL. we need to adjust it so that it's stable.
 789          * freq = Tpll * 192 / Tpci
 790          *
 791          * Todo. For non x86 should probably check the dword is
 792          * set to 0xABCDExxx indicating the BIOS saved f_CNT
 793          */
 794         pci_read_config_word(dev, 0x78, &freq);
 795         freq &= 0x1FF;
 796
 797         /*
 798          * The 372N uses different PCI clock information and has
 799          * some other complications
 800          *      On PCI33 timing we must clock switch
 801          *      On PCI66 timing we must NOT use the PCI clock
 802          *
 803          * Currently we always set up the PLL for the 372N
 804          */
 805
 806         if(info->flags & IS_372N)
 807         {
 808                 printk(KERN_INFO "hpt: HPT372N detected, using 372N timing.\n");
 809                 if(freq < 0x55)
 810                         pll = F_LOW_PCI_33;
 811                 else if(freq < 0x70)
 812                         pll = F_LOW_PCI_40;
 813                 else if(freq < 0x7F)
 814                         pll = F_LOW_PCI_50;
 815                 else
 816                         pll = F_LOW_PCI_66;
 817
 818                 printk(KERN_INFO "FREQ: %d PLL: %d\n", freq, pll);
 819
 820                 /* We always use the pll not the PCI clock on 372N */
 821         }
 822         else
 823         {
 824                 if(freq < 0x9C)
 825                         pll = F_LOW_PCI_33;
 826                 else if(freq < 0xb0)
 827                         pll = F_LOW_PCI_40;
 828                 else if(freq <0xc8)
 829                         pll = F_LOW_PCI_50;
 830                 else
 831                         pll = F_LOW_PCI_66;
 832
 833                 if (pll == F_LOW_PCI_33) {
 834                         if (info->revision >= 8)
 835                                 info->speed = thirty_three_base_hpt374;
 836                         else if (info->revision >= 5)
 837                                 info->speed = thirty_three_base_hpt372;
 838                         else if (info->revision >= 4)
 839                                 info->speed = thirty_three_base_hpt370a;
 840                         else
 841                                 info->speed = thirty_three_base_hpt370;
 842                         printk(KERN_DEBUG "HPT37X: using 33MHz PCI clock\n");
 843                 } else if (pll == F_LOW_PCI_40) {
 844                         /* Unsupported */
 845                 } else if (pll == F_LOW_PCI_50) {
 846                         if (info->revision >= 8)
 847                                 info->speed = fifty_base_hpt370a;
 848                         else if (info->revision >= 5)
 849                                 info->speed = fifty_base_hpt372;
 850                         else if (info->revision >= 4)
 851                                 info->speed = fifty_base_hpt370a;
 852                         else
 853                                 info->speed = fifty_base_hpt370a;
 854                         printk(KERN_DEBUG "HPT37X: using 50MHz PCI clock\n");
 855                 } else {
 856                         if (info->revision >= 8) {
 857                                 printk(KERN_ERR "HPT37x: 66MHz timings are not supported.\n");
 858                         }
 859                         else if (info->revision >= 5)
 860                                 info->speed = sixty_six_base_hpt372;
 861                         else if (info->revision >= 4)
 862                                 info->speed = sixty_six_base_hpt370a;
 863                         else
 864                                 info->speed = sixty_six_base_hpt370;
 865                         printk(KERN_DEBUG "HPT37X: using 66MHz PCI clock\n");
 866                 }
 867         }
 868
 869         /*
 870          * only try the pll if we don't have a table for the clock
 871          * speed that we're running at. NOTE: the internal PLL will
 872          * result in slow reads when using a 33MHz PCI clock. we also
 873          * don't like to use the PLL because it will cause glitches
 874          * on PRST/SRST when the HPT state engine gets reset.
 875          *
 876          * ToDo: Use 66MHz PLL when ATA133 devices are present on a
 877          * 372 device so we can get ATA133 support
 878          */
 879         if (info->speed)
 880                 goto init_hpt37X_done;
 881
 882         info->flags |= PLL_MODE;
 883
 884         /*
 885          * FIXME: make this work correctly, esp with 372N as per
 886          * reference driver code.
 887          *
 888          * adjust PLL based upon PCI clock, enable it, and wait for
 889          * stabilization.
 890          */
 891         adjust = 0;
 892         freq = (pll < F_LOW_PCI_50) ? 2 : 4;
 893         while (adjust++ < 6) {
 894                 pci_write_config_dword(dev, 0x5c, (freq + pll) << 16 |
 895                                        pll | 0x100);
 896
 897                 /* wait for clock stabilization */
 898                 for (i = 0; i < 0x50000; i++) {
 899                         pci_read_config_byte(dev, 0x5b, &reg5bh);
 900                         if (reg5bh & 0x80) {
 901                                 /* spin looking for the clock to destabilize */
 902                                 for (i = 0; i < 0x1000; ++i) {
 903                                         pci_read_config_byte(dev, 0x5b,
 904                                                              &reg5bh);
 905                                         if ((reg5bh & 0x80) == 0)
 906                                                 goto pll_recal;
 907                                 }
 908                                 pci_read_config_dword(dev, 0x5c, &pll);
 909                                 pci_write_config_dword(dev, 0x5c,
 910                                                        pll & ~0x100);
 911                                 pci_write_config_byte(dev, 0x5b, 0x21);
 912                                 if (info->revision >= 8)
 913                                         info->speed = fifty_base_hpt370a;
 914                                 else if (info->revision >= 5)
 915                                         info->speed = fifty_base_hpt372;
 916                                 else if (info->revision >= 4)
 917                                         info->speed = fifty_base_hpt370a;
 918                                 else
 919                                         info->speed = fifty_base_hpt370a;
 920                                 printk("HPT37X: using 50MHz internal PLL\n");
 921                                 goto init_hpt37X_done;
 922                         }
 923                 }
 924 pll_recal:
 925                 if (adjust & 1)
 926                         pll -= (adjust >> 1);
 927                 else
 928                         pll += (adjust >> 1);
 929         }
 930
 931 init_hpt37X_done:
 932         if (!info->speed)
 933                 printk(KERN_ERR "HPT37X%s: unknown bus timing [%d %d].\n",
 934                         (info->flags & IS_372N)?"N":"", pll, freq);
 935         /* reset state engine */
 936         pci_write_config_byte(dev, 0x50, 0x37);
 937         pci_write_config_byte(dev, 0x54, 0x37);
 938         udelay(100);
 939 }
 940
 941 static int __devinit init_hpt37x(struct pci_dev *dev)
 942 {
 943         u8 reg5ah;
 944
 945         pci_read_config_byte(dev, 0x5a, &reg5ah);
 946         /* interrupt force enable */
 947         pci_write_config_byte(dev, 0x5a, (reg5ah & ~0x10));
 948         return 0;
 949 }
 950
 951 static int __devinit init_hpt366(struct pci_dev *dev)
 952 {
 953         u32 reg1        = 0;
 954         u8 drive_fast   = 0;
 955
 956         /*
 957          * Disable the "fast interrupt" prediction.
 958          */
 959         pci_read_config_byte(dev, 0x51, &drive_fast);
 960         if (drive_fast & 0x80)
 961                 pci_write_config_byte(dev, 0x51, drive_fast & ~0x80);
 962         pci_read_config_dword(dev, 0x40, &reg1);
 963
 964         return 0;
 965 }
 966
 967 static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const char *name)
 968 {
 969         int ret = 0;
 970         /* FIXME: Not portable */
 971         if (dev->resource[PCI_ROM_RESOURCE].start)
 972                 pci_write_config_byte(dev, PCI_ROM_ADDRESS,
 973                         dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
 974
 975         pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
 976         pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
 977         pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
 978         pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
 979
 980         if (hpt_revision(dev) >= 3)
 981                 ret = init_hpt37x(dev);
 982         else
 983                 ret = init_hpt366(dev);
 984
 985         if (ret)
 986                 return ret;
 987
 988         return dev->irq;
 989 }
 990
 991 static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
 992 {
 993         struct pci_dev *dev             = hwif->pci_dev;
 994         struct hpt_info *info           = ide_get_hwifdata(hwif);
 995         u8 ata66 = 0, regmask           = (hwif->channel) ? 0x01 : 0x02;
 996
 997         hwif->tuneproc                  = &hpt3xx_tune_drive;
 998         hwif->speedproc                 = &hpt3xx_tune_chipset;
 999         hwif->quirkproc                 = &hpt3xx_quirkproc;
1000         hwif->intrproc                  = &hpt3xx_intrproc;
1001         hwif->maskproc                  = &hpt3xx_maskproc;
1002
1003         if(info->flags & IS_372N)
1004                 hwif->rw_disk = &hpt372n_rw_disk;
1005
1006         /*
1007          * The HPT37x uses the CBLID pins as outputs for MA15/MA16
1008          * address lines to access an external eeprom.  To read valid
1009          * cable detect state the pins must be enabled as inputs.
1010          */
1011         if (info->revision >= 8 && (PCI_FUNC(dev->devfn) & 1)) {
1012                 /*
1013                  * HPT374 PCI function 1
1014                  * - set bit 15 of reg 0x52 to enable TCBLID as input
1015                  * - set bit 15 of reg 0x56 to enable FCBLID as input
1016                  */
1017                 u16 mcr3, mcr6;
1018                 pci_read_config_word(dev, 0x52, &mcr3);
1019                 pci_read_config_word(dev, 0x56, &mcr6);
1020                 pci_write_config_word(dev, 0x52, mcr3 | 0x8000);
1021                 pci_write_config_word(dev, 0x56, mcr6 | 0x8000);
1022                 /* now read cable id register */
1023                 pci_read_config_byte(dev, 0x5a, &ata66);
1024                 pci_write_config_word(dev, 0x52, mcr3);
1025                 pci_write_config_word(dev, 0x56, mcr6);
1026         } else if (info->revision >= 3) {
1027                 /*
1028                  * HPT370/372 and 374 pcifn 0
1029                  * - clear bit 0 of 0x5b to enable P/SCBLID as inputs
1030                  */
1031                 u8 scr2;
1032                 pci_read_config_byte(dev, 0x5b, &scr2);
1033                 pci_write_config_byte(dev, 0x5b, scr2 & ~1);
1034                 /* now read cable id register */
1035                 pci_read_config_byte(dev, 0x5a, &ata66);
1036                 pci_write_config_byte(dev, 0x5b, scr2);
1037         } else {
1038                 pci_read_config_byte(dev, 0x5a, &ata66);
1039         }
1040
1041 #ifdef DEBUG
1042         printk("HPT366: reg5ah=0x%02x ATA-%s Cable Port%d\n",
1043                 ata66, (ata66 & regmask) ? "33" : "66",
1044                 PCI_FUNC(hwif->pci_dev->devfn));
1045 #endif /* DEBUG */
1046
1047 #ifdef HPT_SERIALIZE_IO
1048         /* serialize access to this device */
1049         if (hwif->mate)
1050                 hwif->serialized = hwif->mate->serialized = 1;
1051 #endif
1052
1053         if (info->revision >= 3) {
1054                 u8 reg5ah = 0;
1055                         pci_write_config_byte(dev, 0x5a, reg5ah & ~0x10);
1056                 /*
1057                  * set up ioctl for power status.
1058                  * note: power affects both
1059                  * drives on each channel
1060                  */
1061                 hwif->resetproc = &hpt3xx_reset;
1062                 hwif->busproc   = &hpt370_busproc;
1063         } else if (info->revision >= 2) {
1064                 hwif->resetproc = &hpt3xx_reset;
1065                 hwif->busproc   = &hpt3xx_tristate;
1066         } else {
1067                 hwif->resetproc = &hpt3xx_reset;
1068                 hwif->busproc   = &hpt3xx_tristate;
1069         }
1070
1071         if (!hwif->dma_base) {
1072                 hwif->drives[0].autotune = 1;
1073                 hwif->drives[1].autotune = 1;
1074                 return;
1075         }
1076
1077         hwif->ultra_mask = 0x7f;
1078         hwif->mwdma_mask = 0x07;
1079
1080         if (!(hwif->udma_four))
1081                 hwif->udma_four = ((ata66 & regmask) ? 0 : 1);
1082         hwif->ide_dma_check = &hpt366_config_drive_xfer_rate;
1083
1084         if (info->revision >= 8) {
1085                 hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq;
1086                 hwif->ide_dma_end = &hpt374_ide_dma_end;
1087         } else if (info->revision >= 5) {
1088                 hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq;
1089                 hwif->ide_dma_end = &hpt374_ide_dma_end;
1090         } else if (info->revision >= 3) {
1091                 hwif->ide_dma_start = &hpt370_ide_dma_start;
1092                 hwif->ide_dma_end = &hpt370_ide_dma_end;
1093                 hwif->ide_dma_timeout = &hpt370_ide_dma_timeout;
1094                 hwif->ide_dma_lostirq = &hpt370_ide_dma_lostirq;
1095         } else if (info->revision >= 2)
1096                 hwif->ide_dma_lostirq = &hpt366_ide_dma_lostirq;
1097         else
1098                 hwif->ide_dma_lostirq = &hpt366_ide_dma_lostirq;
1099
1100         if (!noautodma)
1101                 hwif->autodma = 1;
1102         hwif->drives[0].autodma = hwif->autodma;
1103         hwif->drives[1].autodma = hwif->autodma;
1104 }
1105
1106 static void __devinit init_dma_hpt366(ide_hwif_t *hwif, unsigned long dmabase)
1107 {
1108         struct hpt_info *info   = ide_get_hwifdata(hwif);
1109         u8 masterdma    = 0, slavedma = 0;
1110         u8 dma_new      = 0, dma_old = 0;
1111         u8 primary      = hwif->channel ? 0x4b : 0x43;
1112         u8 secondary    = hwif->channel ? 0x4f : 0x47;
1113         unsigned long flags;
1114
1115         if (!dmabase)
1116                 return;
1117
1118         if(info->speed == NULL) {
1119                 printk(KERN_WARNING "hpt: no known IDE timings, disabling DMA.\n");
1120                 return;
1121         }
1122
1123         dma_old = hwif->INB(dmabase+2);
1124
1125         local_irq_save(flags);
1126
1127         dma_new = dma_old;
1128         pci_read_config_byte(hwif->pci_dev, primary, &masterdma);
1129         pci_read_config_byte(hwif->pci_dev, secondary, &slavedma);
1130
1131         if (masterdma & 0x30)   dma_new |= 0x20;
1132         if (slavedma & 0x30)    dma_new |= 0x40;
1133         if (dma_new != dma_old)
1134                 hwif->OUTB(dma_new, dmabase+2);
1135
1136         local_irq_restore(flags);
1137
1138         ide_setup_dma(hwif, dmabase, 8);
1139 }
1140
1141 /*
1142  *      We "borrow" this hook in order to set the data structures
1143  *      up early enough before dma or init_hwif calls are made.
1144  */
1145
1146 static void __devinit init_iops_hpt366(ide_hwif_t *hwif)
1147 {
1148         struct hpt_info *info = kmalloc(sizeof(struct hpt_info), GFP_KERNEL);
1149         unsigned long dmabase = pci_resource_start(hwif->pci_dev, 4);
1150         u8 did, rid;
1151
1152         if(info == NULL) {
1153                 printk(KERN_WARNING "hpt366: out of memory.\n");
1154                 return;
1155         }
1156         memset(info, 0, sizeof(struct hpt_info));
1157         ide_set_hwifdata(hwif, info);
1158
1159         if(dmabase) {
1160                 did = inb(dmabase + 0x22);
1161                 rid = inb(dmabase + 0x28);
1162
1163                 if((did == 4 && rid == 6) || (did == 5 && rid > 1))
1164                         info->flags |= IS_372N;
1165         }
1166
1167         info->revision = hpt_revision(hwif->pci_dev);
1168
1169         if (info->revision >= 3)
1170                 hpt37x_clocking(hwif);
1171         else
1172                 hpt366_clocking(hwif);
1173 }
1174
1175
1176 static void __devinit init_setup_hpt374(struct pci_dev *dev, ide_pci_device_t *d)
1177 {
1178         struct pci_dev *findev = NULL;
1179
1180         if (PCI_FUNC(dev->devfn) & 1)
1181                 return;
1182
1183         while ((findev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, findev)) != NULL) {
1184                 if ((findev->vendor == dev->vendor) &&
1185                     (findev->device == dev->device) &&
1186                     ((findev->devfn - dev->devfn) == 1) &&
1187                     (PCI_FUNC(findev->devfn) & 1)) {
1188                         if (findev->irq != dev->irq) {
1189                                 /* FIXME: we need a core pci_set_interrupt() */
1190                                 findev->irq = dev->irq;
1191                                 printk(KERN_WARNING "%s: pci-config space interrupt "
1192                                         "fixed.\n", d->name);
1193                         }
1194                         ide_setup_pci_devices(dev, findev, d);
1195                         return;
1196                 }
1197         }
1198         ide_setup_pci_device(dev, d);
1199 }
1200
1201 static void __devinit init_setup_hpt37x(struct pci_dev *dev, ide_pci_device_t *d)
1202 {
1203         ide_setup_pci_device(dev, d);
1204 }
1205
1206 static void __devinit init_setup_hpt366(struct pci_dev *dev, ide_pci_device_t *d)
1207 {
1208         struct pci_dev *findev = NULL;
1209         u8 pin1 = 0, pin2 = 0;
1210         unsigned int class_rev;
1211         char *chipset_names[] = {"HPT366", "HPT366",  "HPT368",
1212                                  "HPT370", "HPT370A", "HPT372",
1213                                  "HPT372N" };
1214
1215         if (PCI_FUNC(dev->devfn) & 1)
1216                 return;
1217
1218         pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
1219         class_rev &= 0xff;
1220
1221         if(dev->device == PCI_DEVICE_ID_TTI_HPT372N)
1222                 class_rev = 6;
1223
1224         if(class_rev <= 6)
1225                 d->name = chipset_names[class_rev];
1226
1227         switch(class_rev) {
1228                 case 6:
1229                 case 5:
1230                 case 4:
1231                 case 3: ide_setup_pci_device(dev, d);
1232                         return;
1233                 default:        break;
1234         }
1235
1236         d->channels = 1;
1237
1238         pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1);
1239         while ((findev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, findev)) != NULL) {
1240                 if ((findev->vendor == dev->vendor) &&
1241                     (findev->device == dev->device) &&
1242                     ((findev->devfn - dev->devfn) == 1) &&
1243                     (PCI_FUNC(findev->devfn) & 1)) {
1244                         pci_read_config_byte(findev, PCI_INTERRUPT_PIN, &pin2);
1245                         if ((pin1 != pin2) && (dev->irq == findev->irq)) {
1246                                 d->bootable = ON_BOARD;
1247                                 printk("%s: onboard version of chipset, "
1248                                         "pin1=%d pin2=%d\n", d->name,
1249                                         pin1, pin2);
1250                         }
1251                         ide_setup_pci_devices(dev, findev, d);
1252                         return;
1253                 }
1254         }
1255         ide_setup_pci_device(dev, d);
1256 }
1257
1258
1259 /**
1260  *      hpt366_init_one -       called when an HPT366 is found
1261  *      @dev: the hpt366 device
1262  *      @id: the matching pci id
1263  *
1264  *      Called when the PCI registration layer (or the IDE initialization)
1265  *      finds a device matching our IDE device tables.
1266  */
1267
1268 static int __devinit hpt366_init_one(struct pci_dev *dev, const struct pci_device_id *id)
1269 {
1270         ide_pci_device_t *d = &hpt366_chipsets[id->driver_data];
1271
1272         d->init_setup(dev, d);
1273         return 0;
1274 }
1275
1276 static struct pci_device_id hpt366_pci_tbl[] = {
1277         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT366, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1278         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
1279         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT302, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
1280         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
1281         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT374, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
1282         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372N, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5},
1283         { 0, },
1284 };
1285 MODULE_DEVICE_TABLE(pci, hpt366_pci_tbl);
1286
1287 static struct pci_driver driver = {
1288         .name           = "HPT366_IDE",
1289         .id_table       = hpt366_pci_tbl,
1290         .probe          = hpt366_init_one,
1291 };
1292
1293 static int hpt366_ide_init(void)
1294 {
1295         return ide_pci_register_driver(&driver);
1296 }
1297
1298 module_init(hpt366_ide_init);
1299
1300 MODULE_AUTHOR("Andre Hedrick");
1301 MODULE_DESCRIPTION("PCI driver module for Highpoint HPT366 IDE");
1302 MODULE_LICENSE("GPL");