2 * dv1394.c - DV input/output over IEEE 1394 on OHCI chips
3 * Copyright (C)2001 Daniel Maas <dmaas@dcine.com>
4 * receive by Dan Dennedy <dan@dennedy.org>
7 * video1394.c - video driver for OHCI 1394 boards
8 * Copyright (C)1999,2000 Sebastien Rougeaux <sebastien.rougeaux@anu.edu.au>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software Foundation,
22 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
28 I designed dv1394 as a "pipe" that you can use to shoot DV onto a
29 FireWire bus. In transmission mode, dv1394 does the following:
31 1. accepts contiguous frames of DV data from user-space, via write()
32 or mmap() (see dv1394.h for the complete API)
33 2. wraps IEC 61883 packets around the DV data, inserting
34 empty synchronization packets as necessary
35 3. assigns accurate SYT timestamps to the outgoing packets
36 4. shoots them out using the OHCI card's IT DMA engine
38 Thanks to Dan Dennedy, we now have a receive mode that does the following:
40 1. accepts raw IEC 61883 packets from the OHCI card
41 2. re-assembles the DV data payloads into contiguous frames,
42 discarding empty packets
43 3. sends the DV data to user-space via read() or mmap()
49 - tunable frame-drop behavior: either loop last frame, or halt transmission
51 - use a scatter/gather buffer for DMA programs (f->descriptor_pool)
52 so that we don't rely on allocating 64KB of contiguous kernel memory
53 via pci_alloc_consistent()
56 - during reception, better handling of dropped frames and continuity errors
57 - during reception, prevent DMA from bypassing the irq tasklets
58 - reduce irq rate during reception (1/250 packets).
59 - add many more internal buffers during reception with scatter/gather dma.
60 - add dbc (continuity) checking on receive, increment status.dropped_frames
62 - restart IT DMA after a bus reset
63 - safely obtain and release ISO Tx channels in cooperation with OHCI driver
64 - map received DIF blocks to their proper location in DV frame (ensure
65 recovery if dropped packet)
66 - handle bus resets gracefully (OHCI card seems to take care of this itself(!))
67 - do not allow resizing the user_buf once allocated; eliminate nuke_buffer_mappings
68 - eliminated #ifdef DV1394_DEBUG_LEVEL by inventing macros debug_printk and irq_printk
69 - added wmb() and mb() to places where PCI read/write ordering needs to be enforced
70 - set video->id correctly
71 - store video_cards in an array indexed by OHCI card ID, rather than a list
72 - implement DMA context allocation to cooperate with other users of the OHCI
73 - fix all XXX showstoppers
74 - disable IR/IT DMA interrupts on shutdown
75 - flush pci writes to the card by issuing a read
76 - devfs and character device dispatching (* needs testing with Linux 2.2.x)
77 - switch over to the new kernel DMA API (pci_map_*()) (* needs testing on platforms with IOMMU!)
78 - keep all video_cards in a list (for open() via chardev), set file->private_data = video
79 - dv1394_poll should indicate POLLIN when receiving buffers are available
80 - add proc fs interface to set cip_n, cip_d, syt_offset, and video signal
81 - expose xmit and recv as separate devices (not exclusive)
82 - expose NTSC and PAL as separate devices (can be overridden)
86 #include <linux/config.h>
87 #include <linux/kernel.h>
88 #include <linux/list.h>
89 #include <linux/slab.h>
90 #include <linux/interrupt.h>
91 #include <linux/wait.h>
92 #include <linux/errno.h>
93 #include <linux/module.h>
94 #include <linux/init.h>
95 #include <linux/pci.h>
97 #include <linux/poll.h>
98 #include <linux/smp_lock.h>
99 #include <linux/bitops.h>
100 #include <asm/byteorder.h>
101 #include <asm/atomic.h>
103 #include <asm/uaccess.h>
104 #include <linux/delay.h>
105 #include <asm/pgtable.h>
106 #include <asm/page.h>
107 #include <linux/sched.h>
108 #include <linux/types.h>
109 #include <linux/vmalloc.h>
110 #include <linux/string.h>
111 #include <linux/ioctl32.h>
112 #include <linux/compat.h>
113 #include <linux/cdev.h>
115 #include "ieee1394.h"
116 #include "ieee1394_types.h"
119 #include "ieee1394_core.h"
120 #include "highlevel.h"
122 #include "dv1394-private.h"
124 #include "ohci1394.h"
127 #define virt_to_page(x) MAP_NR(x)
131 #define vmalloc_32(x) vmalloc(x)
136 0 - no debugging messages
137 1 - some debugging messages, but none during DMA frame transmission
138 2 - lots of messages, including during DMA frame transmission
139 (will cause undeflows if your machine is too slow!)
142 #define DV1394_DEBUG_LEVEL 0
144 /* for debugging use ONLY: allow more than one open() of the device */
145 /* #define DV1394_ALLOW_MORE_THAN_ONE_OPEN 1 */
147 #if DV1394_DEBUG_LEVEL >= 2
148 #define irq_printk( args... ) printk( args )
150 #define irq_printk( args... )
153 #if DV1394_DEBUG_LEVEL >= 1
154 #define debug_printk( args... ) printk( args)
156 #define debug_printk( args... )
159 /* issue a dummy PCI read to force the preceding write
160 to be posted to the PCI bus immediately */
162 static inline void flush_pci_write(struct ti_ohci *ohci)
165 reg_read(ohci, OHCI1394_IsochronousCycleTimer);
168 static void it_tasklet_func(unsigned long data);
169 static void ir_tasklet_func(unsigned long data);
173 /* list of all video_cards */
174 static LIST_HEAD(dv1394_cards);
175 static spinlock_t dv1394_cards_lock = SPIN_LOCK_UNLOCKED;
177 /* translate from a struct file* to the corresponding struct video_card* */
179 static inline struct video_card* file_to_video_card(struct file *file)
181 return (struct video_card*) file->private_data;
184 /*** FRAME METHODS *********************************************************/
186 static void frame_reset(struct frame *f)
188 f->state = FRAME_CLEAR;
191 f->frame_begin_timestamp = NULL;
192 f->assigned_timestamp = 0;
195 f->mid_frame_timestamp = NULL;
196 f->frame_end_timestamp = NULL;
197 f->frame_end_branch = NULL;
200 static struct frame* frame_new(unsigned int frame_num, struct video_card *video)
202 struct frame *f = kmalloc(sizeof(*f), GFP_KERNEL);
207 f->frame_num = frame_num;
209 f->header_pool = pci_alloc_consistent(f->video->ohci->dev, PAGE_SIZE, &f->header_pool_dma);
210 if (!f->header_pool) {
211 printk(KERN_ERR "dv1394: failed to allocate CIP header pool\n");
216 debug_printk("dv1394: frame_new: allocated CIP header pool at virt 0x%08lx (contig) dma 0x%08lx size %ld\n",
217 (unsigned long) f->header_pool, (unsigned long) f->header_pool_dma, PAGE_SIZE);
219 f->descriptor_pool_size = MAX_PACKETS * sizeof(struct DMA_descriptor_block);
220 /* make it an even # of pages */
221 f->descriptor_pool_size += PAGE_SIZE - (f->descriptor_pool_size%PAGE_SIZE);
223 f->descriptor_pool = pci_alloc_consistent(f->video->ohci->dev,
224 f->descriptor_pool_size,
225 &f->descriptor_pool_dma);
226 if (!f->descriptor_pool) {
227 pci_free_consistent(f->video->ohci->dev, PAGE_SIZE, f->header_pool, f->header_pool_dma);
232 debug_printk("dv1394: frame_new: allocated DMA program memory at virt 0x%08lx (contig) dma 0x%08lx size %ld\n",
233 (unsigned long) f->descriptor_pool, (unsigned long) f->descriptor_pool_dma, f->descriptor_pool_size);
241 static void frame_delete(struct frame *f)
243 pci_free_consistent(f->video->ohci->dev, PAGE_SIZE, f->header_pool, f->header_pool_dma);
244 pci_free_consistent(f->video->ohci->dev, f->descriptor_pool_size, f->descriptor_pool, f->descriptor_pool_dma);
252 frame_prepare() - build the DMA program for transmitting
254 Frame_prepare() must be called OUTSIDE the video->spinlock.
255 However, frame_prepare() must still be serialized, so
256 it should be called WITH the video->sem taken.
259 static void frame_prepare(struct video_card *video, unsigned int this_frame)
261 struct frame *f = video->frames[this_frame];
264 struct DMA_descriptor_block *block;
265 dma_addr_t block_dma;
266 struct CIP_header *cip;
269 unsigned int n_descriptors, full_packets, packets_per_frame, payload_size;
271 /* these flags denote packets that need special attention */
272 int empty_packet, first_packet, last_packet, mid_packet;
274 u32 *branch_address, *last_branch_address = NULL;
275 unsigned long data_p;
276 int first_packet_empty = 0;
277 u32 cycleTimer, ct_sec, ct_cyc, ct_off;
278 unsigned long irq_flags;
280 irq_printk("frame_prepare( %d ) ---------------------\n", this_frame);
286 if (video->pal_or_ntsc == DV1394_PAL)
287 packets_per_frame = DV1394_PAL_PACKETS_PER_FRAME;
289 packets_per_frame = DV1394_NTSC_PACKETS_PER_FRAME;
291 while ( full_packets < packets_per_frame ) {
292 empty_packet = first_packet = last_packet = mid_packet = 0;
294 data_p = f->data + full_packets * 480;
296 /************************************************/
297 /* allocate a descriptor block and a CIP header */
298 /************************************************/
300 /* note: these should NOT cross a page boundary (DMA restriction) */
302 if (f->n_packets >= MAX_PACKETS) {
303 printk(KERN_ERR "dv1394: FATAL ERROR: max packet count exceeded\n");
307 /* the block surely won't cross a page boundary,
308 since an even number of descriptor_blocks fit on a page */
309 block = &(f->descriptor_pool[f->n_packets]);
311 /* DMA address of the block = offset of block relative
312 to the kernel base address of the descriptor pool
313 + DMA base address of the descriptor pool */
314 block_dma = ((unsigned long) block - (unsigned long) f->descriptor_pool) + f->descriptor_pool_dma;
317 /* the whole CIP pool fits on one page, so no worries about boundaries */
318 if ( ((unsigned long) &(f->header_pool[f->n_packets]) - (unsigned long) f->header_pool)
320 printk(KERN_ERR "dv1394: FATAL ERROR: no room to allocate CIP header\n");
324 cip = &(f->header_pool[f->n_packets]);
326 /* DMA address of the CIP header = offset of cip
327 relative to kernel base address of the header pool
328 + DMA base address of the header pool */
329 cip_dma = (unsigned long) cip % PAGE_SIZE + f->header_pool_dma;
331 /* is this an empty packet? */
333 if (video->cip_accum > (video->cip_d - video->cip_n)) {
336 video->cip_accum -= (video->cip_d - video->cip_n);
339 video->cip_accum += video->cip_n;
342 /* there are three important packets each frame:
344 the first packet in the frame - we ask the card to record the timestamp when
345 this packet is actually sent, so we can monitor
346 how accurate our timestamps are. Also, the first
347 packet serves as a semaphore to let us know that
348 it's OK to free the *previous* frame's DMA buffer
350 the last packet in the frame - this packet is used to detect buffer underflows.
351 if this is the last ready frame, the last DMA block
352 will have a branch back to the beginning of the frame
353 (so that the card will re-send the frame on underflow).
354 if this branch gets taken, we know that at least one
355 frame has been dropped. When the next frame is ready,
356 the branch is pointed to its first packet, and the
357 semaphore is disabled.
359 a "mid" packet slightly before the end of the frame - this packet should trigger
360 an interrupt so we can go and assign a timestamp to the first packet
361 in the next frame. We don't use the very last packet in the frame
362 for this purpose, because that would leave very little time to set
363 the timestamp before DMA starts on the next frame.
366 if (f->n_packets == 0) {
368 } else if ( full_packets == (packets_per_frame-1) ) {
370 } else if (f->n_packets == packets_per_frame) {
375 /********************/
376 /* setup CIP header */
377 /********************/
379 /* the timestamp will be written later from the
380 mid-frame interrupt handler. For now we just
381 store the address of the CIP header(s) that
384 /* first packet in the frame needs a timestamp */
388 first_packet_empty = 1;
390 } else if (first_packet_empty && (f->n_packets == 1) ) {
391 /* if the first packet was empty, the second
392 packet's CIP header also needs a timestamp */
397 /* the node ID number of the OHCI card */
398 reg_read(video->ohci, OHCI1394_NodeID) & 0x3F,
399 video->continuity_counter,
401 0xFFFF /* the timestamp is filled in later */);
403 /* advance counter, only for full packets */
404 if ( ! empty_packet )
405 video->continuity_counter++;
407 /******************************/
408 /* setup DMA descriptor block */
409 /******************************/
411 /* first descriptor - OUTPUT_MORE_IMMEDIATE, for the controller's IT header */
412 fill_output_more_immediate( &(block->u.out.omi), 1, video->channel, 0, payload_size);
415 /* second descriptor - OUTPUT_LAST for CIP header */
416 fill_output_last( &(block->u.out.u.empty.ol),
418 /* want completion status on all interesting packets */
419 (first_packet || mid_packet || last_packet) ? 1 : 0,
421 /* want interrupts on all interesting packets */
422 (first_packet || mid_packet || last_packet) ? 1 : 0,
424 sizeof(struct CIP_header), /* data size */
428 f->frame_begin_timestamp = &(block->u.out.u.empty.ol.q[3]);
430 f->mid_frame_timestamp = &(block->u.out.u.empty.ol.q[3]);
431 else if (last_packet) {
432 f->frame_end_timestamp = &(block->u.out.u.empty.ol.q[3]);
433 f->frame_end_branch = &(block->u.out.u.empty.ol.q[2]);
436 branch_address = &(block->u.out.u.empty.ol.q[2]);
439 f->first_n_descriptors = n_descriptors;
441 } else { /* full packet */
443 /* second descriptor - OUTPUT_MORE for CIP header */
444 fill_output_more( &(block->u.out.u.full.om),
445 sizeof(struct CIP_header), /* data size */
449 /* third (and possibly fourth) descriptor - for DV data */
450 /* the 480-byte payload can cross a page boundary; if so,
451 we need to split it into two DMA descriptors */
453 /* does the 480-byte data payload cross a page boundary? */
454 if ( (PAGE_SIZE- ((unsigned long)data_p % PAGE_SIZE) ) < 480 ) {
456 /* page boundary crossed */
458 fill_output_more( &(block->u.out.u.full.u.cross.om),
459 /* data size - how much of data_p fits on the first page */
460 PAGE_SIZE - (data_p % PAGE_SIZE),
462 /* DMA address of data_p */
463 dma_region_offset_to_bus(&video->dv_buf,
464 data_p - (unsigned long) video->dv_buf.kvirt));
466 fill_output_last( &(block->u.out.u.full.u.cross.ol),
468 /* want completion status on all interesting packets */
469 (first_packet || mid_packet || last_packet) ? 1 : 0,
471 /* want interrupt on all interesting packets */
472 (first_packet || mid_packet || last_packet) ? 1 : 0,
474 /* data size - remaining portion of data_p */
475 480 - (PAGE_SIZE - (data_p % PAGE_SIZE)),
477 /* DMA address of data_p + PAGE_SIZE - (data_p % PAGE_SIZE) */
478 dma_region_offset_to_bus(&video->dv_buf,
479 data_p + PAGE_SIZE - (data_p % PAGE_SIZE) - (unsigned long) video->dv_buf.kvirt));
482 f->frame_begin_timestamp = &(block->u.out.u.full.u.cross.ol.q[3]);
484 f->mid_frame_timestamp = &(block->u.out.u.full.u.cross.ol.q[3]);
485 else if (last_packet) {
486 f->frame_end_timestamp = &(block->u.out.u.full.u.cross.ol.q[3]);
487 f->frame_end_branch = &(block->u.out.u.full.u.cross.ol.q[2]);
490 branch_address = &(block->u.out.u.full.u.cross.ol.q[2]);
494 f->first_n_descriptors = n_descriptors;
499 /* fits on one page */
501 fill_output_last( &(block->u.out.u.full.u.nocross.ol),
503 /* want completion status on all interesting packets */
504 (first_packet || mid_packet || last_packet) ? 1 : 0,
506 /* want interrupt on all interesting packets */
507 (first_packet || mid_packet || last_packet) ? 1 : 0,
509 480, /* data size (480 bytes of DV data) */
512 /* DMA address of data_p */
513 dma_region_offset_to_bus(&video->dv_buf,
514 data_p - (unsigned long) video->dv_buf.kvirt));
517 f->frame_begin_timestamp = &(block->u.out.u.full.u.nocross.ol.q[3]);
519 f->mid_frame_timestamp = &(block->u.out.u.full.u.nocross.ol.q[3]);
520 else if (last_packet) {
521 f->frame_end_timestamp = &(block->u.out.u.full.u.nocross.ol.q[3]);
522 f->frame_end_branch = &(block->u.out.u.full.u.nocross.ol.q[2]);
525 branch_address = &(block->u.out.u.full.u.nocross.ol.q[2]);
529 f->first_n_descriptors = n_descriptors;
535 /* link this descriptor block into the DMA program by filling in
536 the branch address of the previous block */
538 /* note: we are not linked into the active DMA chain yet */
540 if (last_branch_address) {
541 *(last_branch_address) = cpu_to_le32(block_dma | n_descriptors);
544 last_branch_address = branch_address;
551 /* when we first assemble a new frame, set the final branch
552 to loop back up to the top */
553 *(f->frame_end_branch) = cpu_to_le32(f->descriptor_pool_dma | f->first_n_descriptors);
555 /* make the latest version of this frame visible to the PCI card */
556 dma_region_sync_for_device(&video->dv_buf, f->data - (unsigned long) video->dv_buf.kvirt, video->frame_size);
558 /* lock against DMA interrupt */
559 spin_lock_irqsave(&video->spinlock, irq_flags);
561 f->state = FRAME_READY;
563 video->n_clear_frames--;
565 last_frame = video->first_clear_frame - 1;
566 if (last_frame == -1)
567 last_frame = video->n_frames-1;
569 video->first_clear_frame = (video->first_clear_frame + 1) % video->n_frames;
571 irq_printk(" frame %d prepared, active_frame = %d, n_clear_frames = %d, first_clear_frame = %d\n last=%d\n",
572 this_frame, video->active_frame, video->n_clear_frames, video->first_clear_frame, last_frame);
574 irq_printk(" begin_ts %08lx mid_ts %08lx end_ts %08lx end_br %08lx\n",
575 (unsigned long) f->frame_begin_timestamp,
576 (unsigned long) f->mid_frame_timestamp,
577 (unsigned long) f->frame_end_timestamp,
578 (unsigned long) f->frame_end_branch);
580 if (video->active_frame != -1) {
582 /* if DMA is already active, we are almost done */
583 /* just link us onto the active DMA chain */
584 if (video->frames[last_frame]->frame_end_branch) {
587 /* point the previous frame's tail to this frame's head */
588 *(video->frames[last_frame]->frame_end_branch) = cpu_to_le32(f->descriptor_pool_dma | f->first_n_descriptors);
590 /* this write MUST precede the next one, or we could silently drop frames */
593 /* disable the want_status semaphore on the last packet */
594 temp = le32_to_cpu(*(video->frames[last_frame]->frame_end_branch - 2));
596 *(video->frames[last_frame]->frame_end_branch - 2) = cpu_to_le32(temp);
598 /* flush these writes to memory ASAP */
599 flush_pci_write(video->ohci);
602 ideally the writes should be "atomic": if
603 the OHCI card reads the want_status flag in
604 between them, we'll falsely report a
605 dropped frame. Hopefully this window is too
606 small to really matter, and the consequence
607 is rather harmless. */
610 irq_printk(" new frame %d linked onto DMA chain\n", this_frame);
613 printk(KERN_ERR "dv1394: last frame not ready???\n");
618 u32 transmit_sec, transmit_cyc;
621 /* DMA is stopped, so this is the very first frame */
622 video->active_frame = this_frame;
624 /* set CommandPtr to address and size of first descriptor block */
625 reg_write(video->ohci, video->ohci_IsoXmitCommandPtr,
626 video->frames[video->active_frame]->descriptor_pool_dma |
627 f->first_n_descriptors);
629 /* assign a timestamp based on the current cycle time...
630 We'll tell the card to begin DMA 100 cycles from now,
631 and assign a timestamp 103 cycles from now */
633 cycleTimer = reg_read(video->ohci, OHCI1394_IsochronousCycleTimer);
635 ct_sec = cycleTimer >> 25;
636 ct_cyc = (cycleTimer >> 12) & 0x1FFF;
637 ct_off = cycleTimer & 0xFFF;
639 transmit_sec = ct_sec;
640 transmit_cyc = ct_cyc + 100;
642 transmit_sec += transmit_cyc/8000;
643 transmit_cyc %= 8000;
646 ts_cyc = transmit_cyc + 3;
649 f->assigned_timestamp = (ts_cyc&0xF) << 12;
651 /* now actually write the timestamp into the appropriate CIP headers */
653 f->cip_syt1->b[6] = f->assigned_timestamp >> 8;
654 f->cip_syt1->b[7] = f->assigned_timestamp & 0xFF;
657 f->cip_syt2->b[6] = f->assigned_timestamp >> 8;
658 f->cip_syt2->b[7] = f->assigned_timestamp & 0xFF;
661 /* --- start DMA --- */
663 /* clear all bits in ContextControl register */
665 reg_write(video->ohci, video->ohci_IsoXmitContextControlClear, 0xFFFFFFFF);
668 /* the OHCI card has the ability to start ISO transmission on a
669 particular cycle (start-on-cycle). This way we can ensure that
670 the first DV frame will have an accurate timestamp.
672 However, start-on-cycle only appears to work if the OHCI card
673 is cycle master! Since the consequences of messing up the first
674 timestamp are minimal*, just disable start-on-cycle for now.
676 * my DV deck drops the first few frames before it "locks in;"
677 so the first frame having an incorrect timestamp is inconsequential.
681 reg_write(video->ohci, video->ohci_IsoXmitContextControlSet,
682 (1 << 31) /* enable start-on-cycle */
683 | ( (transmit_sec & 0x3) << 29)
684 | (transmit_cyc << 16));
688 video->dma_running = 1;
690 /* set the 'run' bit */
691 reg_write(video->ohci, video->ohci_IsoXmitContextControlSet, 0x8000);
692 flush_pci_write(video->ohci);
694 /* --- DMA should be running now --- */
696 debug_printk(" Cycle = %4u ContextControl = %08x CmdPtr = %08x\n",
697 (reg_read(video->ohci, OHCI1394_IsochronousCycleTimer) >> 12) & 0x1FFF,
698 reg_read(video->ohci, video->ohci_IsoXmitContextControlSet),
699 reg_read(video->ohci, video->ohci_IsoXmitCommandPtr));
701 debug_printk(" DMA start - current cycle %4u, transmit cycle %4u (%2u), assigning ts cycle %2u\n",
702 ct_cyc, transmit_cyc, transmit_cyc & 0xF, ts_cyc & 0xF);
704 #if DV1394_DEBUG_LEVEL >= 2
706 /* check if DMA is really running */
711 if (reg_read(video->ohci, video->ohci_IsoXmitContextControlSet) & (1 << 10)) {
712 printk("DMA ACTIVE after %d msec\n", i);
718 printk("set = %08x, cmdPtr = %08x\n",
719 reg_read(video->ohci, video->ohci_IsoXmitContextControlSet),
720 reg_read(video->ohci, video->ohci_IsoXmitCommandPtr)
723 if ( ! (reg_read(video->ohci, video->ohci_IsoXmitContextControlSet) & (1 << 10)) ) {
724 printk("DMA did NOT go active after 20ms, event = %x\n",
725 reg_read(video->ohci, video->ohci_IsoXmitContextControlSet) & 0x1F);
727 printk("DMA is RUNNING!\n");
734 spin_unlock_irqrestore(&video->spinlock, irq_flags);
739 /*** RECEIVE FUNCTIONS *****************************************************/
742 frame method put_packet
744 map and copy the packet data to its location in the frame
745 based upon DIF section and sequence
749 frame_put_packet (struct frame *f, struct packet *p)
751 int section_type = p->data[0] >> 5; /* section type is in bits 5 - 7 */
752 int dif_sequence = p->data[1] >> 4; /* dif sequence number is in bits 4 - 7 */
753 int dif_block = p->data[2];
756 if (dif_sequence > 11 || dif_block > 149) return;
758 switch (section_type) {
759 case 0: /* 1 Header block */
760 memcpy( (void *) f->data + dif_sequence * 150 * 80, p->data, 480);
763 case 1: /* 2 Subcode blocks */
764 memcpy( (void *) f->data + dif_sequence * 150 * 80 + (1 + dif_block) * 80, p->data, 480);
767 case 2: /* 3 VAUX blocks */
768 memcpy( (void *) f->data + dif_sequence * 150 * 80 + (3 + dif_block) * 80, p->data, 480);
771 case 3: /* 9 Audio blocks interleaved with video */
772 memcpy( (void *) f->data + dif_sequence * 150 * 80 + (6 + dif_block * 16) * 80, p->data, 480);
775 case 4: /* 135 Video blocks interleaved with audio */
776 memcpy( (void *) f->data + dif_sequence * 150 * 80 + (7 + (dif_block / 15) + dif_block) * 80, p->data, 480);
779 default: /* we can not handle any other data */
785 static void start_dma_receive(struct video_card *video)
787 if (video->first_run == 1) {
788 video->first_run = 0;
790 /* start DMA once all of the frames are READY */
791 video->n_clear_frames = 0;
792 video->first_clear_frame = -1;
793 video->current_packet = 0;
794 video->active_frame = 0;
796 /* reset iso recv control register */
797 reg_write(video->ohci, video->ohci_IsoRcvContextControlClear, 0xFFFFFFFF);
800 /* clear bufferFill, set isochHeader and speed (0=100) */
801 reg_write(video->ohci, video->ohci_IsoRcvContextControlSet, 0x40000000);
803 /* match on all tags, listen on channel */
804 reg_write(video->ohci, video->ohci_IsoRcvContextMatch, 0xf0000000 | video->channel);
806 /* address and first descriptor block + Z=1 */
807 reg_write(video->ohci, video->ohci_IsoRcvCommandPtr,
808 video->frames[0]->descriptor_pool_dma | 1); /* Z=1 */
811 video->dma_running = 1;
814 reg_write(video->ohci, video->ohci_IsoRcvContextControlSet, 0x8000);
815 flush_pci_write(video->ohci);
817 debug_printk("dv1394: DMA started\n");
819 #if DV1394_DEBUG_LEVEL >= 2
823 for (i = 0; i < 1000; ++i) {
825 if (reg_read(video->ohci, video->ohci_IsoRcvContextControlSet) & (1 << 10)) {
826 printk("DMA ACTIVE after %d msec\n", i);
830 if ( reg_read(video->ohci, video->ohci_IsoRcvContextControlSet) & (1 << 11) ) {
831 printk("DEAD, event = %x\n",
832 reg_read(video->ohci, video->ohci_IsoRcvContextControlSet) & 0x1F);
834 printk("RUNNING!\n");
837 } else if ( reg_read(video->ohci, video->ohci_IsoRcvContextControlSet) & (1 << 11) ) {
838 debug_printk("DEAD, event = %x\n",
839 reg_read(video->ohci, video->ohci_IsoRcvContextControlSet) & 0x1F);
842 reg_write(video->ohci, video->ohci_IsoRcvContextControlSet, (1 << 12));
848 receive_packets() - build the DMA program for receiving
851 static void receive_packets(struct video_card *video)
853 struct DMA_descriptor_block *block = NULL;
854 dma_addr_t block_dma = 0;
855 struct packet *data = NULL;
856 dma_addr_t data_dma = 0;
857 u32 *last_branch_address = NULL;
858 unsigned long irq_flags;
859 int want_interrupt = 0;
860 struct frame *f = NULL;
863 spin_lock_irqsave(&video->spinlock, irq_flags);
865 for (j = 0; j < video->n_frames; j++) {
868 if (j > 0 && f != NULL && f->frame_end_branch != NULL)
869 *(f->frame_end_branch) = cpu_to_le32(video->frames[j]->descriptor_pool_dma | 1); /* set Z=1 */
871 f = video->frames[j];
873 for (i = 0; i < MAX_PACKETS; i++) {
874 /* locate a descriptor block and packet from the buffer */
875 block = &(f->descriptor_pool[i]);
876 block_dma = ((unsigned long) block - (unsigned long) f->descriptor_pool) + f->descriptor_pool_dma;
878 data = ((struct packet*)video->packet_buf.kvirt) + f->frame_num * MAX_PACKETS + i;
879 data_dma = dma_region_offset_to_bus( &video->packet_buf,
880 ((unsigned long) data - (unsigned long) video->packet_buf.kvirt) );
882 /* setup DMA descriptor block */
883 want_interrupt = ((i % (MAX_PACKETS/2)) == 0 || i == (MAX_PACKETS-1));
884 fill_input_last( &(block->u.in.il), want_interrupt, 512, data_dma);
886 /* link descriptors */
887 last_branch_address = f->frame_end_branch;
889 if (last_branch_address != NULL)
890 *(last_branch_address) = cpu_to_le32(block_dma | 1); /* set Z=1 */
892 f->frame_end_branch = &(block->u.in.il.q[2]);
897 spin_unlock_irqrestore(&video->spinlock, irq_flags);
903 /*** MANAGEMENT FUNCTIONS **************************************************/
905 static int do_dv1394_init(struct video_card *video, struct dv1394_init *init)
907 unsigned long flags, new_buf_size;
910 int retval = -EINVAL;
912 debug_printk("dv1394: initialising %d\n", video->id);
913 if (init->api_version != DV1394_API_VERSION)
916 /* first sanitize all the parameters */
917 if ( (init->n_frames < 2) || (init->n_frames > DV1394_MAX_FRAMES) )
920 if ( (init->format != DV1394_NTSC) && (init->format != DV1394_PAL) )
923 if ( (init->syt_offset == 0) || (init->syt_offset > 50) )
924 /* default SYT offset is 3 cycles */
925 init->syt_offset = 3;
927 if ( (init->channel > 63) || (init->channel < 0) )
930 chan_mask = (u64)1 << init->channel;
932 /* calculate what size DMA buffer is needed */
933 if (init->format == DV1394_NTSC)
934 new_buf_size = DV1394_NTSC_FRAME_SIZE * init->n_frames;
936 new_buf_size = DV1394_PAL_FRAME_SIZE * init->n_frames;
938 /* round up to PAGE_SIZE */
939 if (new_buf_size % PAGE_SIZE) new_buf_size += PAGE_SIZE - (new_buf_size % PAGE_SIZE);
941 /* don't allow the user to allocate the DMA buffer more than once */
942 if (video->dv_buf.kvirt && video->dv_buf_size != new_buf_size) {
943 printk("dv1394: re-sizing the DMA buffer is not allowed\n");
947 /* shutdown the card if it's currently active */
948 /* (the card should not be reset if the parameters are screwy) */
950 do_dv1394_shutdown(video, 0);
952 /* try to claim the ISO channel */
953 spin_lock_irqsave(&video->ohci->IR_channel_lock, flags);
954 if (video->ohci->ISO_channel_usage & chan_mask) {
955 spin_unlock_irqrestore(&video->ohci->IR_channel_lock, flags);
959 video->ohci->ISO_channel_usage |= chan_mask;
960 spin_unlock_irqrestore(&video->ohci->IR_channel_lock, flags);
962 video->channel = init->channel;
964 /* initialize misc. fields of video */
965 video->n_frames = init->n_frames;
966 video->pal_or_ntsc = init->format;
968 video->cip_accum = 0;
969 video->continuity_counter = 0;
971 video->active_frame = -1;
972 video->first_clear_frame = 0;
973 video->n_clear_frames = video->n_frames;
974 video->dropped_frames = 0;
976 video->write_off = 0;
978 video->first_run = 1;
979 video->current_packet = -1;
980 video->first_frame = 0;
982 if (video->pal_or_ntsc == DV1394_NTSC) {
983 video->cip_n = init->cip_n != 0 ? init->cip_n : CIP_N_NTSC;
984 video->cip_d = init->cip_d != 0 ? init->cip_d : CIP_D_NTSC;
985 video->frame_size = DV1394_NTSC_FRAME_SIZE;
987 video->cip_n = init->cip_n != 0 ? init->cip_n : CIP_N_PAL;
988 video->cip_d = init->cip_d != 0 ? init->cip_d : CIP_D_PAL;
989 video->frame_size = DV1394_PAL_FRAME_SIZE;
992 video->syt_offset = init->syt_offset;
994 /* find and claim DMA contexts on the OHCI card */
996 if (video->ohci_it_ctx == -1) {
997 ohci1394_init_iso_tasklet(&video->it_tasklet, OHCI_ISO_TRANSMIT,
998 it_tasklet_func, (unsigned long) video);
1000 if (ohci1394_register_iso_tasklet(video->ohci, &video->it_tasklet) < 0) {
1001 printk(KERN_ERR "dv1394: could not find an available IT DMA context\n");
1006 video->ohci_it_ctx = video->it_tasklet.context;
1007 debug_printk("dv1394: claimed IT DMA context %d\n", video->ohci_it_ctx);
1010 if (video->ohci_ir_ctx == -1) {
1011 ohci1394_init_iso_tasklet(&video->ir_tasklet, OHCI_ISO_RECEIVE,
1012 ir_tasklet_func, (unsigned long) video);
1014 if (ohci1394_register_iso_tasklet(video->ohci, &video->ir_tasklet) < 0) {
1015 printk(KERN_ERR "dv1394: could not find an available IR DMA context\n");
1019 video->ohci_ir_ctx = video->ir_tasklet.context;
1020 debug_printk("dv1394: claimed IR DMA context %d\n", video->ohci_ir_ctx);
1023 /* allocate struct frames */
1024 for (i = 0; i < init->n_frames; i++) {
1025 video->frames[i] = frame_new(i, video);
1027 if (!video->frames[i]) {
1028 printk(KERN_ERR "dv1394: Cannot allocate frame structs\n");
1034 if (!video->dv_buf.kvirt) {
1035 /* allocate the ringbuffer */
1036 retval = dma_region_alloc(&video->dv_buf, new_buf_size, video->ohci->dev, PCI_DMA_TODEVICE);
1040 video->dv_buf_size = new_buf_size;
1042 debug_printk("dv1394: Allocated %d frame buffers, total %u pages (%u DMA pages), %lu bytes\n",
1043 video->n_frames, video->dv_buf.n_pages,
1044 video->dv_buf.n_dma_pages, video->dv_buf_size);
1047 /* set up the frame->data pointers */
1048 for (i = 0; i < video->n_frames; i++)
1049 video->frames[i]->data = (unsigned long) video->dv_buf.kvirt + i * video->frame_size;
1051 if (!video->packet_buf.kvirt) {
1052 /* allocate packet buffer */
1053 video->packet_buf_size = sizeof(struct packet) * video->n_frames * MAX_PACKETS;
1054 if (video->packet_buf_size % PAGE_SIZE)
1055 video->packet_buf_size += PAGE_SIZE - (video->packet_buf_size % PAGE_SIZE);
1057 retval = dma_region_alloc(&video->packet_buf, video->packet_buf_size,
1058 video->ohci->dev, PCI_DMA_FROMDEVICE);
1062 debug_printk("dv1394: Allocated %d packets in buffer, total %u pages (%u DMA pages), %lu bytes\n",
1063 video->n_frames*MAX_PACKETS, video->packet_buf.n_pages,
1064 video->packet_buf.n_dma_pages, video->packet_buf_size);
1067 /* set up register offsets for IT context */
1068 /* IT DMA context registers are spaced 16 bytes apart */
1069 video->ohci_IsoXmitContextControlSet = OHCI1394_IsoXmitContextControlSet+16*video->ohci_it_ctx;
1070 video->ohci_IsoXmitContextControlClear = OHCI1394_IsoXmitContextControlClear+16*video->ohci_it_ctx;
1071 video->ohci_IsoXmitCommandPtr = OHCI1394_IsoXmitCommandPtr+16*video->ohci_it_ctx;
1073 /* enable interrupts for IT context */
1074 reg_write(video->ohci, OHCI1394_IsoXmitIntMaskSet, (1 << video->ohci_it_ctx));
1075 debug_printk("dv1394: interrupts enabled for IT context %d\n", video->ohci_it_ctx);
1077 /* set up register offsets for IR context */
1078 /* IR DMA context registers are spaced 32 bytes apart */
1079 video->ohci_IsoRcvContextControlSet = OHCI1394_IsoRcvContextControlSet+32*video->ohci_ir_ctx;
1080 video->ohci_IsoRcvContextControlClear = OHCI1394_IsoRcvContextControlClear+32*video->ohci_ir_ctx;
1081 video->ohci_IsoRcvCommandPtr = OHCI1394_IsoRcvCommandPtr+32*video->ohci_ir_ctx;
1082 video->ohci_IsoRcvContextMatch = OHCI1394_IsoRcvContextMatch+32*video->ohci_ir_ctx;
1084 /* enable interrupts for IR context */
1085 reg_write(video->ohci, OHCI1394_IsoRecvIntMaskSet, (1 << video->ohci_ir_ctx) );
1086 debug_printk("dv1394: interrupts enabled for IR context %d\n", video->ohci_ir_ctx);
1091 do_dv1394_shutdown(video, 1);
1095 /* if the user doesn't bother to call ioctl(INIT) before starting
1096 mmap() or read()/write(), just give him some default values */
1098 static int do_dv1394_init_default(struct video_card *video)
1100 struct dv1394_init init;
1102 init.api_version = DV1394_API_VERSION;
1103 init.n_frames = DV1394_MAX_FRAMES / 4;
1104 /* the following are now set via devfs */
1105 init.channel = video->channel;
1106 init.format = video->pal_or_ntsc;
1107 init.cip_n = video->cip_n;
1108 init.cip_d = video->cip_d;
1109 init.syt_offset = video->syt_offset;
1111 return do_dv1394_init(video, &init);
1114 /* do NOT call from interrupt context */
1115 static void stop_dma(struct video_card *video)
1117 unsigned long flags;
1121 spin_lock_irqsave(&video->spinlock, flags);
1123 video->dma_running = 0;
1125 if ( (video->ohci_it_ctx == -1) && (video->ohci_ir_ctx == -1) )
1128 /* stop DMA if in progress */
1129 if ( (video->active_frame != -1) ||
1130 (reg_read(video->ohci, video->ohci_IsoXmitContextControlClear) & (1 << 10)) ||
1131 (reg_read(video->ohci, video->ohci_IsoRcvContextControlClear) & (1 << 10)) ) {
1133 /* clear the .run bits */
1134 reg_write(video->ohci, video->ohci_IsoXmitContextControlClear, (1 << 15));
1135 reg_write(video->ohci, video->ohci_IsoRcvContextControlClear, (1 << 15));
1136 flush_pci_write(video->ohci);
1138 video->active_frame = -1;
1139 video->first_run = 1;
1141 /* wait until DMA really stops */
1145 /* wait 0.1 millisecond */
1148 if ( (reg_read(video->ohci, video->ohci_IsoXmitContextControlClear) & (1 << 10)) ||
1149 (reg_read(video->ohci, video->ohci_IsoRcvContextControlClear) & (1 << 10)) ) {
1151 debug_printk("dv1394: stop_dma: DMA not stopped yet\n" );
1154 debug_printk("dv1394: stop_dma: DMA stopped safely after %d ms\n", i/10);
1162 printk(KERN_ERR "dv1394: stop_dma: DMA still going after %d ms!\n", i/10);
1166 debug_printk("dv1394: stop_dma: already stopped.\n");
1169 spin_unlock_irqrestore(&video->spinlock, flags);
1174 static void do_dv1394_shutdown(struct video_card *video, int free_dv_buf)
1178 debug_printk("dv1394: shutdown...\n");
1180 /* stop DMA if in progress */
1183 /* release the DMA contexts */
1184 if (video->ohci_it_ctx != -1) {
1185 video->ohci_IsoXmitContextControlSet = 0;
1186 video->ohci_IsoXmitContextControlClear = 0;
1187 video->ohci_IsoXmitCommandPtr = 0;
1189 /* disable interrupts for IT context */
1190 reg_write(video->ohci, OHCI1394_IsoXmitIntMaskClear, (1 << video->ohci_it_ctx));
1192 /* remove tasklet */
1193 ohci1394_unregister_iso_tasklet(video->ohci, &video->it_tasklet);
1194 debug_printk("dv1394: IT context %d released\n", video->ohci_it_ctx);
1195 video->ohci_it_ctx = -1;
1198 if (video->ohci_ir_ctx != -1) {
1199 video->ohci_IsoRcvContextControlSet = 0;
1200 video->ohci_IsoRcvContextControlClear = 0;
1201 video->ohci_IsoRcvCommandPtr = 0;
1202 video->ohci_IsoRcvContextMatch = 0;
1204 /* disable interrupts for IR context */
1205 reg_write(video->ohci, OHCI1394_IsoRecvIntMaskClear, (1 << video->ohci_ir_ctx));
1207 /* remove tasklet */
1208 ohci1394_unregister_iso_tasklet(video->ohci, &video->ir_tasklet);
1209 debug_printk("dv1394: IR context %d released\n", video->ohci_ir_ctx);
1210 video->ohci_ir_ctx = -1;
1213 /* release the ISO channel */
1214 if (video->channel != -1) {
1216 unsigned long flags;
1218 chan_mask = (u64)1 << video->channel;
1220 spin_lock_irqsave(&video->ohci->IR_channel_lock, flags);
1221 video->ohci->ISO_channel_usage &= ~(chan_mask);
1222 spin_unlock_irqrestore(&video->ohci->IR_channel_lock, flags);
1224 video->channel = -1;
1227 /* free the frame structs */
1228 for (i = 0; i < DV1394_MAX_FRAMES; i++) {
1229 if (video->frames[i])
1230 frame_delete(video->frames[i]);
1231 video->frames[i] = NULL;
1234 video->n_frames = 0;
1236 /* we can't free the DMA buffer unless it is guaranteed that
1237 no more user-space mappings exist */
1240 dma_region_free(&video->dv_buf);
1241 video->dv_buf_size = 0;
1244 /* free packet buffer */
1245 dma_region_free(&video->packet_buf);
1246 video->packet_buf_size = 0;
1248 debug_printk("dv1394: shutdown OK\n");
1252 **********************************
1253 *** MMAP() THEORY OF OPERATION ***
1254 **********************************
1256 The ringbuffer cannot be re-allocated or freed while
1257 a user program maintains a mapping of it. (note that a mapping
1258 can persist even after the device fd is closed!)
1260 So, only let the user process allocate the DMA buffer once.
1261 To resize or deallocate it, you must close the device file
1264 Previously Dan M. hacked out a scheme that allowed the DMA
1265 buffer to change by forcefully unmapping it from the user's
1266 address space. It was prone to error because it's very hard to
1267 track all the places the buffer could have been mapped (we
1268 would have had to walk the vma list of every process in the
1269 system to be sure we found all the mappings!). Instead, we
1270 force the user to choose one buffer size and stick with
1271 it. This small sacrifice is worth the huge reduction in
1272 error-prone code in dv1394.
1275 int dv1394_mmap(struct file *file, struct vm_area_struct *vma)
1277 struct video_card *video = file_to_video_card(file);
1278 int retval = -EINVAL;
1280 /* serialize mmap */
1283 if ( ! video_card_initialized(video) ) {
1284 retval = do_dv1394_init_default(video);
1289 retval = dma_region_mmap(&video->dv_buf, file, vma);
1295 /*** DEVICE FILE INTERFACE *************************************************/
1297 /* no need to serialize, multiple threads OK */
1298 static unsigned int dv1394_poll(struct file *file, struct poll_table_struct *wait)
1300 struct video_card *video = file_to_video_card(file);
1301 unsigned int mask = 0;
1302 unsigned long flags;
1304 poll_wait(file, &video->waitq, wait);
1306 spin_lock_irqsave(&video->spinlock, flags);
1307 if ( video->n_frames == 0 ) {
1309 } else if ( video->active_frame == -1 ) {
1310 /* nothing going on */
1313 /* any clear/ready buffers? */
1314 if (video->n_clear_frames >0)
1315 mask |= POLLOUT | POLLIN;
1317 spin_unlock_irqrestore(&video->spinlock, flags);
1322 static int dv1394_fasync(int fd, struct file *file, int on)
1324 /* I just copied this code verbatim from Alan Cox's mouse driver example
1325 (linux/Documentation/DocBook/) */
1327 struct video_card *video = file_to_video_card(file);
1329 int retval = fasync_helper(fd, file, on, &video->fasync);
1336 static ssize_t dv1394_write(struct file *file, const char *buffer, size_t count, loff_t *ppos)
1338 struct video_card *video = file_to_video_card(file);
1339 DECLARE_WAITQUEUE(wait, current);
1342 unsigned long flags;
1345 /* serialize this to prevent multi-threaded mayhem */
1346 if (file->f_flags & O_NONBLOCK) {
1347 if (down_trylock(&video->sem))
1350 if (down_interruptible(&video->sem))
1351 return -ERESTARTSYS;
1354 if ( !video_card_initialized(video) ) {
1355 ret = do_dv1394_init_default(video);
1363 add_wait_queue(&video->waitq, &wait);
1367 /* must set TASK_INTERRUPTIBLE *before* checking for free
1368 buffers; otherwise we could miss a wakeup if the interrupt
1369 fires between the check and the schedule() */
1371 set_current_state(TASK_INTERRUPTIBLE);
1373 spin_lock_irqsave(&video->spinlock, flags);
1375 target_frame = video->first_clear_frame;
1377 spin_unlock_irqrestore(&video->spinlock, flags);
1379 if (video->frames[target_frame]->state == FRAME_CLEAR) {
1381 /* how much room is left in the target frame buffer */
1382 cnt = video->frame_size - (video->write_off - target_frame * video->frame_size);
1385 /* buffer is already used */
1393 /* no room left, gotta wait */
1394 if (file->f_flags & O_NONBLOCK) {
1399 if (signal_pending(current)) {
1407 continue; /* start over from 'while(count > 0)...' */
1410 if (copy_from_user(video->dv_buf.kvirt + video->write_off, buffer, cnt)) {
1416 video->write_off = (video->write_off + cnt) % (video->n_frames * video->frame_size);
1422 if (video->write_off == video->frame_size * ((target_frame + 1) % video->n_frames))
1423 frame_prepare(video, target_frame);
1426 remove_wait_queue(&video->waitq, &wait);
1427 set_current_state(TASK_RUNNING);
1433 static ssize_t dv1394_read(struct file *file, char *buffer, size_t count, loff_t *ppos)
1435 struct video_card *video = file_to_video_card(file);
1436 DECLARE_WAITQUEUE(wait, current);
1439 unsigned long flags;
1442 /* serialize this to prevent multi-threaded mayhem */
1443 if (file->f_flags & O_NONBLOCK) {
1444 if (down_trylock(&video->sem))
1447 if (down_interruptible(&video->sem))
1448 return -ERESTARTSYS;
1451 if ( !video_card_initialized(video) ) {
1452 ret = do_dv1394_init_default(video);
1457 video->continuity_counter = -1;
1459 receive_packets(video);
1461 start_dma_receive(video);
1465 add_wait_queue(&video->waitq, &wait);
1469 /* must set TASK_INTERRUPTIBLE *before* checking for free
1470 buffers; otherwise we could miss a wakeup if the interrupt
1471 fires between the check and the schedule() */
1473 set_current_state(TASK_INTERRUPTIBLE);
1475 spin_lock_irqsave(&video->spinlock, flags);
1477 target_frame = video->first_clear_frame;
1479 spin_unlock_irqrestore(&video->spinlock, flags);
1481 if (target_frame >= 0 &&
1482 video->n_clear_frames > 0 &&
1483 video->frames[target_frame]->state == FRAME_CLEAR) {
1485 /* how much room is left in the target frame buffer */
1486 cnt = video->frame_size - (video->write_off - target_frame * video->frame_size);
1489 /* buffer is already used */
1497 /* no room left, gotta wait */
1498 if (file->f_flags & O_NONBLOCK) {
1503 if (signal_pending(current)) {
1511 continue; /* start over from 'while(count > 0)...' */
1514 if (copy_to_user(buffer, video->dv_buf.kvirt + video->write_off, cnt)) {
1520 video->write_off = (video->write_off + cnt) % (video->n_frames * video->frame_size);
1526 if (video->write_off == video->frame_size * ((target_frame + 1) % video->n_frames)) {
1527 spin_lock_irqsave(&video->spinlock, flags);
1528 video->n_clear_frames--;
1529 video->first_clear_frame = (video->first_clear_frame + 1) % video->n_frames;
1530 spin_unlock_irqrestore(&video->spinlock, flags);
1534 remove_wait_queue(&video->waitq, &wait);
1535 set_current_state(TASK_RUNNING);
1541 /*** DEVICE IOCTL INTERFACE ************************************************/
1543 /* I *think* the VFS serializes ioctl() for us, so we don't have to worry
1544 about situations like having two threads in here at once... */
1546 static int dv1394_ioctl(struct inode *inode, struct file *file,
1547 unsigned int cmd, unsigned long arg)
1549 struct video_card *video = file_to_video_card(file);
1550 unsigned long flags;
1553 DECLARE_WAITQUEUE(wait, current);
1555 /* serialize this to prevent multi-threaded mayhem */
1556 if (file->f_flags & O_NONBLOCK) {
1557 if (down_trylock(&video->sem))
1560 if (down_interruptible(&video->sem))
1561 return -ERESTARTSYS;
1566 case DV1394_IOC_SUBMIT_FRAMES: {
1567 unsigned int n_submit;
1569 if ( !video_card_initialized(video) ) {
1570 ret = do_dv1394_init_default(video);
1575 n_submit = (unsigned int) arg;
1577 if (n_submit > video->n_frames) {
1582 while (n_submit > 0) {
1584 add_wait_queue(&video->waitq, &wait);
1585 set_current_state(TASK_INTERRUPTIBLE);
1587 spin_lock_irqsave(&video->spinlock, flags);
1589 /* wait until video->first_clear_frame is really CLEAR */
1590 while (video->frames[video->first_clear_frame]->state != FRAME_CLEAR) {
1592 spin_unlock_irqrestore(&video->spinlock, flags);
1594 if (signal_pending(current)) {
1595 remove_wait_queue(&video->waitq, &wait);
1596 set_current_state(TASK_RUNNING);
1602 set_current_state(TASK_INTERRUPTIBLE);
1604 spin_lock_irqsave(&video->spinlock, flags);
1606 spin_unlock_irqrestore(&video->spinlock, flags);
1608 remove_wait_queue(&video->waitq, &wait);
1609 set_current_state(TASK_RUNNING);
1611 frame_prepare(video, video->first_clear_frame);
1620 case DV1394_IOC_WAIT_FRAMES: {
1621 unsigned int n_wait;
1623 if ( !video_card_initialized(video) ) {
1628 n_wait = (unsigned int) arg;
1630 /* since we re-run the last frame on underflow, we will
1631 never actually have n_frames clear frames; at most only
1634 if (n_wait > (video->n_frames-1) ) {
1639 add_wait_queue(&video->waitq, &wait);
1640 set_current_state(TASK_INTERRUPTIBLE);
1642 spin_lock_irqsave(&video->spinlock, flags);
1644 while (video->n_clear_frames < n_wait) {
1646 spin_unlock_irqrestore(&video->spinlock, flags);
1648 if (signal_pending(current)) {
1649 remove_wait_queue(&video->waitq, &wait);
1650 set_current_state(TASK_RUNNING);
1656 set_current_state(TASK_INTERRUPTIBLE);
1658 spin_lock_irqsave(&video->spinlock, flags);
1661 spin_unlock_irqrestore(&video->spinlock, flags);
1663 remove_wait_queue(&video->waitq, &wait);
1664 set_current_state(TASK_RUNNING);
1669 case DV1394_IOC_RECEIVE_FRAMES: {
1670 unsigned int n_recv;
1672 if ( !video_card_initialized(video) ) {
1677 n_recv = (unsigned int) arg;
1679 /* at least one frame must be active */
1680 if (n_recv > (video->n_frames-1) ) {
1685 spin_lock_irqsave(&video->spinlock, flags);
1687 /* release the clear frames */
1688 video->n_clear_frames -= n_recv;
1690 /* advance the clear frame cursor */
1691 video->first_clear_frame = (video->first_clear_frame + n_recv) % video->n_frames;
1693 /* reset dropped_frames */
1694 video->dropped_frames = 0;
1696 spin_unlock_irqrestore(&video->spinlock, flags);
1702 case DV1394_IOC_START_RECEIVE: {
1703 if ( !video_card_initialized(video) ) {
1704 ret = do_dv1394_init_default(video);
1709 video->continuity_counter = -1;
1711 receive_packets(video);
1713 start_dma_receive(video);
1719 case DV1394_IOC_INIT: {
1720 struct dv1394_init init;
1721 if (arg == (unsigned long) NULL) {
1722 ret = do_dv1394_init_default(video);
1724 if (copy_from_user(&init, (void*)arg, sizeof(init))) {
1728 ret = do_dv1394_init(video, &init);
1733 case DV1394_IOC_SHUTDOWN:
1734 do_dv1394_shutdown(video, 0);
1739 case DV1394_IOC_GET_STATUS: {
1740 struct dv1394_status status;
1742 if ( !video_card_initialized(video) ) {
1747 status.init.api_version = DV1394_API_VERSION;
1748 status.init.channel = video->channel;
1749 status.init.n_frames = video->n_frames;
1750 status.init.format = video->pal_or_ntsc;
1751 status.init.cip_n = video->cip_n;
1752 status.init.cip_d = video->cip_d;
1753 status.init.syt_offset = video->syt_offset;
1755 status.first_clear_frame = video->first_clear_frame;
1757 /* the rest of the fields need to be locked against the interrupt */
1758 spin_lock_irqsave(&video->spinlock, flags);
1760 status.active_frame = video->active_frame;
1761 status.n_clear_frames = video->n_clear_frames;
1763 status.dropped_frames = video->dropped_frames;
1765 /* reset dropped_frames */
1766 video->dropped_frames = 0;
1768 spin_unlock_irqrestore(&video->spinlock, flags);
1770 if (copy_to_user((void*)arg, &status, sizeof(status))) {
1790 /*** DEVICE FILE INTERFACE CONTINUED ***************************************/
1792 static int dv1394_open(struct inode *inode, struct file *file)
1794 struct video_card *video = NULL;
1796 /* if the device was opened through devfs, then file->private_data
1797 has already been set to video by devfs */
1798 if (file->private_data) {
1799 video = (struct video_card*) file->private_data;
1802 /* look up the card by ID */
1803 unsigned long flags;
1805 spin_lock_irqsave(&dv1394_cards_lock, flags);
1806 if (!list_empty(&dv1394_cards)) {
1807 struct video_card *p;
1808 list_for_each_entry(p, &dv1394_cards, list) {
1809 if ((p->id) == ieee1394_file_to_instance(file)) {
1815 spin_unlock_irqrestore(&dv1394_cards_lock, flags);
1818 debug_printk("dv1394: OHCI card %d not found", ieee1394_file_to_instance(file));
1822 file->private_data = (void*) video;
1825 #ifndef DV1394_ALLOW_MORE_THAN_ONE_OPEN
1827 if ( test_and_set_bit(0, &video->open) ) {
1828 /* video is already open by someone else */
1838 static int dv1394_release(struct inode *inode, struct file *file)
1840 struct video_card *video = file_to_video_card(file);
1842 /* OK to free the DMA buffer, no more mappings can exist */
1843 do_dv1394_shutdown(video, 1);
1845 /* clean up async I/O users */
1846 dv1394_fasync(-1, file, 0);
1848 /* give someone else a turn */
1849 clear_bit(0, &video->open);
1855 /*** DEVICE DRIVER HANDLERS ************************************************/
1857 static void it_tasklet_func(unsigned long data)
1860 struct video_card *video = (struct video_card*) data;
1862 spin_lock(&video->spinlock);
1864 if (!video->dma_running)
1867 irq_printk("ContextControl = %08x, CommandPtr = %08x\n",
1868 reg_read(video->ohci, video->ohci_IsoXmitContextControlSet),
1869 reg_read(video->ohci, video->ohci_IsoXmitCommandPtr)
1873 if ( (video->ohci_it_ctx != -1) &&
1874 (reg_read(video->ohci, video->ohci_IsoXmitContextControlSet) & (1 << 10)) ) {
1877 unsigned int frame, i;
1880 if (video->active_frame == -1)
1883 frame = video->active_frame;
1885 /* check all the DMA-able frames */
1886 for (i = 0; i < video->n_frames; i++, frame = (frame+1) % video->n_frames) {
1888 irq_printk("IRQ checking frame %d...", frame);
1889 f = video->frames[frame];
1890 if (f->state != FRAME_READY) {
1891 irq_printk("clear, skipping\n");
1892 /* we don't own this frame */
1896 irq_printk("DMA\n");
1898 /* check the frame begin semaphore to see if we can free the previous frame */
1899 if ( *(f->frame_begin_timestamp) ) {
1901 struct frame *prev_f;
1905 /* don't reset, need this later *(f->frame_begin_timestamp) = 0; */
1906 irq_printk(" BEGIN\n");
1908 prev_frame = frame - 1;
1909 if (prev_frame == -1)
1910 prev_frame += video->n_frames;
1911 prev_f = video->frames[prev_frame];
1913 /* make sure we can actually garbage collect
1915 if ( (prev_f->state == FRAME_READY) &&
1916 prev_f->done && (!f->done) )
1918 frame_reset(prev_f);
1919 video->n_clear_frames++;
1921 video->active_frame = frame;
1923 irq_printk(" BEGIN - freeing previous frame %d, new active frame is %d\n", prev_frame, frame);
1925 irq_printk(" BEGIN - can't free yet\n");
1932 /* see if we need to set the timestamp for the next frame */
1933 if ( *(f->mid_frame_timestamp) ) {
1934 struct frame *next_frame;
1935 u32 begin_ts, ts_cyc, ts_off;
1937 *(f->mid_frame_timestamp) = 0;
1939 begin_ts = le32_to_cpu(*(f->frame_begin_timestamp));
1941 irq_printk(" MIDDLE - first packet was sent at cycle %4u (%2u), assigned timestamp was (%2u) %4u\n",
1942 begin_ts & 0x1FFF, begin_ts & 0xF,
1943 f->assigned_timestamp >> 12, f->assigned_timestamp & 0xFFF);
1945 /* prepare next frame and assign timestamp */
1946 next_frame = video->frames[ (frame+1) % video->n_frames ];
1948 if (next_frame->state == FRAME_READY) {
1949 irq_printk(" MIDDLE - next frame is ready, good\n");
1951 debug_printk("dv1394: Underflow! At least one frame has been dropped.\n");
1955 /* set the timestamp to the timestamp of the last frame sent,
1956 plus the length of the last frame sent, plus the syt latency */
1957 ts_cyc = begin_ts & 0xF;
1958 /* advance one frame, plus syt latency (typically 2-3) */
1959 ts_cyc += f->n_packets + video->syt_offset ;
1963 ts_cyc += ts_off/3072;
1966 next_frame->assigned_timestamp = ((ts_cyc&0xF) << 12) + ts_off;
1967 if (next_frame->cip_syt1) {
1968 next_frame->cip_syt1->b[6] = next_frame->assigned_timestamp >> 8;
1969 next_frame->cip_syt1->b[7] = next_frame->assigned_timestamp & 0xFF;
1971 if (next_frame->cip_syt2) {
1972 next_frame->cip_syt2->b[6] = next_frame->assigned_timestamp >> 8;
1973 next_frame->cip_syt2->b[7] = next_frame->assigned_timestamp & 0xFF;
1978 /* see if the frame looped */
1979 if ( *(f->frame_end_timestamp) ) {
1981 *(f->frame_end_timestamp) = 0;
1983 debug_printk(" END - the frame looped at least once\n");
1985 video->dropped_frames++;
1988 } /* for (each frame) */
1992 kill_fasync(&video->fasync, SIGIO, POLL_OUT);
1994 /* wake readers/writers/ioctl'ers */
1995 wake_up_interruptible(&video->waitq);
1999 spin_unlock(&video->spinlock);
2002 static void ir_tasklet_func(unsigned long data)
2005 struct video_card *video = (struct video_card*) data;
2007 spin_lock(&video->spinlock);
2009 if (!video->dma_running)
2012 if ( (video->ohci_ir_ctx != -1) &&
2013 (reg_read(video->ohci, video->ohci_IsoRcvContextControlSet) & (1 << 10)) ) {
2015 int sof=0; /* start-of-frame flag */
2017 u16 packet_length, packet_time;
2019 struct DMA_descriptor_block *block = NULL;
2023 struct DMA_descriptor_block *next = NULL;
2024 dma_addr_t next_dma = 0;
2025 struct DMA_descriptor_block *prev = NULL;
2027 /* loop over all descriptors in all frames */
2028 for (i = 0; i < video->n_frames*MAX_PACKETS; i++) {
2029 struct packet *p = dma_region_i(&video->packet_buf, struct packet, video->current_packet);
2031 /* make sure we are seeing the latest changes to p */
2032 dma_region_sync_for_cpu(&video->packet_buf,
2033 (unsigned long) p - (unsigned long) video->packet_buf.kvirt,
2034 sizeof(struct packet));
2036 packet_length = le16_to_cpu(p->data_length);
2037 packet_time = le16_to_cpu(p->timestamp);
2039 irq_printk("received packet %02d, timestamp=%04x, length=%04x, sof=%02x%02x\n", video->current_packet,
2040 packet_time, packet_length,
2041 p->data[0], p->data[1]);
2043 /* get the descriptor based on packet_buffer cursor */
2044 f = video->frames[video->current_packet / MAX_PACKETS];
2045 block = &(f->descriptor_pool[video->current_packet % MAX_PACKETS]);
2046 xferstatus = le32_to_cpu(block->u.in.il.q[3]) >> 16;
2048 irq_printk("ir_tasklet_func: xferStatus/resCount [%d] = 0x%08x\n", i, le32_to_cpu(block->u.in.il.q[3]) );
2050 /* get the current frame */
2051 f = video->frames[video->active_frame];
2053 /* exclude empty packet */
2054 if (packet_length > 8 && xferstatus == 0x11) {
2055 /* check for start of frame */
2056 /* DRD> Changed to check section type ([0]>>5==0)
2057 and dif sequence ([1]>>4==0) */
2058 sof = ( (p->data[0] >> 5) == 0 && (p->data[1] >> 4) == 0);
2060 dbc = (int) (p->cip_h1 >> 24);
2061 if ( video->continuity_counter != -1 && dbc > ((video->continuity_counter + 1) % 256) )
2063 printk(KERN_WARNING "dv1394: discontinuity detected, dropping all frames\n" );
2064 video->dropped_frames += video->n_clear_frames + 1;
2065 video->first_frame = 0;
2066 video->n_clear_frames = 0;
2067 video->first_clear_frame = -1;
2069 video->continuity_counter = dbc;
2071 if (!video->first_frame) {
2073 video->first_frame = 1;
2077 /* close current frame */
2078 frame_reset(f); /* f->state = STATE_CLEAR */
2079 video->n_clear_frames++;
2080 if (video->n_clear_frames > video->n_frames) {
2081 video->dropped_frames++;
2082 printk(KERN_WARNING "dv1394: dropped a frame during reception\n" );
2083 video->n_clear_frames = video->n_frames-1;
2084 video->first_clear_frame = (video->first_clear_frame + 1) % video->n_frames;
2086 if (video->first_clear_frame == -1)
2087 video->first_clear_frame = video->active_frame;
2089 /* get the next frame */
2090 video->active_frame = (video->active_frame + 1) % video->n_frames;
2091 f = video->frames[video->active_frame];
2092 irq_printk(" frame received, active_frame = %d, n_clear_frames = %d, first_clear_frame = %d\n",
2093 video->active_frame, video->n_clear_frames, video->first_clear_frame);
2095 if (video->first_frame) {
2097 /* open next frame */
2098 f->state = FRAME_READY;
2101 /* copy to buffer */
2102 if (f->n_packets > (video->frame_size / 480)) {
2103 printk(KERN_ERR "frame buffer overflow during receive\n");
2106 frame_put_packet(f, p);
2111 /* stop, end of ready packets */
2112 else if (xferstatus == 0) {
2116 /* reset xferStatus & resCount */
2117 block->u.in.il.q[3] = cpu_to_le32(512);
2119 /* terminate dma chain at this (next) packet */
2120 next_i = video->current_packet;
2121 f = video->frames[next_i / MAX_PACKETS];
2122 next = &(f->descriptor_pool[next_i % MAX_PACKETS]);
2123 next_dma = ((unsigned long) block - (unsigned long) f->descriptor_pool) + f->descriptor_pool_dma;
2124 next->u.in.il.q[0] |= 3 << 20; /* enable interrupt */
2125 next->u.in.il.q[2] = 0; /* disable branch */
2127 /* link previous to next */
2128 prev_i = (next_i == 0) ? (MAX_PACKETS * video->n_frames - 1) : (next_i - 1);
2129 f = video->frames[prev_i / MAX_PACKETS];
2130 prev = &(f->descriptor_pool[prev_i % MAX_PACKETS]);
2131 if (prev_i % (MAX_PACKETS/2)) {
2132 prev->u.in.il.q[0] &= ~(3 << 20); /* no interrupt */
2134 prev->u.in.il.q[0] |= 3 << 20; /* enable interrupt */
2136 prev->u.in.il.q[2] = cpu_to_le32(next_dma | 1); /* set Z=1 */
2139 /* wake up DMA in case it fell asleep */
2140 reg_write(video->ohci, video->ohci_IsoRcvContextControlSet, (1 << 12));
2142 /* advance packet_buffer cursor */
2143 video->current_packet = (video->current_packet + 1) % (MAX_PACKETS * video->n_frames);
2145 } /* for all packets */
2147 wake = 1; /* why the hell not? */
2149 } /* receive interrupt */
2152 kill_fasync(&video->fasync, SIGIO, POLL_IN);
2154 /* wake readers/writers/ioctl'ers */
2155 wake_up_interruptible(&video->waitq);
2159 spin_unlock(&video->spinlock);
2162 static struct cdev dv1394_cdev;
2163 static struct file_operations dv1394_fops=
2165 .owner = THIS_MODULE,
2166 .poll = dv1394_poll,
2167 .ioctl = dv1394_ioctl,
2168 .mmap = dv1394_mmap,
2169 .open = dv1394_open,
2170 .write = dv1394_write,
2171 .read = dv1394_read,
2172 .release = dv1394_release,
2173 .fasync = dv1394_fasync,
2177 /*** HOTPLUG STUFF **********************************************************/
2179 * Export information about protocols/devices supported by this driver.
2181 static struct ieee1394_device_id dv1394_id_table[] = {
2183 .match_flags = IEEE1394_MATCH_SPECIFIER_ID | IEEE1394_MATCH_VERSION,
2184 .specifier_id = AVC_UNIT_SPEC_ID_ENTRY & 0xffffff,
2185 .version = AVC_SW_VERSION_ENTRY & 0xffffff
2190 MODULE_DEVICE_TABLE(ieee1394, dv1394_id_table);
2192 static struct hpsb_protocol_driver dv1394_driver = {
2193 .name = "DV/1394 Driver",
2194 .id_table = dv1394_id_table,
2197 .bus = &ieee1394_bus_type,
2202 /*** IEEE1394 HPSB CALLBACKS ***********************************************/
2204 static int dv1394_init(struct ti_ohci *ohci, enum pal_or_ntsc format, enum modes mode)
2206 struct video_card *video;
2207 unsigned long flags;
2210 video = kmalloc(sizeof(struct video_card), GFP_KERNEL);
2212 printk(KERN_ERR "dv1394: cannot allocate video_card\n");
2216 memset(video, 0, sizeof(struct video_card));
2219 /* lower 2 bits of id indicate which of four "plugs"
2221 video->id = ohci->host->id << 2;
2222 if (format == DV1394_NTSC)
2225 video->id |= 2 + mode;
2227 video->ohci_it_ctx = -1;
2228 video->ohci_ir_ctx = -1;
2230 video->ohci_IsoXmitContextControlSet = 0;
2231 video->ohci_IsoXmitContextControlClear = 0;
2232 video->ohci_IsoXmitCommandPtr = 0;
2234 video->ohci_IsoRcvContextControlSet = 0;
2235 video->ohci_IsoRcvContextControlClear = 0;
2236 video->ohci_IsoRcvCommandPtr = 0;
2237 video->ohci_IsoRcvContextMatch = 0;
2239 video->n_frames = 0; /* flag that video is not initialized */
2240 video->channel = 63; /* default to broadcast channel */
2241 video->active_frame = -1;
2243 /* initialize the following */
2244 video->pal_or_ntsc = format;
2245 video->cip_n = 0; /* 0 = use builtin default */
2247 video->syt_offset = 0;
2250 for (i = 0; i < DV1394_MAX_FRAMES; i++)
2251 video->frames[i] = NULL;
2253 dma_region_init(&video->dv_buf);
2254 video->dv_buf_size = 0;
2255 dma_region_init(&video->packet_buf);
2256 video->packet_buf_size = 0;
2258 clear_bit(0, &video->open);
2259 spin_lock_init(&video->spinlock);
2260 video->dma_running = 0;
2261 init_MUTEX(&video->sem);
2262 init_waitqueue_head(&video->waitq);
2263 video->fasync = NULL;
2265 spin_lock_irqsave(&dv1394_cards_lock, flags);
2266 INIT_LIST_HEAD(&video->list);
2267 list_add_tail(&video->list, &dv1394_cards);
2268 spin_unlock_irqrestore(&dv1394_cards_lock, flags);
2270 if (devfs_mk_cdev(MKDEV(IEEE1394_MAJOR,
2271 IEEE1394_MINOR_BLOCK_DV1394*16 + video->id),
2272 S_IFCHR|S_IRUGO|S_IWUGO,
2273 "ieee1394/dv/host%d/%s/%s",
2275 (video->pal_or_ntsc == DV1394_NTSC ? "NTSC" : "PAL"),
2276 (video->mode == MODE_RECEIVE ? "in" : "out")) < 0)
2279 debug_printk("dv1394: dv1394_init() OK on ID %d\n", video->id);
2289 static void dv1394_un_init(struct video_card *video)
2293 /* obviously nobody has the driver open at this point */
2294 do_dv1394_shutdown(video, 1);
2295 snprintf(buf, sizeof(buf), "dv/host%d/%s/%s", (video->id >> 2),
2296 (video->pal_or_ntsc == DV1394_NTSC ? "NTSC" : "PAL"),
2297 (video->mode == MODE_RECEIVE ? "in" : "out")
2300 devfs_remove("ieee1394/%s", buf);
2305 static void dv1394_remove_host (struct hpsb_host *host)
2307 struct video_card *video;
2308 unsigned long flags;
2311 /* We only work with the OHCI-1394 driver */
2312 if (strcmp(host->driver->name, OHCI1394_DRIVER_NAME))
2315 /* find the corresponding video_cards */
2317 struct video_card *tmp_vid;
2321 spin_lock_irqsave(&dv1394_cards_lock, flags);
2322 list_for_each_entry(tmp_vid, &dv1394_cards, list) {
2323 if ((tmp_vid->id >> 2) == id) {
2324 list_del(&tmp_vid->list);
2329 spin_unlock_irqrestore(&dv1394_cards_lock, flags);
2332 dv1394_un_init(video);
2333 } while (video != NULL);
2335 devfs_remove("ieee1394/dv/host%d/NTSC", id);
2336 devfs_remove("ieee1394/dv/host%d/PAL", id);
2337 devfs_remove("ieee1394/dv/host%d", id);
2340 static void dv1394_add_host (struct hpsb_host *host)
2342 struct ti_ohci *ohci;
2345 /* We only work with the OHCI-1394 driver */
2346 if (strcmp(host->driver->name, OHCI1394_DRIVER_NAME))
2349 ohci = (struct ti_ohci *)host->hostdata;
2351 devfs_mk_dir("ieee1394/dv/host%d", id);
2352 devfs_mk_dir("ieee1394/dv/host%d/NTSC", id);
2353 devfs_mk_dir("ieee1394/dv/host%d/PAL", id);
2355 dv1394_init(ohci, DV1394_NTSC, MODE_RECEIVE);
2356 dv1394_init(ohci, DV1394_NTSC, MODE_TRANSMIT);
2357 dv1394_init(ohci, DV1394_PAL, MODE_RECEIVE);
2358 dv1394_init(ohci, DV1394_PAL, MODE_TRANSMIT);
2362 /* Bus reset handler. In the event of a bus reset, we may need to
2363 re-start the DMA contexts - otherwise the user program would
2364 end up waiting forever.
2367 static void dv1394_host_reset(struct hpsb_host *host)
2369 struct ti_ohci *ohci;
2370 struct video_card *video = NULL, *tmp_vid;
2371 unsigned long flags;
2373 /* We only work with the OHCI-1394 driver */
2374 if (strcmp(host->driver->name, OHCI1394_DRIVER_NAME))
2377 ohci = (struct ti_ohci *)host->hostdata;
2380 /* find the corresponding video_cards */
2381 spin_lock_irqsave(&dv1394_cards_lock, flags);
2382 list_for_each_entry(tmp_vid, &dv1394_cards, list) {
2383 if ((tmp_vid->id >> 2) == host->id) {
2388 spin_unlock_irqrestore(&dv1394_cards_lock, flags);
2394 spin_lock_irqsave(&video->spinlock, flags);
2396 if (!video->dma_running)
2399 /* check IT context */
2400 if (video->ohci_it_ctx != -1) {
2403 ctx = reg_read(video->ohci, video->ohci_IsoXmitContextControlSet);
2405 /* if (RUN but not ACTIVE) */
2406 if ( (ctx & (1<<15)) &&
2407 !(ctx & (1<<10)) ) {
2409 debug_printk("dv1394: IT context stopped due to bus reset; waking it up\n");
2411 /* to be safe, assume a frame has been dropped. User-space programs
2412 should handle this condition like an underflow. */
2413 video->dropped_frames++;
2415 /* for some reason you must clear, then re-set the RUN bit to restart DMA */
2418 reg_write(video->ohci, video->ohci_IsoXmitContextControlClear, (1 << 15));
2419 flush_pci_write(video->ohci);
2422 reg_write(video->ohci, video->ohci_IsoXmitContextControlSet, (1 << 15));
2423 flush_pci_write(video->ohci);
2425 /* set the WAKE bit (just in case; this isn't strictly necessary) */
2426 reg_write(video->ohci, video->ohci_IsoXmitContextControlSet, (1 << 12));
2427 flush_pci_write(video->ohci);
2429 irq_printk("dv1394: AFTER IT restart ctx 0x%08x ptr 0x%08x\n",
2430 reg_read(video->ohci, video->ohci_IsoXmitContextControlSet),
2431 reg_read(video->ohci, video->ohci_IsoXmitCommandPtr));
2435 /* check IR context */
2436 if (video->ohci_ir_ctx != -1) {
2439 ctx = reg_read(video->ohci, video->ohci_IsoRcvContextControlSet);
2441 /* if (RUN but not ACTIVE) */
2442 if ( (ctx & (1<<15)) &&
2443 !(ctx & (1<<10)) ) {
2445 debug_printk("dv1394: IR context stopped due to bus reset; waking it up\n");
2447 /* to be safe, assume a frame has been dropped. User-space programs
2448 should handle this condition like an overflow. */
2449 video->dropped_frames++;
2451 /* for some reason you must clear, then re-set the RUN bit to restart DMA */
2452 /* XXX this doesn't work for me, I can't get IR DMA to restart :[ */
2455 reg_write(video->ohci, video->ohci_IsoRcvContextControlClear, (1 << 15));
2456 flush_pci_write(video->ohci);
2459 reg_write(video->ohci, video->ohci_IsoRcvContextControlSet, (1 << 15));
2460 flush_pci_write(video->ohci);
2462 /* set the WAKE bit (just in case; this isn't strictly necessary) */
2463 reg_write(video->ohci, video->ohci_IsoRcvContextControlSet, (1 << 12));
2464 flush_pci_write(video->ohci);
2466 irq_printk("dv1394: AFTER IR restart ctx 0x%08x ptr 0x%08x\n",
2467 reg_read(video->ohci, video->ohci_IsoRcvContextControlSet),
2468 reg_read(video->ohci, video->ohci_IsoRcvCommandPtr));
2473 spin_unlock_irqrestore(&video->spinlock, flags);
2475 /* wake readers/writers/ioctl'ers */
2476 wake_up_interruptible(&video->waitq);
2479 static struct hpsb_highlevel dv1394_highlevel = {
2481 .add_host = dv1394_add_host,
2482 .remove_host = dv1394_remove_host,
2483 .host_reset = dv1394_host_reset,
2486 #ifdef CONFIG_COMPAT
2488 #define DV1394_IOC32_INIT _IOW('#', 0x06, struct dv1394_init32)
2489 #define DV1394_IOC32_GET_STATUS _IOR('#', 0x0c, struct dv1394_status32)
2491 struct dv1394_init32 {
2501 struct dv1394_status32 {
2502 struct dv1394_init32 init;
2504 u32 first_clear_frame;
2509 static int handle_dv1394_init(unsigned int fd, unsigned int cmd, unsigned long arg,
2512 struct dv1394_init32 dv32;
2513 struct dv1394_init dv;
2514 mm_segment_t old_fs;
2517 if (file->f_op->ioctl != dv1394_ioctl)
2520 if (copy_from_user(&dv32, (void *)arg, sizeof(dv32)))
2523 dv.api_version = dv32.api_version;
2524 dv.channel = dv32.channel;
2525 dv.n_frames = dv32.n_frames;
2526 dv.format = dv32.format;
2527 dv.cip_n = (unsigned long)dv32.cip_n;
2528 dv.cip_d = (unsigned long)dv32.cip_d;
2529 dv.syt_offset = dv32.syt_offset;
2533 ret = dv1394_ioctl(file->f_dentry->d_inode, file,
2534 DV1394_IOC_INIT, (unsigned long)&dv);
2540 static int handle_dv1394_get_status(unsigned int fd, unsigned int cmd, unsigned long arg,
2543 struct dv1394_status32 dv32;
2544 struct dv1394_status dv;
2545 mm_segment_t old_fs;
2548 if (file->f_op->ioctl != dv1394_ioctl)
2553 ret = dv1394_ioctl(file->f_dentry->d_inode, file,
2554 DV1394_IOC_GET_STATUS, (unsigned long)&dv);
2558 dv32.init.api_version = dv.init.api_version;
2559 dv32.init.channel = dv.init.channel;
2560 dv32.init.n_frames = dv.init.n_frames;
2561 dv32.init.format = dv.init.format;
2562 dv32.init.cip_n = (u32)dv.init.cip_n;
2563 dv32.init.cip_d = (u32)dv.init.cip_d;
2564 dv32.init.syt_offset = dv.init.syt_offset;
2565 dv32.active_frame = dv.active_frame;
2566 dv32.first_clear_frame = dv.first_clear_frame;
2567 dv32.n_clear_frames = dv.n_clear_frames;
2568 dv32.dropped_frames = dv.dropped_frames;
2570 if (copy_to_user((struct dv1394_status32 *)arg, &dv32, sizeof(dv32)))
2576 #endif /* CONFIG_COMPAT */
2579 /*** KERNEL MODULE HANDLERS ************************************************/
2581 MODULE_AUTHOR("Dan Maas <dmaas@dcine.com>, Dan Dennedy <dan@dennedy.org>");
2582 MODULE_DESCRIPTION("driver for DV input/output on OHCI board");
2583 MODULE_SUPPORTED_DEVICE("dv1394");
2584 MODULE_LICENSE("GPL");
2586 static void __exit dv1394_exit_module(void)
2588 #ifdef CONFIG_COMPAT
2591 ret = unregister_ioctl32_conversion(DV1394_IOC_SHUTDOWN);
2592 ret |= unregister_ioctl32_conversion(DV1394_IOC_SUBMIT_FRAMES);
2593 ret |= unregister_ioctl32_conversion(DV1394_IOC_WAIT_FRAMES);
2594 ret |= unregister_ioctl32_conversion(DV1394_IOC_RECEIVE_FRAMES);
2595 ret |= unregister_ioctl32_conversion(DV1394_IOC_START_RECEIVE);
2596 ret |= unregister_ioctl32_conversion(DV1394_IOC32_INIT);
2597 ret |= unregister_ioctl32_conversion(DV1394_IOC32_GET_STATUS);
2599 printk(KERN_ERR "dv1394: Error unregistering ioctl32 translations\n");
2602 hpsb_unregister_protocol(&dv1394_driver);
2604 hpsb_unregister_highlevel(&dv1394_highlevel);
2605 cdev_del(&dv1394_cdev);
2606 devfs_remove("ieee1394/dv");
2609 static int __init dv1394_init_module(void)
2613 cdev_init(&dv1394_cdev, &dv1394_fops);
2614 dv1394_cdev.owner = THIS_MODULE;
2615 kobject_set_name(&dv1394_cdev.kobj, "dv1394");
2616 ret = cdev_add(&dv1394_cdev, IEEE1394_DV1394_DEV, 16);
2618 printk(KERN_ERR "dv1394: unable to register character device\n");
2622 devfs_mk_dir("ieee1394/dv");
2624 hpsb_register_highlevel(&dv1394_highlevel);
2626 ret = hpsb_register_protocol(&dv1394_driver);
2628 printk(KERN_ERR "dv1394: failed to register protocol\n");
2629 hpsb_unregister_highlevel(&dv1394_highlevel);
2630 devfs_remove("ieee1394/dv");
2631 cdev_del(&dv1394_cdev);
2635 #ifdef CONFIG_COMPAT
2637 /* First compatible ones */
2638 ret = register_ioctl32_conversion(DV1394_IOC_SHUTDOWN, NULL);
2639 ret |= register_ioctl32_conversion(DV1394_IOC_SUBMIT_FRAMES, NULL);
2640 ret |= register_ioctl32_conversion(DV1394_IOC_WAIT_FRAMES, NULL);
2641 ret |= register_ioctl32_conversion(DV1394_IOC_RECEIVE_FRAMES, NULL);
2642 ret |= register_ioctl32_conversion(DV1394_IOC_START_RECEIVE, NULL);
2644 /* These need to be handled by translation */
2645 ret |= register_ioctl32_conversion(DV1394_IOC32_INIT, handle_dv1394_init);
2646 ret |= register_ioctl32_conversion(DV1394_IOC32_GET_STATUS, handle_dv1394_get_status);
2648 printk(KERN_ERR "dv1394: Error registering ioctl32 translations\n");
2655 module_init(dv1394_init_module);
2656 module_exit(dv1394_exit_module);
2657 MODULE_ALIAS_CHARDEV(IEEE1394_MAJOR, IEEE1394_MINOR_BLOCK_DV1394 * 16);