2 * Copyright (c) 2004 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Cisco Systems. All rights reserved.
4 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
5 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 * $Id: mthca_qp.c 1355 2004-12-17 15:23:43Z roland $
38 #include <linux/init.h>
39 #include <linux/string.h>
40 #include <linux/slab.h>
44 #include <rdma/ib_verbs.h>
45 #include <rdma/ib_cache.h>
46 #include <rdma/ib_pack.h>
48 #include "mthca_dev.h"
49 #include "mthca_cmd.h"
50 #include "mthca_memfree.h"
51 #include "mthca_wqe.h"
54 MTHCA_MAX_DIRECT_QP_SIZE = 4 * PAGE_SIZE,
55 MTHCA_ACK_REQ_FREQ = 10,
56 MTHCA_FLIGHT_LIMIT = 9,
57 MTHCA_UD_HEADER_SIZE = 72, /* largest UD header possible */
58 MTHCA_INLINE_HEADER_SIZE = 4, /* data segment overhead for inline */
59 MTHCA_INLINE_CHUNK_SIZE = 16 /* inline data segment chunk */
63 MTHCA_QP_STATE_RST = 0,
64 MTHCA_QP_STATE_INIT = 1,
65 MTHCA_QP_STATE_RTR = 2,
66 MTHCA_QP_STATE_RTS = 3,
67 MTHCA_QP_STATE_SQE = 4,
68 MTHCA_QP_STATE_SQD = 5,
69 MTHCA_QP_STATE_ERR = 6,
70 MTHCA_QP_STATE_DRAINING = 7
82 MTHCA_QP_PM_MIGRATED = 0x3,
83 MTHCA_QP_PM_ARMED = 0x0,
84 MTHCA_QP_PM_REARM = 0x1
88 /* qp_context flags */
89 MTHCA_QP_BIT_DE = 1 << 8,
91 MTHCA_QP_BIT_SRE = 1 << 15,
92 MTHCA_QP_BIT_SWE = 1 << 14,
93 MTHCA_QP_BIT_SAE = 1 << 13,
94 MTHCA_QP_BIT_SIC = 1 << 4,
95 MTHCA_QP_BIT_SSC = 1 << 3,
97 MTHCA_QP_BIT_RRE = 1 << 15,
98 MTHCA_QP_BIT_RWE = 1 << 14,
99 MTHCA_QP_BIT_RAE = 1 << 13,
100 MTHCA_QP_BIT_RIC = 1 << 4,
101 MTHCA_QP_BIT_RSC = 1 << 3
105 MTHCA_SEND_DOORBELL_FENCE = 1 << 5
108 struct mthca_qp_path {
117 __be32 sl_tclass_flowlabel;
119 } __attribute__((packed));
121 struct mthca_qp_context {
123 __be32 tavor_sched_queue; /* Reserved on Arbel */
125 u8 rq_size_stride; /* Reserved on Tavor */
126 u8 sq_size_stride; /* Reserved on Tavor */
127 u8 rlkey_arbel_sched_queue; /* Reserved on Tavor */
132 struct mthca_qp_path pri_path;
133 struct mthca_qp_path alt_path;
140 __be32 next_send_psn;
142 __be32 snd_wqe_base_l; /* Next send WQE on Tavor */
143 __be32 snd_db_index; /* (debugging only entries) */
144 __be32 last_acked_psn;
147 __be32 rnr_nextrecvpsn;
150 __be32 rcv_wqe_base_l; /* Next recv WQE on Tavor */
151 __be32 rcv_db_index; /* (debugging only entries) */
155 __be16 rq_wqe_counter; /* reserved on Tavor */
156 __be16 sq_wqe_counter; /* reserved on Tavor */
158 } __attribute__((packed));
160 struct mthca_qp_param {
161 __be32 opt_param_mask;
163 struct mthca_qp_context context;
165 } __attribute__((packed));
168 MTHCA_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0,
169 MTHCA_QP_OPTPAR_RRE = 1 << 1,
170 MTHCA_QP_OPTPAR_RAE = 1 << 2,
171 MTHCA_QP_OPTPAR_RWE = 1 << 3,
172 MTHCA_QP_OPTPAR_PKEY_INDEX = 1 << 4,
173 MTHCA_QP_OPTPAR_Q_KEY = 1 << 5,
174 MTHCA_QP_OPTPAR_RNR_TIMEOUT = 1 << 6,
175 MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
176 MTHCA_QP_OPTPAR_SRA_MAX = 1 << 8,
177 MTHCA_QP_OPTPAR_RRA_MAX = 1 << 9,
178 MTHCA_QP_OPTPAR_PM_STATE = 1 << 10,
179 MTHCA_QP_OPTPAR_PORT_NUM = 1 << 11,
180 MTHCA_QP_OPTPAR_RETRY_COUNT = 1 << 12,
181 MTHCA_QP_OPTPAR_ALT_RNR_RETRY = 1 << 13,
182 MTHCA_QP_OPTPAR_ACK_TIMEOUT = 1 << 14,
183 MTHCA_QP_OPTPAR_RNR_RETRY = 1 << 15,
184 MTHCA_QP_OPTPAR_SCHED_QUEUE = 1 << 16
187 static const u8 mthca_opcode[] = {
188 [IB_WR_SEND] = MTHCA_OPCODE_SEND,
189 [IB_WR_SEND_WITH_IMM] = MTHCA_OPCODE_SEND_IMM,
190 [IB_WR_RDMA_WRITE] = MTHCA_OPCODE_RDMA_WRITE,
191 [IB_WR_RDMA_WRITE_WITH_IMM] = MTHCA_OPCODE_RDMA_WRITE_IMM,
192 [IB_WR_RDMA_READ] = MTHCA_OPCODE_RDMA_READ,
193 [IB_WR_ATOMIC_CMP_AND_SWP] = MTHCA_OPCODE_ATOMIC_CS,
194 [IB_WR_ATOMIC_FETCH_AND_ADD] = MTHCA_OPCODE_ATOMIC_FA,
197 static int is_sqp(struct mthca_dev *dev, struct mthca_qp *qp)
199 return qp->qpn >= dev->qp_table.sqp_start &&
200 qp->qpn <= dev->qp_table.sqp_start + 3;
203 static int is_qp0(struct mthca_dev *dev, struct mthca_qp *qp)
205 return qp->qpn >= dev->qp_table.sqp_start &&
206 qp->qpn <= dev->qp_table.sqp_start + 1;
209 static void *get_recv_wqe(struct mthca_qp *qp, int n)
212 return qp->queue.direct.buf + (n << qp->rq.wqe_shift);
214 return qp->queue.page_list[(n << qp->rq.wqe_shift) >> PAGE_SHIFT].buf +
215 ((n << qp->rq.wqe_shift) & (PAGE_SIZE - 1));
218 static void *get_send_wqe(struct mthca_qp *qp, int n)
221 return qp->queue.direct.buf + qp->send_wqe_offset +
222 (n << qp->sq.wqe_shift);
224 return qp->queue.page_list[(qp->send_wqe_offset +
225 (n << qp->sq.wqe_shift)) >>
227 ((qp->send_wqe_offset + (n << qp->sq.wqe_shift)) &
231 static void mthca_wq_reset(struct mthca_wq *wq)
234 wq->last_comp = wq->max - 1;
239 void mthca_qp_event(struct mthca_dev *dev, u32 qpn,
240 enum ib_event_type event_type)
243 struct ib_event event;
245 spin_lock(&dev->qp_table.lock);
246 qp = mthca_array_get(&dev->qp_table.qp, qpn & (dev->limits.num_qps - 1));
249 spin_unlock(&dev->qp_table.lock);
252 mthca_warn(dev, "Async event for bogus QP %08x\n", qpn);
256 if (event_type == IB_EVENT_PATH_MIG)
257 qp->port = qp->alt_port;
259 event.device = &dev->ib_dev;
260 event.event = event_type;
261 event.element.qp = &qp->ibqp;
262 if (qp->ibqp.event_handler)
263 qp->ibqp.event_handler(&event, qp->ibqp.qp_context);
265 spin_lock(&dev->qp_table.lock);
268 spin_unlock(&dev->qp_table.lock);
271 static int to_mthca_state(enum ib_qp_state ib_state)
274 case IB_QPS_RESET: return MTHCA_QP_STATE_RST;
275 case IB_QPS_INIT: return MTHCA_QP_STATE_INIT;
276 case IB_QPS_RTR: return MTHCA_QP_STATE_RTR;
277 case IB_QPS_RTS: return MTHCA_QP_STATE_RTS;
278 case IB_QPS_SQD: return MTHCA_QP_STATE_SQD;
279 case IB_QPS_SQE: return MTHCA_QP_STATE_SQE;
280 case IB_QPS_ERR: return MTHCA_QP_STATE_ERR;
285 enum { RC, UC, UD, RD, RDEE, MLX, NUM_TRANS };
287 static int to_mthca_st(int transport)
290 case RC: return MTHCA_QP_ST_RC;
291 case UC: return MTHCA_QP_ST_UC;
292 case UD: return MTHCA_QP_ST_UD;
293 case RD: return MTHCA_QP_ST_RD;
294 case MLX: return MTHCA_QP_ST_MLX;
299 static void store_attrs(struct mthca_sqp *sqp, struct ib_qp_attr *attr,
302 if (attr_mask & IB_QP_PKEY_INDEX)
303 sqp->pkey_index = attr->pkey_index;
304 if (attr_mask & IB_QP_QKEY)
305 sqp->qkey = attr->qkey;
306 if (attr_mask & IB_QP_SQ_PSN)
307 sqp->send_psn = attr->sq_psn;
310 static void init_port(struct mthca_dev *dev, int port)
314 struct mthca_init_ib_param param;
316 memset(¶m, 0, sizeof param);
318 param.port_width = dev->limits.port_width_cap;
319 param.vl_cap = dev->limits.vl_cap;
320 param.mtu_cap = dev->limits.mtu_cap;
321 param.gid_cap = dev->limits.gid_table_len;
322 param.pkey_cap = dev->limits.pkey_table_len;
324 err = mthca_INIT_IB(dev, ¶m, port, &status);
326 mthca_warn(dev, "INIT_IB failed, return code %d.\n", err);
328 mthca_warn(dev, "INIT_IB returned status %02x.\n", status);
331 static __be32 get_hw_access_flags(struct mthca_qp *qp, struct ib_qp_attr *attr,
336 u32 hw_access_flags = 0;
338 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
339 dest_rd_atomic = attr->max_dest_rd_atomic;
341 dest_rd_atomic = qp->resp_depth;
343 if (attr_mask & IB_QP_ACCESS_FLAGS)
344 access_flags = attr->qp_access_flags;
346 access_flags = qp->atomic_rd_en;
349 access_flags &= IB_ACCESS_REMOTE_WRITE;
351 if (access_flags & IB_ACCESS_REMOTE_READ)
352 hw_access_flags |= MTHCA_QP_BIT_RRE;
353 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
354 hw_access_flags |= MTHCA_QP_BIT_RAE;
355 if (access_flags & IB_ACCESS_REMOTE_WRITE)
356 hw_access_flags |= MTHCA_QP_BIT_RWE;
358 return cpu_to_be32(hw_access_flags);
361 static inline enum ib_qp_state to_ib_qp_state(int mthca_state)
363 switch (mthca_state) {
364 case MTHCA_QP_STATE_RST: return IB_QPS_RESET;
365 case MTHCA_QP_STATE_INIT: return IB_QPS_INIT;
366 case MTHCA_QP_STATE_RTR: return IB_QPS_RTR;
367 case MTHCA_QP_STATE_RTS: return IB_QPS_RTS;
368 case MTHCA_QP_STATE_DRAINING:
369 case MTHCA_QP_STATE_SQD: return IB_QPS_SQD;
370 case MTHCA_QP_STATE_SQE: return IB_QPS_SQE;
371 case MTHCA_QP_STATE_ERR: return IB_QPS_ERR;
376 static inline enum ib_mig_state to_ib_mig_state(int mthca_mig_state)
378 switch (mthca_mig_state) {
379 case 0: return IB_MIG_ARMED;
380 case 1: return IB_MIG_REARM;
381 case 3: return IB_MIG_MIGRATED;
386 static int to_ib_qp_access_flags(int mthca_flags)
390 if (mthca_flags & MTHCA_QP_BIT_RRE)
391 ib_flags |= IB_ACCESS_REMOTE_READ;
392 if (mthca_flags & MTHCA_QP_BIT_RWE)
393 ib_flags |= IB_ACCESS_REMOTE_WRITE;
394 if (mthca_flags & MTHCA_QP_BIT_RAE)
395 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
400 static void to_ib_ah_attr(struct mthca_dev *dev, struct ib_ah_attr *ib_ah_attr,
401 struct mthca_qp_path *path)
403 memset(ib_ah_attr, 0, sizeof *path);
404 ib_ah_attr->port_num = (be32_to_cpu(path->port_pkey) >> 24) & 0x3;
406 if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->limits.num_ports)
409 ib_ah_attr->dlid = be16_to_cpu(path->rlid);
410 ib_ah_attr->sl = be32_to_cpu(path->sl_tclass_flowlabel) >> 28;
411 ib_ah_attr->src_path_bits = path->g_mylmc & 0x7f;
412 ib_ah_attr->static_rate = mthca_rate_to_ib(dev,
413 path->static_rate & 0x7,
414 ib_ah_attr->port_num);
415 ib_ah_attr->ah_flags = (path->g_mylmc & (1 << 7)) ? IB_AH_GRH : 0;
416 if (ib_ah_attr->ah_flags) {
417 ib_ah_attr->grh.sgid_index = path->mgid_index & (dev->limits.gid_table_len - 1);
418 ib_ah_attr->grh.hop_limit = path->hop_limit;
419 ib_ah_attr->grh.traffic_class =
420 (be32_to_cpu(path->sl_tclass_flowlabel) >> 20) & 0xff;
421 ib_ah_attr->grh.flow_label =
422 be32_to_cpu(path->sl_tclass_flowlabel) & 0xfffff;
423 memcpy(ib_ah_attr->grh.dgid.raw,
424 path->rgid, sizeof ib_ah_attr->grh.dgid.raw);
428 int mthca_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
429 struct ib_qp_init_attr *qp_init_attr)
431 struct mthca_dev *dev = to_mdev(ibqp->device);
432 struct mthca_qp *qp = to_mqp(ibqp);
434 struct mthca_mailbox *mailbox;
435 struct mthca_qp_param *qp_param;
436 struct mthca_qp_context *context;
440 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
442 return PTR_ERR(mailbox);
444 err = mthca_QUERY_QP(dev, qp->qpn, 0, mailbox, &status);
448 mthca_warn(dev, "QUERY_QP returned status %02x\n", status);
453 qp_param = mailbox->buf;
454 context = &qp_param->context;
455 mthca_state = be32_to_cpu(context->flags) >> 28;
457 qp_attr->qp_state = to_ib_qp_state(mthca_state);
458 qp_attr->cur_qp_state = qp_attr->qp_state;
459 qp_attr->path_mtu = context->mtu_msgmax >> 5;
460 qp_attr->path_mig_state =
461 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
462 qp_attr->qkey = be32_to_cpu(context->qkey);
463 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
464 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff;
465 qp_attr->dest_qp_num = be32_to_cpu(context->remote_qpn) & 0xffffff;
466 qp_attr->qp_access_flags =
467 to_ib_qp_access_flags(be32_to_cpu(context->params2));
468 qp_attr->cap.max_send_wr = qp->sq.max;
469 qp_attr->cap.max_recv_wr = qp->rq.max;
470 qp_attr->cap.max_send_sge = qp->sq.max_gs;
471 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
472 qp_attr->cap.max_inline_data = qp->max_inline_data;
474 if (qp->transport == RC || qp->transport == UC) {
475 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
476 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
479 qp_attr->pkey_index = be32_to_cpu(context->pri_path.port_pkey) & 0x7f;
480 qp_attr->alt_pkey_index = be32_to_cpu(context->alt_path.port_pkey) & 0x7f;
482 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
483 qp_attr->sq_draining = mthca_state == MTHCA_QP_STATE_DRAINING;
485 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
487 qp_attr->max_dest_rd_atomic =
488 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
489 qp_attr->min_rnr_timer =
490 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
491 qp_attr->port_num = qp_attr->ah_attr.port_num;
492 qp_attr->timeout = context->pri_path.ackto >> 3;
493 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7;
494 qp_attr->rnr_retry = context->pri_path.rnr_retry >> 5;
495 qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num;
496 qp_attr->alt_timeout = context->alt_path.ackto >> 3;
497 qp_init_attr->cap = qp_attr->cap;
500 mthca_free_mailbox(dev, mailbox);
504 static int mthca_path_set(struct mthca_dev *dev, struct ib_ah_attr *ah,
505 struct mthca_qp_path *path, u8 port)
507 path->g_mylmc = ah->src_path_bits & 0x7f;
508 path->rlid = cpu_to_be16(ah->dlid);
509 path->static_rate = mthca_get_rate(dev, ah->static_rate, port);
511 if (ah->ah_flags & IB_AH_GRH) {
512 if (ah->grh.sgid_index >= dev->limits.gid_table_len) {
513 mthca_dbg(dev, "sgid_index (%u) too large. max is %d\n",
514 ah->grh.sgid_index, dev->limits.gid_table_len-1);
518 path->g_mylmc |= 1 << 7;
519 path->mgid_index = ah->grh.sgid_index;
520 path->hop_limit = ah->grh.hop_limit;
521 path->sl_tclass_flowlabel =
522 cpu_to_be32((ah->sl << 28) |
523 (ah->grh.traffic_class << 20) |
524 (ah->grh.flow_label));
525 memcpy(path->rgid, ah->grh.dgid.raw, 16);
527 path->sl_tclass_flowlabel = cpu_to_be32(ah->sl << 28);
532 int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask)
534 struct mthca_dev *dev = to_mdev(ibqp->device);
535 struct mthca_qp *qp = to_mqp(ibqp);
536 enum ib_qp_state cur_state, new_state;
537 struct mthca_mailbox *mailbox;
538 struct mthca_qp_param *qp_param;
539 struct mthca_qp_context *qp_context;
544 mutex_lock(&qp->mutex);
546 if (attr_mask & IB_QP_CUR_STATE) {
547 cur_state = attr->cur_qp_state;
549 spin_lock_irq(&qp->sq.lock);
550 spin_lock(&qp->rq.lock);
551 cur_state = qp->state;
552 spin_unlock(&qp->rq.lock);
553 spin_unlock_irq(&qp->sq.lock);
556 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
558 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask)) {
559 mthca_dbg(dev, "Bad QP transition (transport %d) "
560 "%d->%d with attr 0x%08x\n",
561 qp->transport, cur_state, new_state,
566 if ((attr_mask & IB_QP_PKEY_INDEX) &&
567 attr->pkey_index >= dev->limits.pkey_table_len) {
568 mthca_dbg(dev, "P_Key index (%u) too large. max is %d\n",
569 attr->pkey_index, dev->limits.pkey_table_len-1);
573 if ((attr_mask & IB_QP_PORT) &&
574 (attr->port_num == 0 || attr->port_num > dev->limits.num_ports)) {
575 mthca_dbg(dev, "Port number (%u) is invalid\n", attr->port_num);
579 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
580 attr->max_rd_atomic > dev->limits.max_qp_init_rdma) {
581 mthca_dbg(dev, "Max rdma_atomic as initiator %u too large (max is %d)\n",
582 attr->max_rd_atomic, dev->limits.max_qp_init_rdma);
586 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
587 attr->max_dest_rd_atomic > 1 << dev->qp_table.rdb_shift) {
588 mthca_dbg(dev, "Max rdma_atomic as responder %u too large (max %d)\n",
589 attr->max_dest_rd_atomic, 1 << dev->qp_table.rdb_shift);
593 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
594 if (IS_ERR(mailbox)) {
595 err = PTR_ERR(mailbox);
598 qp_param = mailbox->buf;
599 qp_context = &qp_param->context;
600 memset(qp_param, 0, sizeof *qp_param);
602 qp_context->flags = cpu_to_be32((to_mthca_state(new_state) << 28) |
603 (to_mthca_st(qp->transport) << 16));
604 qp_context->flags |= cpu_to_be32(MTHCA_QP_BIT_DE);
605 if (!(attr_mask & IB_QP_PATH_MIG_STATE))
606 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
608 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PM_STATE);
609 switch (attr->path_mig_state) {
610 case IB_MIG_MIGRATED:
611 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
614 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_REARM << 11);
617 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_ARMED << 11);
622 /* leave tavor_sched_queue as 0 */
624 if (qp->transport == MLX || qp->transport == UD)
625 qp_context->mtu_msgmax = (IB_MTU_2048 << 5) | 11;
626 else if (attr_mask & IB_QP_PATH_MTU) {
627 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_2048) {
628 mthca_dbg(dev, "path MTU (%u) is invalid\n",
632 qp_context->mtu_msgmax = (attr->path_mtu << 5) | 31;
635 if (mthca_is_memfree(dev)) {
637 qp_context->rq_size_stride = long_log2(qp->rq.max) << 3;
638 qp_context->rq_size_stride |= qp->rq.wqe_shift - 4;
641 qp_context->sq_size_stride = long_log2(qp->sq.max) << 3;
642 qp_context->sq_size_stride |= qp->sq.wqe_shift - 4;
645 /* leave arbel_sched_queue as 0 */
647 if (qp->ibqp.uobject)
648 qp_context->usr_page =
649 cpu_to_be32(to_mucontext(qp->ibqp.uobject->context)->uar.index);
651 qp_context->usr_page = cpu_to_be32(dev->driver_uar.index);
652 qp_context->local_qpn = cpu_to_be32(qp->qpn);
653 if (attr_mask & IB_QP_DEST_QPN) {
654 qp_context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
657 if (qp->transport == MLX)
658 qp_context->pri_path.port_pkey |=
659 cpu_to_be32(qp->port << 24);
661 if (attr_mask & IB_QP_PORT) {
662 qp_context->pri_path.port_pkey |=
663 cpu_to_be32(attr->port_num << 24);
664 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PORT_NUM);
668 if (attr_mask & IB_QP_PKEY_INDEX) {
669 qp_context->pri_path.port_pkey |=
670 cpu_to_be32(attr->pkey_index);
671 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PKEY_INDEX);
674 if (attr_mask & IB_QP_RNR_RETRY) {
675 qp_context->alt_path.rnr_retry = qp_context->pri_path.rnr_retry =
676 attr->rnr_retry << 5;
677 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_RETRY |
678 MTHCA_QP_OPTPAR_ALT_RNR_RETRY);
681 if (attr_mask & IB_QP_AV) {
682 if (mthca_path_set(dev, &attr->ah_attr, &qp_context->pri_path,
683 attr_mask & IB_QP_PORT ? attr->port_num : qp->port))
686 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH);
689 if (attr_mask & IB_QP_TIMEOUT) {
690 qp_context->pri_path.ackto = attr->timeout << 3;
691 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ACK_TIMEOUT);
694 if (attr_mask & IB_QP_ALT_PATH) {
695 if (attr->alt_pkey_index >= dev->limits.pkey_table_len) {
696 mthca_dbg(dev, "Alternate P_Key index (%u) too large. max is %d\n",
697 attr->alt_pkey_index, dev->limits.pkey_table_len-1);
701 if (attr->alt_port_num == 0 || attr->alt_port_num > dev->limits.num_ports) {
702 mthca_dbg(dev, "Alternate port number (%u) is invalid\n",
707 if (mthca_path_set(dev, &attr->alt_ah_attr, &qp_context->alt_path,
708 attr->alt_ah_attr.port_num))
711 qp_context->alt_path.port_pkey |= cpu_to_be32(attr->alt_pkey_index |
712 attr->alt_port_num << 24);
713 qp_context->alt_path.ackto = attr->alt_timeout << 3;
714 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ALT_ADDR_PATH);
718 qp_context->pd = cpu_to_be32(to_mpd(ibqp->pd)->pd_num);
719 /* leave wqe_base as 0 (we always create an MR based at 0 for WQs) */
720 qp_context->wqe_lkey = cpu_to_be32(qp->mr.ibmr.lkey);
721 qp_context->params1 = cpu_to_be32((MTHCA_ACK_REQ_FREQ << 28) |
722 (MTHCA_FLIGHT_LIMIT << 24) |
724 if (qp->sq_policy == IB_SIGNAL_ALL_WR)
725 qp_context->params1 |= cpu_to_be32(MTHCA_QP_BIT_SSC);
726 if (attr_mask & IB_QP_RETRY_CNT) {
727 qp_context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
728 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RETRY_COUNT);
731 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
732 if (attr->max_rd_atomic) {
733 qp_context->params1 |=
734 cpu_to_be32(MTHCA_QP_BIT_SRE |
736 qp_context->params1 |=
737 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
739 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_SRA_MAX);
742 if (attr_mask & IB_QP_SQ_PSN)
743 qp_context->next_send_psn = cpu_to_be32(attr->sq_psn);
744 qp_context->cqn_snd = cpu_to_be32(to_mcq(ibqp->send_cq)->cqn);
746 if (mthca_is_memfree(dev)) {
747 qp_context->snd_wqe_base_l = cpu_to_be32(qp->send_wqe_offset);
748 qp_context->snd_db_index = cpu_to_be32(qp->sq.db_index);
751 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
752 if (attr->max_dest_rd_atomic)
753 qp_context->params2 |=
754 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
756 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RRA_MAX);
759 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
760 qp_context->params2 |= get_hw_access_flags(qp, attr, attr_mask);
761 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RWE |
762 MTHCA_QP_OPTPAR_RRE |
763 MTHCA_QP_OPTPAR_RAE);
766 qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RSC);
769 qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RIC);
771 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
772 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
773 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_TIMEOUT);
775 if (attr_mask & IB_QP_RQ_PSN)
776 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
778 qp_context->ra_buff_indx =
779 cpu_to_be32(dev->qp_table.rdb_base +
780 ((qp->qpn & (dev->limits.num_qps - 1)) * MTHCA_RDB_ENTRY_SIZE <<
781 dev->qp_table.rdb_shift));
783 qp_context->cqn_rcv = cpu_to_be32(to_mcq(ibqp->recv_cq)->cqn);
785 if (mthca_is_memfree(dev))
786 qp_context->rcv_db_index = cpu_to_be32(qp->rq.db_index);
788 if (attr_mask & IB_QP_QKEY) {
789 qp_context->qkey = cpu_to_be32(attr->qkey);
790 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_Q_KEY);
794 qp_context->srqn = cpu_to_be32(1 << 24 |
795 to_msrq(ibqp->srq)->srqn);
797 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD &&
798 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY &&
799 attr->en_sqd_async_notify)
802 err = mthca_MODIFY_QP(dev, cur_state, new_state, qp->qpn, 0,
803 mailbox, sqd_event, &status);
807 mthca_warn(dev, "modify QP %d->%d returned status %02x.\n",
808 cur_state, new_state, status);
813 qp->state = new_state;
814 if (attr_mask & IB_QP_ACCESS_FLAGS)
815 qp->atomic_rd_en = attr->qp_access_flags;
816 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
817 qp->resp_depth = attr->max_dest_rd_atomic;
818 if (attr_mask & IB_QP_PORT)
819 qp->port = attr->port_num;
820 if (attr_mask & IB_QP_ALT_PATH)
821 qp->alt_port = attr->alt_port_num;
824 store_attrs(to_msqp(qp), attr, attr_mask);
827 * If we moved QP0 to RTR, bring the IB link up; if we moved
828 * QP0 to RESET or ERROR, bring the link back down.
830 if (is_qp0(dev, qp)) {
831 if (cur_state != IB_QPS_RTR &&
832 new_state == IB_QPS_RTR)
833 init_port(dev, qp->port);
835 if (cur_state != IB_QPS_RESET &&
836 cur_state != IB_QPS_ERR &&
837 (new_state == IB_QPS_RESET ||
838 new_state == IB_QPS_ERR))
839 mthca_CLOSE_IB(dev, qp->port, &status);
843 * If we moved a kernel QP to RESET, clean up all old CQ
844 * entries and reinitialize the QP.
846 if (new_state == IB_QPS_RESET && !qp->ibqp.uobject) {
847 mthca_cq_clean(dev, to_mcq(qp->ibqp.send_cq), qp->qpn,
848 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
849 if (qp->ibqp.send_cq != qp->ibqp.recv_cq)
850 mthca_cq_clean(dev, to_mcq(qp->ibqp.recv_cq), qp->qpn,
851 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
853 mthca_wq_reset(&qp->sq);
854 qp->sq.last = get_send_wqe(qp, qp->sq.max - 1);
856 mthca_wq_reset(&qp->rq);
857 qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1);
859 if (mthca_is_memfree(dev)) {
866 mthca_free_mailbox(dev, mailbox);
869 mutex_unlock(&qp->mutex);
873 static int mthca_max_data_size(struct mthca_dev *dev, struct mthca_qp *qp, int desc_sz)
876 * Calculate the maximum size of WQE s/g segments, excluding
877 * the next segment and other non-data segments.
879 int max_data_size = desc_sz - sizeof (struct mthca_next_seg);
881 switch (qp->transport) {
883 max_data_size -= 2 * sizeof (struct mthca_data_seg);
887 if (mthca_is_memfree(dev))
888 max_data_size -= sizeof (struct mthca_arbel_ud_seg);
890 max_data_size -= sizeof (struct mthca_tavor_ud_seg);
894 max_data_size -= sizeof (struct mthca_raddr_seg);
898 return max_data_size;
901 static inline int mthca_max_inline_data(struct mthca_pd *pd, int max_data_size)
903 /* We don't support inline data for kernel QPs (yet). */
904 return pd->ibpd.uobject ? max_data_size - MTHCA_INLINE_HEADER_SIZE : 0;
907 static void mthca_adjust_qp_caps(struct mthca_dev *dev,
911 int max_data_size = mthca_max_data_size(dev, qp,
912 min(dev->limits.max_desc_sz,
913 1 << qp->sq.wqe_shift));
915 qp->max_inline_data = mthca_max_inline_data(pd, max_data_size);
917 qp->sq.max_gs = min_t(int, dev->limits.max_sg,
918 max_data_size / sizeof (struct mthca_data_seg));
919 qp->rq.max_gs = min_t(int, dev->limits.max_sg,
920 (min(dev->limits.max_desc_sz, 1 << qp->rq.wqe_shift) -
921 sizeof (struct mthca_next_seg)) /
922 sizeof (struct mthca_data_seg));
926 * Allocate and register buffer for WQEs. qp->rq.max, sq.max,
927 * rq.max_gs and sq.max_gs must all be assigned.
928 * mthca_alloc_wqe_buf will calculate rq.wqe_shift and
929 * sq.wqe_shift (as well as send_wqe_offset, is_direct, and
932 static int mthca_alloc_wqe_buf(struct mthca_dev *dev,
939 size = sizeof (struct mthca_next_seg) +
940 qp->rq.max_gs * sizeof (struct mthca_data_seg);
942 if (size > dev->limits.max_desc_sz)
945 for (qp->rq.wqe_shift = 6; 1 << qp->rq.wqe_shift < size;
949 size = qp->sq.max_gs * sizeof (struct mthca_data_seg);
950 switch (qp->transport) {
952 size += 2 * sizeof (struct mthca_data_seg);
956 size += mthca_is_memfree(dev) ?
957 sizeof (struct mthca_arbel_ud_seg) :
958 sizeof (struct mthca_tavor_ud_seg);
962 size += sizeof (struct mthca_raddr_seg);
966 size += sizeof (struct mthca_raddr_seg);
968 * An atomic op will require an atomic segment, a
969 * remote address segment and one scatter entry.
971 size = max_t(int, size,
972 sizeof (struct mthca_atomic_seg) +
973 sizeof (struct mthca_raddr_seg) +
974 sizeof (struct mthca_data_seg));
981 /* Make sure that we have enough space for a bind request */
982 size = max_t(int, size, sizeof (struct mthca_bind_seg));
984 size += sizeof (struct mthca_next_seg);
986 if (size > dev->limits.max_desc_sz)
989 for (qp->sq.wqe_shift = 6; 1 << qp->sq.wqe_shift < size;
993 qp->send_wqe_offset = ALIGN(qp->rq.max << qp->rq.wqe_shift,
994 1 << qp->sq.wqe_shift);
997 * If this is a userspace QP, we don't actually have to
998 * allocate anything. All we need is to calculate the WQE
999 * sizes and the send_wqe_offset, so we're done now.
1001 if (pd->ibpd.uobject)
1004 size = PAGE_ALIGN(qp->send_wqe_offset +
1005 (qp->sq.max << qp->sq.wqe_shift));
1007 qp->wrid = kmalloc((qp->rq.max + qp->sq.max) * sizeof (u64),
1012 err = mthca_buf_alloc(dev, size, MTHCA_MAX_DIRECT_QP_SIZE,
1013 &qp->queue, &qp->is_direct, pd, 0, &qp->mr);
1024 static void mthca_free_wqe_buf(struct mthca_dev *dev,
1025 struct mthca_qp *qp)
1027 mthca_buf_free(dev, PAGE_ALIGN(qp->send_wqe_offset +
1028 (qp->sq.max << qp->sq.wqe_shift)),
1029 &qp->queue, qp->is_direct, &qp->mr);
1033 static int mthca_map_memfree(struct mthca_dev *dev,
1034 struct mthca_qp *qp)
1038 if (mthca_is_memfree(dev)) {
1039 ret = mthca_table_get(dev, dev->qp_table.qp_table, qp->qpn);
1043 ret = mthca_table_get(dev, dev->qp_table.eqp_table, qp->qpn);
1047 ret = mthca_table_get(dev, dev->qp_table.rdb_table,
1048 qp->qpn << dev->qp_table.rdb_shift);
1057 mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1060 mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1065 static void mthca_unmap_memfree(struct mthca_dev *dev,
1066 struct mthca_qp *qp)
1068 mthca_table_put(dev, dev->qp_table.rdb_table,
1069 qp->qpn << dev->qp_table.rdb_shift);
1070 mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1071 mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1074 static int mthca_alloc_memfree(struct mthca_dev *dev,
1075 struct mthca_qp *qp)
1079 if (mthca_is_memfree(dev)) {
1080 qp->rq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_RQ,
1081 qp->qpn, &qp->rq.db);
1082 if (qp->rq.db_index < 0)
1085 qp->sq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_SQ,
1086 qp->qpn, &qp->sq.db);
1087 if (qp->sq.db_index < 0)
1088 mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1094 static void mthca_free_memfree(struct mthca_dev *dev,
1095 struct mthca_qp *qp)
1097 if (mthca_is_memfree(dev)) {
1098 mthca_free_db(dev, MTHCA_DB_TYPE_SQ, qp->sq.db_index);
1099 mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1103 static int mthca_alloc_qp_common(struct mthca_dev *dev,
1104 struct mthca_pd *pd,
1105 struct mthca_cq *send_cq,
1106 struct mthca_cq *recv_cq,
1107 enum ib_sig_type send_policy,
1108 struct mthca_qp *qp)
1114 init_waitqueue_head(&qp->wait);
1115 mutex_init(&qp->mutex);
1116 qp->state = IB_QPS_RESET;
1117 qp->atomic_rd_en = 0;
1119 qp->sq_policy = send_policy;
1120 mthca_wq_reset(&qp->sq);
1121 mthca_wq_reset(&qp->rq);
1123 spin_lock_init(&qp->sq.lock);
1124 spin_lock_init(&qp->rq.lock);
1126 ret = mthca_map_memfree(dev, qp);
1130 ret = mthca_alloc_wqe_buf(dev, pd, qp);
1132 mthca_unmap_memfree(dev, qp);
1136 mthca_adjust_qp_caps(dev, pd, qp);
1139 * If this is a userspace QP, we're done now. The doorbells
1140 * will be allocated and buffers will be initialized in
1143 if (pd->ibpd.uobject)
1146 ret = mthca_alloc_memfree(dev, qp);
1148 mthca_free_wqe_buf(dev, qp);
1149 mthca_unmap_memfree(dev, qp);
1153 if (mthca_is_memfree(dev)) {
1154 struct mthca_next_seg *next;
1155 struct mthca_data_seg *scatter;
1156 int size = (sizeof (struct mthca_next_seg) +
1157 qp->rq.max_gs * sizeof (struct mthca_data_seg)) / 16;
1159 for (i = 0; i < qp->rq.max; ++i) {
1160 next = get_recv_wqe(qp, i);
1161 next->nda_op = cpu_to_be32(((i + 1) & (qp->rq.max - 1)) <<
1163 next->ee_nds = cpu_to_be32(size);
1165 for (scatter = (void *) (next + 1);
1166 (void *) scatter < (void *) next + (1 << qp->rq.wqe_shift);
1168 scatter->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
1171 for (i = 0; i < qp->sq.max; ++i) {
1172 next = get_send_wqe(qp, i);
1173 next->nda_op = cpu_to_be32((((i + 1) & (qp->sq.max - 1)) <<
1175 qp->send_wqe_offset);
1179 qp->sq.last = get_send_wqe(qp, qp->sq.max - 1);
1180 qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1);
1185 static int mthca_set_qp_size(struct mthca_dev *dev, struct ib_qp_cap *cap,
1186 struct mthca_pd *pd, struct mthca_qp *qp)
1188 int max_data_size = mthca_max_data_size(dev, qp, dev->limits.max_desc_sz);
1190 /* Sanity check QP size before proceeding */
1191 if (cap->max_send_wr > dev->limits.max_wqes ||
1192 cap->max_recv_wr > dev->limits.max_wqes ||
1193 cap->max_send_sge > dev->limits.max_sg ||
1194 cap->max_recv_sge > dev->limits.max_sg ||
1195 cap->max_inline_data > mthca_max_inline_data(pd, max_data_size))
1199 * For MLX transport we need 2 extra S/G entries:
1200 * one for the header and one for the checksum at the end
1202 if (qp->transport == MLX && cap->max_recv_sge + 2 > dev->limits.max_sg)
1205 if (mthca_is_memfree(dev)) {
1206 qp->rq.max = cap->max_recv_wr ?
1207 roundup_pow_of_two(cap->max_recv_wr) : 0;
1208 qp->sq.max = cap->max_send_wr ?
1209 roundup_pow_of_two(cap->max_send_wr) : 0;
1211 qp->rq.max = cap->max_recv_wr;
1212 qp->sq.max = cap->max_send_wr;
1215 qp->rq.max_gs = cap->max_recv_sge;
1216 qp->sq.max_gs = max_t(int, cap->max_send_sge,
1217 ALIGN(cap->max_inline_data + MTHCA_INLINE_HEADER_SIZE,
1218 MTHCA_INLINE_CHUNK_SIZE) /
1219 sizeof (struct mthca_data_seg));
1224 int mthca_alloc_qp(struct mthca_dev *dev,
1225 struct mthca_pd *pd,
1226 struct mthca_cq *send_cq,
1227 struct mthca_cq *recv_cq,
1228 enum ib_qp_type type,
1229 enum ib_sig_type send_policy,
1230 struct ib_qp_cap *cap,
1231 struct mthca_qp *qp)
1236 case IB_QPT_RC: qp->transport = RC; break;
1237 case IB_QPT_UC: qp->transport = UC; break;
1238 case IB_QPT_UD: qp->transport = UD; break;
1239 default: return -EINVAL;
1242 err = mthca_set_qp_size(dev, cap, pd, qp);
1246 qp->qpn = mthca_alloc(&dev->qp_table.alloc);
1250 /* initialize port to zero for error-catching. */
1253 err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1256 mthca_free(&dev->qp_table.alloc, qp->qpn);
1260 spin_lock_irq(&dev->qp_table.lock);
1261 mthca_array_set(&dev->qp_table.qp,
1262 qp->qpn & (dev->limits.num_qps - 1), qp);
1263 spin_unlock_irq(&dev->qp_table.lock);
1268 static void mthca_lock_cqs(struct mthca_cq *send_cq, struct mthca_cq *recv_cq)
1270 if (send_cq == recv_cq)
1271 spin_lock_irq(&send_cq->lock);
1272 else if (send_cq->cqn < recv_cq->cqn) {
1273 spin_lock_irq(&send_cq->lock);
1274 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
1276 spin_lock_irq(&recv_cq->lock);
1277 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
1281 static void mthca_unlock_cqs(struct mthca_cq *send_cq, struct mthca_cq *recv_cq)
1283 if (send_cq == recv_cq)
1284 spin_unlock_irq(&send_cq->lock);
1285 else if (send_cq->cqn < recv_cq->cqn) {
1286 spin_unlock(&recv_cq->lock);
1287 spin_unlock_irq(&send_cq->lock);
1289 spin_unlock(&send_cq->lock);
1290 spin_unlock_irq(&recv_cq->lock);
1294 int mthca_alloc_sqp(struct mthca_dev *dev,
1295 struct mthca_pd *pd,
1296 struct mthca_cq *send_cq,
1297 struct mthca_cq *recv_cq,
1298 enum ib_sig_type send_policy,
1299 struct ib_qp_cap *cap,
1302 struct mthca_sqp *sqp)
1304 u32 mqpn = qpn * 2 + dev->qp_table.sqp_start + port - 1;
1307 sqp->qp.transport = MLX;
1308 err = mthca_set_qp_size(dev, cap, pd, &sqp->qp);
1312 sqp->header_buf_size = sqp->qp.sq.max * MTHCA_UD_HEADER_SIZE;
1313 sqp->header_buf = dma_alloc_coherent(&dev->pdev->dev, sqp->header_buf_size,
1314 &sqp->header_dma, GFP_KERNEL);
1315 if (!sqp->header_buf)
1318 spin_lock_irq(&dev->qp_table.lock);
1319 if (mthca_array_get(&dev->qp_table.qp, mqpn))
1322 mthca_array_set(&dev->qp_table.qp, mqpn, sqp);
1323 spin_unlock_irq(&dev->qp_table.lock);
1328 sqp->qp.port = port;
1330 sqp->qp.transport = MLX;
1332 err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1333 send_policy, &sqp->qp);
1337 atomic_inc(&pd->sqp_count);
1343 * Lock CQs here, so that CQ polling code can do QP lookup
1344 * without taking a lock.
1346 mthca_lock_cqs(send_cq, recv_cq);
1348 spin_lock(&dev->qp_table.lock);
1349 mthca_array_clear(&dev->qp_table.qp, mqpn);
1350 spin_unlock(&dev->qp_table.lock);
1352 mthca_unlock_cqs(send_cq, recv_cq);
1355 dma_free_coherent(&dev->pdev->dev, sqp->header_buf_size,
1356 sqp->header_buf, sqp->header_dma);
1361 static inline int get_qp_refcount(struct mthca_dev *dev, struct mthca_qp *qp)
1365 spin_lock_irq(&dev->qp_table.lock);
1367 spin_unlock_irq(&dev->qp_table.lock);
1372 void mthca_free_qp(struct mthca_dev *dev,
1373 struct mthca_qp *qp)
1376 struct mthca_cq *send_cq;
1377 struct mthca_cq *recv_cq;
1379 send_cq = to_mcq(qp->ibqp.send_cq);
1380 recv_cq = to_mcq(qp->ibqp.recv_cq);
1383 * Lock CQs here, so that CQ polling code can do QP lookup
1384 * without taking a lock.
1386 mthca_lock_cqs(send_cq, recv_cq);
1388 spin_lock(&dev->qp_table.lock);
1389 mthca_array_clear(&dev->qp_table.qp,
1390 qp->qpn & (dev->limits.num_qps - 1));
1392 spin_unlock(&dev->qp_table.lock);
1394 mthca_unlock_cqs(send_cq, recv_cq);
1396 wait_event(qp->wait, !get_qp_refcount(dev, qp));
1398 if (qp->state != IB_QPS_RESET)
1399 mthca_MODIFY_QP(dev, qp->state, IB_QPS_RESET, qp->qpn, 0,
1403 * If this is a userspace QP, the buffers, MR, CQs and so on
1404 * will be cleaned up in userspace, so all we have to do is
1405 * unref the mem-free tables and free the QPN in our table.
1407 if (!qp->ibqp.uobject) {
1408 mthca_cq_clean(dev, to_mcq(qp->ibqp.send_cq), qp->qpn,
1409 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1410 if (qp->ibqp.send_cq != qp->ibqp.recv_cq)
1411 mthca_cq_clean(dev, to_mcq(qp->ibqp.recv_cq), qp->qpn,
1412 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1414 mthca_free_memfree(dev, qp);
1415 mthca_free_wqe_buf(dev, qp);
1418 mthca_unmap_memfree(dev, qp);
1420 if (is_sqp(dev, qp)) {
1421 atomic_dec(&(to_mpd(qp->ibqp.pd)->sqp_count));
1422 dma_free_coherent(&dev->pdev->dev,
1423 to_msqp(qp)->header_buf_size,
1424 to_msqp(qp)->header_buf,
1425 to_msqp(qp)->header_dma);
1427 mthca_free(&dev->qp_table.alloc, qp->qpn);
1430 /* Create UD header for an MLX send and build a data segment for it */
1431 static int build_mlx_header(struct mthca_dev *dev, struct mthca_sqp *sqp,
1432 int ind, struct ib_send_wr *wr,
1433 struct mthca_mlx_seg *mlx,
1434 struct mthca_data_seg *data)
1440 ib_ud_header_init(256, /* assume a MAD */
1441 mthca_ah_grh_present(to_mah(wr->wr.ud.ah)),
1444 err = mthca_read_ah(dev, to_mah(wr->wr.ud.ah), &sqp->ud_header);
1447 mlx->flags &= ~cpu_to_be32(MTHCA_NEXT_SOLICIT | 1);
1448 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MTHCA_MLX_VL15 : 0) |
1449 (sqp->ud_header.lrh.destination_lid ==
1450 IB_LID_PERMISSIVE ? MTHCA_MLX_SLR : 0) |
1451 (sqp->ud_header.lrh.service_level << 8));
1452 mlx->rlid = sqp->ud_header.lrh.destination_lid;
1455 switch (wr->opcode) {
1457 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
1458 sqp->ud_header.immediate_present = 0;
1460 case IB_WR_SEND_WITH_IMM:
1461 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1462 sqp->ud_header.immediate_present = 1;
1463 sqp->ud_header.immediate_data = wr->imm_data;
1469 sqp->ud_header.lrh.virtual_lane = !sqp->qp.ibqp.qp_num ? 15 : 0;
1470 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
1471 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
1472 sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
1473 if (!sqp->qp.ibqp.qp_num)
1474 ib_get_cached_pkey(&dev->ib_dev, sqp->qp.port,
1475 sqp->pkey_index, &pkey);
1477 ib_get_cached_pkey(&dev->ib_dev, sqp->qp.port,
1478 wr->wr.ud.pkey_index, &pkey);
1479 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
1480 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1481 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1482 sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
1483 sqp->qkey : wr->wr.ud.remote_qkey);
1484 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
1486 header_size = ib_ud_header_pack(&sqp->ud_header,
1488 ind * MTHCA_UD_HEADER_SIZE);
1490 data->byte_count = cpu_to_be32(header_size);
1491 data->lkey = cpu_to_be32(to_mpd(sqp->qp.ibqp.pd)->ntmr.ibmr.lkey);
1492 data->addr = cpu_to_be64(sqp->header_dma +
1493 ind * MTHCA_UD_HEADER_SIZE);
1498 static inline int mthca_wq_overflow(struct mthca_wq *wq, int nreq,
1499 struct ib_cq *ib_cq)
1502 struct mthca_cq *cq;
1504 cur = wq->head - wq->tail;
1505 if (likely(cur + nreq < wq->max))
1509 spin_lock(&cq->lock);
1510 cur = wq->head - wq->tail;
1511 spin_unlock(&cq->lock);
1513 return cur + nreq >= wq->max;
1516 int mthca_tavor_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1517 struct ib_send_wr **bad_wr)
1519 struct mthca_dev *dev = to_mdev(ibqp->device);
1520 struct mthca_qp *qp = to_mqp(ibqp);
1523 unsigned long flags;
1533 spin_lock_irqsave(&qp->sq.lock, flags);
1535 /* XXX check that state is OK to post send */
1537 ind = qp->sq.next_ind;
1539 for (nreq = 0; wr; ++nreq, wr = wr->next) {
1540 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1541 mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1542 " %d max, %d nreq)\n", qp->qpn,
1543 qp->sq.head, qp->sq.tail,
1550 wqe = get_send_wqe(qp, ind);
1551 prev_wqe = qp->sq.last;
1554 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1555 ((struct mthca_next_seg *) wqe)->ee_nds = 0;
1556 ((struct mthca_next_seg *) wqe)->flags =
1557 ((wr->send_flags & IB_SEND_SIGNALED) ?
1558 cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1559 ((wr->send_flags & IB_SEND_SOLICITED) ?
1560 cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0) |
1562 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1563 wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1564 ((struct mthca_next_seg *) wqe)->imm = wr->imm_data;
1566 wqe += sizeof (struct mthca_next_seg);
1567 size = sizeof (struct mthca_next_seg) / 16;
1569 switch (qp->transport) {
1571 switch (wr->opcode) {
1572 case IB_WR_ATOMIC_CMP_AND_SWP:
1573 case IB_WR_ATOMIC_FETCH_AND_ADD:
1574 ((struct mthca_raddr_seg *) wqe)->raddr =
1575 cpu_to_be64(wr->wr.atomic.remote_addr);
1576 ((struct mthca_raddr_seg *) wqe)->rkey =
1577 cpu_to_be32(wr->wr.atomic.rkey);
1578 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1580 wqe += sizeof (struct mthca_raddr_seg);
1582 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1583 ((struct mthca_atomic_seg *) wqe)->swap_add =
1584 cpu_to_be64(wr->wr.atomic.swap);
1585 ((struct mthca_atomic_seg *) wqe)->compare =
1586 cpu_to_be64(wr->wr.atomic.compare_add);
1588 ((struct mthca_atomic_seg *) wqe)->swap_add =
1589 cpu_to_be64(wr->wr.atomic.compare_add);
1590 ((struct mthca_atomic_seg *) wqe)->compare = 0;
1593 wqe += sizeof (struct mthca_atomic_seg);
1594 size += (sizeof (struct mthca_raddr_seg) +
1595 sizeof (struct mthca_atomic_seg)) / 16;
1598 case IB_WR_RDMA_WRITE:
1599 case IB_WR_RDMA_WRITE_WITH_IMM:
1600 case IB_WR_RDMA_READ:
1601 ((struct mthca_raddr_seg *) wqe)->raddr =
1602 cpu_to_be64(wr->wr.rdma.remote_addr);
1603 ((struct mthca_raddr_seg *) wqe)->rkey =
1604 cpu_to_be32(wr->wr.rdma.rkey);
1605 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1606 wqe += sizeof (struct mthca_raddr_seg);
1607 size += sizeof (struct mthca_raddr_seg) / 16;
1611 /* No extra segments required for sends */
1618 switch (wr->opcode) {
1619 case IB_WR_RDMA_WRITE:
1620 case IB_WR_RDMA_WRITE_WITH_IMM:
1621 ((struct mthca_raddr_seg *) wqe)->raddr =
1622 cpu_to_be64(wr->wr.rdma.remote_addr);
1623 ((struct mthca_raddr_seg *) wqe)->rkey =
1624 cpu_to_be32(wr->wr.rdma.rkey);
1625 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1626 wqe += sizeof (struct mthca_raddr_seg);
1627 size += sizeof (struct mthca_raddr_seg) / 16;
1631 /* No extra segments required for sends */
1638 ((struct mthca_tavor_ud_seg *) wqe)->lkey =
1639 cpu_to_be32(to_mah(wr->wr.ud.ah)->key);
1640 ((struct mthca_tavor_ud_seg *) wqe)->av_addr =
1641 cpu_to_be64(to_mah(wr->wr.ud.ah)->avdma);
1642 ((struct mthca_tavor_ud_seg *) wqe)->dqpn =
1643 cpu_to_be32(wr->wr.ud.remote_qpn);
1644 ((struct mthca_tavor_ud_seg *) wqe)->qkey =
1645 cpu_to_be32(wr->wr.ud.remote_qkey);
1647 wqe += sizeof (struct mthca_tavor_ud_seg);
1648 size += sizeof (struct mthca_tavor_ud_seg) / 16;
1652 err = build_mlx_header(dev, to_msqp(qp), ind, wr,
1653 wqe - sizeof (struct mthca_next_seg),
1659 wqe += sizeof (struct mthca_data_seg);
1660 size += sizeof (struct mthca_data_seg) / 16;
1664 if (wr->num_sge > qp->sq.max_gs) {
1665 mthca_err(dev, "too many gathers\n");
1671 for (i = 0; i < wr->num_sge; ++i) {
1672 ((struct mthca_data_seg *) wqe)->byte_count =
1673 cpu_to_be32(wr->sg_list[i].length);
1674 ((struct mthca_data_seg *) wqe)->lkey =
1675 cpu_to_be32(wr->sg_list[i].lkey);
1676 ((struct mthca_data_seg *) wqe)->addr =
1677 cpu_to_be64(wr->sg_list[i].addr);
1678 wqe += sizeof (struct mthca_data_seg);
1679 size += sizeof (struct mthca_data_seg) / 16;
1682 /* Add one more inline data segment for ICRC */
1683 if (qp->transport == MLX) {
1684 ((struct mthca_data_seg *) wqe)->byte_count =
1685 cpu_to_be32((1 << 31) | 4);
1686 ((u32 *) wqe)[1] = 0;
1687 wqe += sizeof (struct mthca_data_seg);
1688 size += sizeof (struct mthca_data_seg) / 16;
1691 qp->wrid[ind + qp->rq.max] = wr->wr_id;
1693 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
1694 mthca_err(dev, "opcode invalid\n");
1700 ((struct mthca_next_seg *) prev_wqe)->nda_op =
1701 cpu_to_be32(((ind << qp->sq.wqe_shift) +
1702 qp->send_wqe_offset) |
1703 mthca_opcode[wr->opcode]);
1705 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1706 cpu_to_be32((size0 ? 0 : MTHCA_NEXT_DBD) | size |
1707 ((wr->send_flags & IB_SEND_FENCE) ?
1708 MTHCA_NEXT_FENCE : 0));
1712 op0 = mthca_opcode[wr->opcode];
1713 f0 = wr->send_flags & IB_SEND_FENCE ?
1714 MTHCA_SEND_DOORBELL_FENCE : 0;
1718 if (unlikely(ind >= qp->sq.max))
1726 doorbell[0] = cpu_to_be32(((qp->sq.next_ind << qp->sq.wqe_shift) +
1727 qp->send_wqe_offset) | f0 | op0);
1728 doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
1732 mthca_write64(doorbell,
1733 dev->kar + MTHCA_SEND_DOORBELL,
1734 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1736 * Make sure doorbells don't leak out of SQ spinlock
1737 * and reach the HCA out of order:
1742 qp->sq.next_ind = ind;
1743 qp->sq.head += nreq;
1745 spin_unlock_irqrestore(&qp->sq.lock, flags);
1749 int mthca_tavor_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1750 struct ib_recv_wr **bad_wr)
1752 struct mthca_dev *dev = to_mdev(ibqp->device);
1753 struct mthca_qp *qp = to_mqp(ibqp);
1755 unsigned long flags;
1765 spin_lock_irqsave(&qp->rq.lock, flags);
1767 /* XXX check that state is OK to post receive */
1769 ind = qp->rq.next_ind;
1771 for (nreq = 0; wr; wr = wr->next) {
1772 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
1773 mthca_err(dev, "RQ %06x full (%u head, %u tail,"
1774 " %d max, %d nreq)\n", qp->qpn,
1775 qp->rq.head, qp->rq.tail,
1782 wqe = get_recv_wqe(qp, ind);
1783 prev_wqe = qp->rq.last;
1786 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1787 ((struct mthca_next_seg *) wqe)->ee_nds =
1788 cpu_to_be32(MTHCA_NEXT_DBD);
1789 ((struct mthca_next_seg *) wqe)->flags = 0;
1791 wqe += sizeof (struct mthca_next_seg);
1792 size = sizeof (struct mthca_next_seg) / 16;
1794 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
1800 for (i = 0; i < wr->num_sge; ++i) {
1801 ((struct mthca_data_seg *) wqe)->byte_count =
1802 cpu_to_be32(wr->sg_list[i].length);
1803 ((struct mthca_data_seg *) wqe)->lkey =
1804 cpu_to_be32(wr->sg_list[i].lkey);
1805 ((struct mthca_data_seg *) wqe)->addr =
1806 cpu_to_be64(wr->sg_list[i].addr);
1807 wqe += sizeof (struct mthca_data_seg);
1808 size += sizeof (struct mthca_data_seg) / 16;
1811 qp->wrid[ind] = wr->wr_id;
1813 ((struct mthca_next_seg *) prev_wqe)->nda_op =
1814 cpu_to_be32((ind << qp->rq.wqe_shift) | 1);
1816 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1817 cpu_to_be32(MTHCA_NEXT_DBD | size);
1823 if (unlikely(ind >= qp->rq.max))
1827 if (unlikely(nreq == MTHCA_TAVOR_MAX_WQES_PER_RECV_DB)) {
1830 doorbell[0] = cpu_to_be32((qp->rq.next_ind << qp->rq.wqe_shift) | size0);
1831 doorbell[1] = cpu_to_be32(qp->qpn << 8);
1835 mthca_write64(doorbell,
1836 dev->kar + MTHCA_RECEIVE_DOORBELL,
1837 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1839 qp->rq.head += MTHCA_TAVOR_MAX_WQES_PER_RECV_DB;
1846 doorbell[0] = cpu_to_be32((qp->rq.next_ind << qp->rq.wqe_shift) | size0);
1847 doorbell[1] = cpu_to_be32((qp->qpn << 8) | nreq);
1851 mthca_write64(doorbell,
1852 dev->kar + MTHCA_RECEIVE_DOORBELL,
1853 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1856 qp->rq.next_ind = ind;
1857 qp->rq.head += nreq;
1860 * Make sure doorbells don't leak out of RQ spinlock and reach
1861 * the HCA out of order:
1865 spin_unlock_irqrestore(&qp->rq.lock, flags);
1869 int mthca_arbel_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1870 struct ib_send_wr **bad_wr)
1872 struct mthca_dev *dev = to_mdev(ibqp->device);
1873 struct mthca_qp *qp = to_mqp(ibqp);
1877 unsigned long flags;
1887 spin_lock_irqsave(&qp->sq.lock, flags);
1889 /* XXX check that state is OK to post send */
1891 ind = qp->sq.head & (qp->sq.max - 1);
1893 for (nreq = 0; wr; ++nreq, wr = wr->next) {
1894 if (unlikely(nreq == MTHCA_ARBEL_MAX_WQES_PER_SEND_DB)) {
1897 doorbell[0] = cpu_to_be32((MTHCA_ARBEL_MAX_WQES_PER_SEND_DB << 24) |
1898 ((qp->sq.head & 0xffff) << 8) |
1900 doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
1902 qp->sq.head += MTHCA_ARBEL_MAX_WQES_PER_SEND_DB;
1906 * Make sure that descriptors are written before
1910 *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff);
1913 * Make sure doorbell record is written before we
1914 * write MMIO send doorbell.
1917 mthca_write64(doorbell,
1918 dev->kar + MTHCA_SEND_DOORBELL,
1919 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1922 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1923 mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1924 " %d max, %d nreq)\n", qp->qpn,
1925 qp->sq.head, qp->sq.tail,
1932 wqe = get_send_wqe(qp, ind);
1933 prev_wqe = qp->sq.last;
1936 ((struct mthca_next_seg *) wqe)->flags =
1937 ((wr->send_flags & IB_SEND_SIGNALED) ?
1938 cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1939 ((wr->send_flags & IB_SEND_SOLICITED) ?
1940 cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0) |
1942 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1943 wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1944 ((struct mthca_next_seg *) wqe)->imm = wr->imm_data;
1946 wqe += sizeof (struct mthca_next_seg);
1947 size = sizeof (struct mthca_next_seg) / 16;
1949 switch (qp->transport) {
1951 switch (wr->opcode) {
1952 case IB_WR_ATOMIC_CMP_AND_SWP:
1953 case IB_WR_ATOMIC_FETCH_AND_ADD:
1954 ((struct mthca_raddr_seg *) wqe)->raddr =
1955 cpu_to_be64(wr->wr.atomic.remote_addr);
1956 ((struct mthca_raddr_seg *) wqe)->rkey =
1957 cpu_to_be32(wr->wr.atomic.rkey);
1958 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1960 wqe += sizeof (struct mthca_raddr_seg);
1962 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1963 ((struct mthca_atomic_seg *) wqe)->swap_add =
1964 cpu_to_be64(wr->wr.atomic.swap);
1965 ((struct mthca_atomic_seg *) wqe)->compare =
1966 cpu_to_be64(wr->wr.atomic.compare_add);
1968 ((struct mthca_atomic_seg *) wqe)->swap_add =
1969 cpu_to_be64(wr->wr.atomic.compare_add);
1970 ((struct mthca_atomic_seg *) wqe)->compare = 0;
1973 wqe += sizeof (struct mthca_atomic_seg);
1974 size += (sizeof (struct mthca_raddr_seg) +
1975 sizeof (struct mthca_atomic_seg)) / 16;
1978 case IB_WR_RDMA_READ:
1979 case IB_WR_RDMA_WRITE:
1980 case IB_WR_RDMA_WRITE_WITH_IMM:
1981 ((struct mthca_raddr_seg *) wqe)->raddr =
1982 cpu_to_be64(wr->wr.rdma.remote_addr);
1983 ((struct mthca_raddr_seg *) wqe)->rkey =
1984 cpu_to_be32(wr->wr.rdma.rkey);
1985 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1986 wqe += sizeof (struct mthca_raddr_seg);
1987 size += sizeof (struct mthca_raddr_seg) / 16;
1991 /* No extra segments required for sends */
1998 switch (wr->opcode) {
1999 case IB_WR_RDMA_WRITE:
2000 case IB_WR_RDMA_WRITE_WITH_IMM:
2001 ((struct mthca_raddr_seg *) wqe)->raddr =
2002 cpu_to_be64(wr->wr.rdma.remote_addr);
2003 ((struct mthca_raddr_seg *) wqe)->rkey =
2004 cpu_to_be32(wr->wr.rdma.rkey);
2005 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
2006 wqe += sizeof (struct mthca_raddr_seg);
2007 size += sizeof (struct mthca_raddr_seg) / 16;
2011 /* No extra segments required for sends */
2018 memcpy(((struct mthca_arbel_ud_seg *) wqe)->av,
2019 to_mah(wr->wr.ud.ah)->av, MTHCA_AV_SIZE);
2020 ((struct mthca_arbel_ud_seg *) wqe)->dqpn =
2021 cpu_to_be32(wr->wr.ud.remote_qpn);
2022 ((struct mthca_arbel_ud_seg *) wqe)->qkey =
2023 cpu_to_be32(wr->wr.ud.remote_qkey);
2025 wqe += sizeof (struct mthca_arbel_ud_seg);
2026 size += sizeof (struct mthca_arbel_ud_seg) / 16;
2030 err = build_mlx_header(dev, to_msqp(qp), ind, wr,
2031 wqe - sizeof (struct mthca_next_seg),
2037 wqe += sizeof (struct mthca_data_seg);
2038 size += sizeof (struct mthca_data_seg) / 16;
2042 if (wr->num_sge > qp->sq.max_gs) {
2043 mthca_err(dev, "too many gathers\n");
2049 for (i = 0; i < wr->num_sge; ++i) {
2050 ((struct mthca_data_seg *) wqe)->byte_count =
2051 cpu_to_be32(wr->sg_list[i].length);
2052 ((struct mthca_data_seg *) wqe)->lkey =
2053 cpu_to_be32(wr->sg_list[i].lkey);
2054 ((struct mthca_data_seg *) wqe)->addr =
2055 cpu_to_be64(wr->sg_list[i].addr);
2056 wqe += sizeof (struct mthca_data_seg);
2057 size += sizeof (struct mthca_data_seg) / 16;
2060 /* Add one more inline data segment for ICRC */
2061 if (qp->transport == MLX) {
2062 ((struct mthca_data_seg *) wqe)->byte_count =
2063 cpu_to_be32((1 << 31) | 4);
2064 ((u32 *) wqe)[1] = 0;
2065 wqe += sizeof (struct mthca_data_seg);
2066 size += sizeof (struct mthca_data_seg) / 16;
2069 qp->wrid[ind + qp->rq.max] = wr->wr_id;
2071 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
2072 mthca_err(dev, "opcode invalid\n");
2078 ((struct mthca_next_seg *) prev_wqe)->nda_op =
2079 cpu_to_be32(((ind << qp->sq.wqe_shift) +
2080 qp->send_wqe_offset) |
2081 mthca_opcode[wr->opcode]);
2083 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
2084 cpu_to_be32(MTHCA_NEXT_DBD | size |
2085 ((wr->send_flags & IB_SEND_FENCE) ?
2086 MTHCA_NEXT_FENCE : 0));
2090 op0 = mthca_opcode[wr->opcode];
2091 f0 = wr->send_flags & IB_SEND_FENCE ?
2092 MTHCA_SEND_DOORBELL_FENCE : 0;
2096 if (unlikely(ind >= qp->sq.max))
2102 doorbell[0] = cpu_to_be32((nreq << 24) |
2103 ((qp->sq.head & 0xffff) << 8) |
2105 doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
2107 qp->sq.head += nreq;
2110 * Make sure that descriptors are written before
2114 *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff);
2117 * Make sure doorbell record is written before we
2118 * write MMIO send doorbell.
2121 mthca_write64(doorbell,
2122 dev->kar + MTHCA_SEND_DOORBELL,
2123 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
2127 * Make sure doorbells don't leak out of SQ spinlock and reach
2128 * the HCA out of order:
2132 spin_unlock_irqrestore(&qp->sq.lock, flags);
2136 int mthca_arbel_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
2137 struct ib_recv_wr **bad_wr)
2139 struct mthca_dev *dev = to_mdev(ibqp->device);
2140 struct mthca_qp *qp = to_mqp(ibqp);
2141 unsigned long flags;
2148 spin_lock_irqsave(&qp->rq.lock, flags);
2150 /* XXX check that state is OK to post receive */
2152 ind = qp->rq.head & (qp->rq.max - 1);
2154 for (nreq = 0; wr; ++nreq, wr = wr->next) {
2155 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
2156 mthca_err(dev, "RQ %06x full (%u head, %u tail,"
2157 " %d max, %d nreq)\n", qp->qpn,
2158 qp->rq.head, qp->rq.tail,
2165 wqe = get_recv_wqe(qp, ind);
2167 ((struct mthca_next_seg *) wqe)->flags = 0;
2169 wqe += sizeof (struct mthca_next_seg);
2171 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
2177 for (i = 0; i < wr->num_sge; ++i) {
2178 ((struct mthca_data_seg *) wqe)->byte_count =
2179 cpu_to_be32(wr->sg_list[i].length);
2180 ((struct mthca_data_seg *) wqe)->lkey =
2181 cpu_to_be32(wr->sg_list[i].lkey);
2182 ((struct mthca_data_seg *) wqe)->addr =
2183 cpu_to_be64(wr->sg_list[i].addr);
2184 wqe += sizeof (struct mthca_data_seg);
2187 if (i < qp->rq.max_gs) {
2188 ((struct mthca_data_seg *) wqe)->byte_count = 0;
2189 ((struct mthca_data_seg *) wqe)->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
2190 ((struct mthca_data_seg *) wqe)->addr = 0;
2193 qp->wrid[ind] = wr->wr_id;
2196 if (unlikely(ind >= qp->rq.max))
2201 qp->rq.head += nreq;
2204 * Make sure that descriptors are written before
2208 *qp->rq.db = cpu_to_be32(qp->rq.head & 0xffff);
2211 spin_unlock_irqrestore(&qp->rq.lock, flags);
2215 void mthca_free_err_wqe(struct mthca_dev *dev, struct mthca_qp *qp, int is_send,
2216 int index, int *dbd, __be32 *new_wqe)
2218 struct mthca_next_seg *next;
2221 * For SRQs, all WQEs generate a CQE, so we're always at the
2222 * end of the doorbell chain.
2230 next = get_send_wqe(qp, index);
2232 next = get_recv_wqe(qp, index);
2234 *dbd = !!(next->ee_nds & cpu_to_be32(MTHCA_NEXT_DBD));
2235 if (next->ee_nds & cpu_to_be32(0x3f))
2236 *new_wqe = (next->nda_op & cpu_to_be32(~0x3f)) |
2237 (next->ee_nds & cpu_to_be32(0x3f));
2242 int __devinit mthca_init_qp_table(struct mthca_dev *dev)
2248 spin_lock_init(&dev->qp_table.lock);
2251 * We reserve 2 extra QPs per port for the special QPs. The
2252 * special QP for port 1 has to be even, so round up.
2254 dev->qp_table.sqp_start = (dev->limits.reserved_qps + 1) & ~1UL;
2255 err = mthca_alloc_init(&dev->qp_table.alloc,
2256 dev->limits.num_qps,
2258 dev->qp_table.sqp_start +
2259 MTHCA_MAX_PORTS * 2);
2263 err = mthca_array_init(&dev->qp_table.qp,
2264 dev->limits.num_qps);
2266 mthca_alloc_cleanup(&dev->qp_table.alloc);
2270 for (i = 0; i < 2; ++i) {
2271 err = mthca_CONF_SPECIAL_QP(dev, i ? IB_QPT_GSI : IB_QPT_SMI,
2272 dev->qp_table.sqp_start + i * 2,
2277 mthca_warn(dev, "CONF_SPECIAL_QP returned "
2278 "status %02x, aborting.\n",
2287 for (i = 0; i < 2; ++i)
2288 mthca_CONF_SPECIAL_QP(dev, i, 0, &status);
2290 mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2291 mthca_alloc_cleanup(&dev->qp_table.alloc);
2296 void mthca_cleanup_qp_table(struct mthca_dev *dev)
2301 for (i = 0; i < 2; ++i)
2302 mthca_CONF_SPECIAL_QP(dev, i, 0, &status);
2304 mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2305 mthca_alloc_cleanup(&dev->qp_table.alloc);