2 driver for LSI L64781 COFDM demodulator
4 Copyright (C) 2001 Holger Waechtler <holger@convergence.de>
5 for Convergence Integrated Media GmbH
6 Marko Kohtala <marko.kohtala@nokia.com>
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 #include <linux/init.h>
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/moduleparam.h>
28 #include <linux/string.h>
29 #include <linux/slab.h>
30 #include "dvb_frontend.h"
36 struct i2c_adapter* i2c;
38 struct dvb_frontend_ops ops;
40 const struct l64781_config* config;
42 struct dvb_frontend frontend;
44 /* private demodulator data */
48 #define dprintk(args...) \
50 if (debug) printk(KERN_DEBUG "l64781: " args); \
55 module_param(debug, int, 0644);
56 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
59 static int l64781_writereg (struct l64781_state* state, u8 reg, u8 data)
62 u8 buf [] = { reg, data };
63 struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 };
65 if ((ret = i2c_transfer(state->i2c, &msg, 1)) != 1)
66 dprintk ("%s: write_reg error (reg == %02x) = %02x!\n",
67 __FUNCTION__, reg, ret);
69 return (ret != 1) ? -1 : 0;
72 static int l64781_readreg (struct l64781_state* state, u8 reg)
77 struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 1 },
78 { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 } };
80 ret = i2c_transfer(state->i2c, msg, 2);
82 if (ret != 2) return ret;
87 static void apply_tps (struct l64781_state* state)
89 l64781_writereg (state, 0x2a, 0x00);
90 l64781_writereg (state, 0x2a, 0x01);
92 /* This here is a little bit questionable because it enables
93 the automatic update of TPS registers. I think we'd need to
94 handle the IRQ from FE to update some other registers as
95 well, or at least implement some magic to tuning to correct
96 to the TPS received from transmission. */
97 l64781_writereg (state, 0x2a, 0x02);
101 static void reset_afc (struct l64781_state* state)
103 /* Set AFC stall for the AFC_INIT_FRQ setting, TIM_STALL for
105 l64781_writereg (state, 0x07, 0x9e); /* stall AFC */
106 l64781_writereg (state, 0x08, 0); /* AFC INIT FREQ */
107 l64781_writereg (state, 0x09, 0);
108 l64781_writereg (state, 0x0a, 0);
109 l64781_writereg (state, 0x07, 0x8e);
110 l64781_writereg (state, 0x0e, 0); /* AGC gain to zero in beginning */
111 l64781_writereg (state, 0x11, 0x80); /* stall TIM */
112 l64781_writereg (state, 0x10, 0); /* TIM_OFFSET_LSB */
113 l64781_writereg (state, 0x12, 0);
114 l64781_writereg (state, 0x13, 0);
115 l64781_writereg (state, 0x11, 0x00);
118 static int reset_and_configure (struct l64781_state* state)
120 u8 buf [] = { 0x06 };
121 struct i2c_msg msg = { .addr = 0x00, .flags = 0, .buf = buf, .len = 1 };
122 // NOTE: this is correct in writing to address 0x00
124 return (i2c_transfer(state->i2c, &msg, 1) == 1) ? 0 : -ENODEV;
127 static int apply_frontend_param (struct dvb_frontend* fe, struct dvb_frontend_parameters *param)
129 struct l64781_state* state = (struct l64781_state*) fe->demodulator_priv;
130 /* The coderates for FEC_NONE, FEC_4_5 and FEC_FEC_6_7 are arbitrary */
131 static const u8 fec_tab[] = { 7, 0, 1, 2, 9, 3, 10, 4 };
132 /* QPSK, QAM_16, QAM_64 */
133 static const u8 qam_tab [] = { 2, 4, 0, 6 };
134 static const u8 bw_tab [] = { 8, 7, 6 }; /* 8Mhz, 7MHz, 6MHz */
135 static const u8 guard_tab [] = { 1, 2, 4, 8 };
136 /* The Grundig 29504-401.04 Tuner comes with 18.432MHz crystal. */
137 static const u32 ppm = 8000;
138 struct dvb_ofdm_parameters *p = ¶m->u.ofdm;
139 u32 ddfs_offset_fixed;
140 /* u32 ddfs_offset_variable = 0x6000-((1000000UL+ppm)/ */
141 /* bw_tab[p->bandWidth]<<10)/15625; */
147 int bw = p->bandwidth - BANDWIDTH_8_MHZ;
149 state->config->pll_set(fe, param);
151 if (param->inversion != INVERSION_ON &&
152 param->inversion != INVERSION_OFF)
155 if (bw < 0 || bw > 2)
158 if (p->code_rate_HP != FEC_1_2 && p->code_rate_HP != FEC_2_3 &&
159 p->code_rate_HP != FEC_3_4 && p->code_rate_HP != FEC_5_6 &&
160 p->code_rate_HP != FEC_7_8)
163 if (p->hierarchy_information != HIERARCHY_NONE &&
164 (p->code_rate_LP != FEC_1_2 && p->code_rate_LP != FEC_2_3 &&
165 p->code_rate_LP != FEC_3_4 && p->code_rate_LP != FEC_5_6 &&
166 p->code_rate_LP != FEC_7_8))
169 if (p->constellation != QPSK && p->constellation != QAM_16 &&
170 p->constellation != QAM_64)
173 if (p->transmission_mode != TRANSMISSION_MODE_2K &&
174 p->transmission_mode != TRANSMISSION_MODE_8K)
177 if (p->guard_interval < GUARD_INTERVAL_1_32 ||
178 p->guard_interval > GUARD_INTERVAL_1_4)
181 if (p->hierarchy_information < HIERARCHY_NONE ||
182 p->hierarchy_information > HIERARCHY_4)
185 ddfs_offset_fixed = 0x4000-(ppm<<16)/bw_tab[p->bandwidth]/1000000;
187 /* This works up to 20000 ppm, it overflows if too large ppm! */
188 init_freq = (((8UL<<25) + (8UL<<19) / 25*ppm / (15625/25)) /
189 bw_tab[p->bandwidth] & 0xFFFFFF);
191 /* SPI bias calculation is slightly modified to fit in 32bit */
192 /* will work for high ppm only... */
193 spi_bias = 378 * (1 << 10);
195 spi_bias *= bw_tab[p->bandwidth];
196 spi_bias *= qam_tab[p->constellation];
197 spi_bias /= p->code_rate_HP + 1;
198 spi_bias /= (guard_tab[p->guard_interval] + 32);
200 spi_bias /= 1000ULL + ppm/1000;
201 spi_bias *= p->code_rate_HP;
203 val0x04 = (p->transmission_mode << 2) | p->guard_interval;
204 val0x05 = fec_tab[p->code_rate_HP];
206 if (p->hierarchy_information != HIERARCHY_NONE)
207 val0x05 |= (p->code_rate_LP - FEC_1_2) << 3;
209 val0x06 = (p->hierarchy_information << 2) | p->constellation;
211 l64781_writereg (state, 0x04, val0x04);
212 l64781_writereg (state, 0x05, val0x05);
213 l64781_writereg (state, 0x06, val0x06);
217 /* Technical manual section 2.6.1, TIM_IIR_GAIN optimal values */
218 l64781_writereg (state, 0x15,
219 p->transmission_mode == TRANSMISSION_MODE_2K ? 1 : 3);
220 l64781_writereg (state, 0x16, init_freq & 0xff);
221 l64781_writereg (state, 0x17, (init_freq >> 8) & 0xff);
222 l64781_writereg (state, 0x18, (init_freq >> 16) & 0xff);
224 l64781_writereg (state, 0x1b, spi_bias & 0xff);
225 l64781_writereg (state, 0x1c, (spi_bias >> 8) & 0xff);
226 l64781_writereg (state, 0x1d, ((spi_bias >> 16) & 0x7f) |
227 (param->inversion == INVERSION_ON ? 0x80 : 0x00));
229 l64781_writereg (state, 0x22, ddfs_offset_fixed & 0xff);
230 l64781_writereg (state, 0x23, (ddfs_offset_fixed >> 8) & 0x3f);
232 l64781_readreg (state, 0x00); /* clear interrupt registers... */
233 l64781_readreg (state, 0x01); /* dto. */
240 static int get_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters* param)
242 struct l64781_state* state = (struct l64781_state*) fe->demodulator_priv;
246 tmp = l64781_readreg(state, 0x04);
249 param->u.ofdm.guard_interval = GUARD_INTERVAL_1_32;
252 param->u.ofdm.guard_interval = GUARD_INTERVAL_1_16;
255 param->u.ofdm.guard_interval = GUARD_INTERVAL_1_8;
258 param->u.ofdm.guard_interval = GUARD_INTERVAL_1_4;
261 switch((tmp >> 2) & 3) {
263 param->u.ofdm.transmission_mode = TRANSMISSION_MODE_2K;
266 param->u.ofdm.transmission_mode = TRANSMISSION_MODE_8K;
269 printk("Unexpected value for transmission_mode\n");
274 tmp = l64781_readreg(state, 0x05);
277 param->u.ofdm.code_rate_HP = FEC_1_2;
280 param->u.ofdm.code_rate_HP = FEC_2_3;
283 param->u.ofdm.code_rate_HP = FEC_3_4;
286 param->u.ofdm.code_rate_HP = FEC_5_6;
289 param->u.ofdm.code_rate_HP = FEC_7_8;
292 printk("Unexpected value for code_rate_HP\n");
294 switch((tmp >> 3) & 7) {
296 param->u.ofdm.code_rate_LP = FEC_1_2;
299 param->u.ofdm.code_rate_LP = FEC_2_3;
302 param->u.ofdm.code_rate_LP = FEC_3_4;
305 param->u.ofdm.code_rate_LP = FEC_5_6;
308 param->u.ofdm.code_rate_LP = FEC_7_8;
311 printk("Unexpected value for code_rate_LP\n");
315 tmp = l64781_readreg(state, 0x06);
318 param->u.ofdm.constellation = QPSK;
321 param->u.ofdm.constellation = QAM_16;
324 param->u.ofdm.constellation = QAM_64;
327 printk("Unexpected value for constellation\n");
329 switch((tmp >> 2) & 7) {
331 param->u.ofdm.hierarchy_information = HIERARCHY_NONE;
334 param->u.ofdm.hierarchy_information = HIERARCHY_1;
337 param->u.ofdm.hierarchy_information = HIERARCHY_2;
340 param->u.ofdm.hierarchy_information = HIERARCHY_4;
343 printk("Unexpected value for hierarchy\n");
347 tmp = l64781_readreg (state, 0x1d);
348 param->inversion = (tmp & 0x80) ? INVERSION_ON : INVERSION_OFF;
350 tmp = (int) (l64781_readreg (state, 0x08) |
351 (l64781_readreg (state, 0x09) << 8) |
352 (l64781_readreg (state, 0x0a) << 16));
353 param->frequency += tmp;
358 static int l64781_read_status(struct dvb_frontend* fe, fe_status_t* status)
360 struct l64781_state* state = (struct l64781_state*) fe->demodulator_priv;
361 int sync = l64781_readreg (state, 0x32);
362 int gain = l64781_readreg (state, 0x0e);
364 l64781_readreg (state, 0x00); /* clear interrupt registers... */
365 l64781_readreg (state, 0x01); /* dto. */
370 *status |= FE_HAS_SIGNAL;
372 if (sync & 0x02) /* VCXO locked, this criteria should be ok */
373 *status |= FE_HAS_CARRIER;
376 *status |= FE_HAS_VITERBI;
379 *status |= FE_HAS_SYNC;
382 *status |= FE_HAS_LOCK;
387 static int l64781_read_ber(struct dvb_frontend* fe, u32* ber)
389 struct l64781_state* state = (struct l64781_state*) fe->demodulator_priv;
391 /* XXX FIXME: set up counting period (reg 0x26...0x28)
393 *ber = l64781_readreg (state, 0x39)
394 | (l64781_readreg (state, 0x3a) << 8);
399 static int l64781_read_signal_strength(struct dvb_frontend* fe, u16* signal_strength)
401 struct l64781_state* state = (struct l64781_state*) fe->demodulator_priv;
403 u8 gain = l64781_readreg (state, 0x0e);
404 *signal_strength = (gain << 8) | gain;
409 static int l64781_read_snr(struct dvb_frontend* fe, u16* snr)
411 struct l64781_state* state = (struct l64781_state*) fe->demodulator_priv;
413 u8 avg_quality = 0xff - l64781_readreg (state, 0x33);
414 *snr = (avg_quality << 8) | avg_quality; /* not exact, but...*/
419 static int l64781_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
421 struct l64781_state* state = (struct l64781_state*) fe->demodulator_priv;
423 *ucblocks = l64781_readreg (state, 0x37)
424 | (l64781_readreg (state, 0x38) << 8);
429 static int l64781_sleep(struct dvb_frontend* fe)
431 struct l64781_state* state = (struct l64781_state*) fe->demodulator_priv;
434 return l64781_writereg (state, 0x3e, 0x5a);
437 static int l64781_init(struct dvb_frontend* fe)
439 struct l64781_state* state = (struct l64781_state*) fe->demodulator_priv;
441 reset_and_configure (state);
444 l64781_writereg (state, 0x3e, 0xa5);
447 l64781_writereg (state, 0x2a, 0x04);
448 l64781_writereg (state, 0x2a, 0x00);
450 /* Set tuner specific things */
451 /* AFC_POL, set also in reset_afc */
452 l64781_writereg (state, 0x07, 0x8e);
454 /* Use internal ADC */
455 l64781_writereg (state, 0x0b, 0x81);
457 /* AGC loop gain, and polarity is positive */
458 l64781_writereg (state, 0x0c, 0x84);
460 /* Internal ADC outputs two's complement */
461 l64781_writereg (state, 0x0d, 0x8c);
463 /* With ppm=8000, it seems the DTR_SENSITIVITY will result in
464 value of 2 with all possible bandwidths and guard
465 intervals, which is the initial value anyway. */
466 /*l64781_writereg (state, 0x19, 0x92);*/
468 /* Everything is two's complement, soft bit and CSI_OUT too */
469 l64781_writereg (state, 0x1e, 0x09);
471 if (state->config->pll_init) state->config->pll_init(fe);
473 /* delay a bit after first init attempt */
482 static int l64781_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings)
484 fesettings->min_delay_ms = 200;
485 fesettings->step_size = 166667;
486 fesettings->max_drift = 166667*2;
490 static void l64781_release(struct dvb_frontend* fe)
492 struct l64781_state* state = (struct l64781_state*) fe->demodulator_priv;
496 static struct dvb_frontend_ops l64781_ops;
498 struct dvb_frontend* l64781_attach(const struct l64781_config* config,
499 struct i2c_adapter* i2c)
501 struct l64781_state* state = NULL;
505 struct i2c_msg msg [] = { { .addr = config->demod_address, .flags = 0, .buf = b0, .len = 1 },
506 { .addr = config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 } };
508 /* allocate memory for the internal state */
509 state = (struct l64781_state*) kmalloc(sizeof(struct l64781_state), GFP_KERNEL);
510 if (state == NULL) goto error;
512 /* setup the state */
513 state->config = config;
515 memcpy(&state->ops, &l64781_ops, sizeof(struct dvb_frontend_ops));
519 * the L64781 won't show up before we send the reset_and_configure()
520 * broadcast. If nothing responds there is no L64781 on the bus...
522 if (reset_and_configure(state) < 0) {
523 dprintk("No response to reset and configure broadcast...\n");
527 /* The chip always responds to reads */
528 if (i2c_transfer(state->i2c, msg, 2) != 2) {
529 dprintk("No response to read on I2C bus\n");
533 /* Save current register contents for bailout */
534 reg0x3e = l64781_readreg(state, 0x3e);
536 /* Reading the POWER_DOWN register always returns 0 */
538 dprintk("Device doesn't look like L64781\n");
542 /* Turn the chip off */
543 l64781_writereg (state, 0x3e, 0x5a);
545 /* Responds to all reads with 0 */
546 if (l64781_readreg(state, 0x1a) != 0) {
547 dprintk("Read 1 returned unexpcted value\n");
551 /* Turn the chip on */
552 l64781_writereg (state, 0x3e, 0xa5);
554 /* Responds with register default value */
555 if (l64781_readreg(state, 0x1a) != 0xa1) {
556 dprintk("Read 2 returned unexpcted value\n");
560 /* create dvb_frontend */
561 state->frontend.ops = &state->ops;
562 state->frontend.demodulator_priv = state;
563 return &state->frontend;
566 if (reg0x3e >= 0) l64781_writereg (state, 0x3e, reg0x3e); /* restore reg 0x3e */
567 if (state) kfree(state);
571 static struct dvb_frontend_ops l64781_ops = {
574 .name = "LSI L64781 DVB-T",
576 /* .frequency_min = ???,*/
577 /* .frequency_max = ???,*/
578 .frequency_stepsize = 166666,
579 /* .frequency_tolerance = ???,*/
580 /* .symbol_rate_tolerance = ???,*/
581 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
582 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
583 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
587 .release = l64781_release,
590 .sleep = l64781_sleep,
592 .set_frontend = apply_frontend_param,
593 .get_frontend = get_frontend,
594 .get_tune_settings = l64781_get_tune_settings,
596 .read_status = l64781_read_status,
597 .read_ber = l64781_read_ber,
598 .read_signal_strength = l64781_read_signal_strength,
599 .read_snr = l64781_read_snr,
600 .read_ucblocks = l64781_read_ucblocks,
603 MODULE_DESCRIPTION("LSI L64781 DVB-T Demodulator driver");
604 MODULE_AUTHOR("Holger Waechtler, Marko Kohtala");
605 MODULE_LICENSE("GPL");
607 EXPORT_SYMBOL(l64781_attach);