2 Driver for STV0297 demodulator
4 Copyright (C) 2004 Andrew de Quincey <adq_dvb@lidskialf.net>
5 Copyright (C) 2003-2004 Dennis Noermann <dennis.noermann@noernet.de>
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 #include <linux/init.h>
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/string.h>
26 #include <linux/delay.h>
28 #include "dvb_frontend.h"
31 struct stv0297_state {
33 struct i2c_adapter* i2c;
35 struct dvb_frontend_ops ops;
37 const struct stv0297_config* config;
39 struct dvb_frontend frontend;
43 unsigned long base_freq;
49 #define dprintk(x...) printk(x)
54 #define STV0297_CLOCK_KHZ 28900
56 static u8 init_tab [] = {
145 static int stv0297_writereg (struct stv0297_state* state, u8 reg, u8 data)
148 u8 buf [] = { reg, data };
149 struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 };
151 ret = i2c_transfer (state->i2c, &msg, 1);
154 dprintk("%s: writereg error (reg == 0x%02x, val == 0x%02x, "
155 "ret == %i)\n", __FUNCTION__, reg, data, ret);
157 return (ret != 1) ? -1 : 0;
160 static int stv0297_readreg (struct stv0297_state* state, u8 reg)
165 struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 1 },
166 { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 } };
168 // this device needs a STOP between the register and data
169 if ((ret = i2c_transfer (state->i2c, &msg[0], 1)) != 1) {
170 dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __FUNCTION__, reg, ret);
173 if ((ret = i2c_transfer (state->i2c, &msg[1], 1)) != 1) {
174 dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __FUNCTION__, reg, ret);
181 static int stv0297_writereg_mask (struct stv0297_state* state, u8 reg, u8 mask, u8 data)
185 val = stv0297_readreg(state, reg);
187 val |= (data & mask);
188 stv0297_writereg(state, reg, val);
193 static int stv0297_readregs (struct stv0297_state* state, u8 reg1, u8 *b, u8 len)
196 struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = ®1, .len = 1 },
197 { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b, .len = len } };
199 // this device needs a STOP between the register and data
200 if ((ret = i2c_transfer (state->i2c, &msg[0], 1)) != 1) {
201 dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __FUNCTION__, reg1, ret);
204 if ((ret = i2c_transfer (state->i2c, &msg[1], 1)) != 1) {
205 dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __FUNCTION__, reg1, ret);
212 static void stv0297_set_symbolrate(struct stv0297_state *state, u32 srate)
216 tmp = 131072L * srate; /* 131072 = 2^17 */
217 tmp = tmp / (STV0297_CLOCK_KHZ / 4); /* 1/4 = 2^-2 */
218 tmp = tmp * 8192L; /* 8192 = 2^13 */
220 stv0297_writereg (state, 0x55,(unsigned char)(tmp & 0xFF));
221 stv0297_writereg (state, 0x56,(unsigned char)(tmp>> 8));
222 stv0297_writereg (state, 0x57,(unsigned char)(tmp>>16));
223 stv0297_writereg (state, 0x58,(unsigned char)(tmp>>24));
226 static void stv0297_set_sweeprate(struct stv0297_state *state, short fshift, long symrate)
230 tmp = (long) fshift *262144L; /* 262144 = 2*18 */
232 tmp *= 1024; /* 1024 = 2*10 */
242 stv0297_writereg(state, 0x60, tmp & 0xFF);
243 stv0297_writereg_mask(state, 0x69, 0xF0, (tmp >> 4) & 0xf0);
246 static void stv0297_set_carrieroffset(struct stv0297_state* state, long offset)
250 /* symrate is hardcoded to 10000 */
251 tmp = offset * 26844L; /* (2**28)/10000 */
256 stv0297_writereg(state, 0x66, (unsigned char) (tmp & 0xFF));
257 stv0297_writereg(state, 0x67, (unsigned char) (tmp >> 8));
258 stv0297_writereg(state, 0x68, (unsigned char) (tmp >> 16));
259 stv0297_writereg_mask(state, 0x69, 0x0F, (tmp >> 24) & 0x0f);
262 static long stv0297_get_carrieroffset(struct stv0297_state* state)
267 stv0297_writereg(state,0x6B, 0x00);
269 raw = stv0297_readreg(state,0x66);
270 raw |= (stv0297_readreg(state,0x67) << 8);
271 raw |= (stv0297_readreg(state,0x68) << 16);
272 raw |= (stv0297_readreg(state,0x69) & 0x0F) << 24;
280 static void stv0297_set_initialdemodfreq(struct stv0297_state* state, long freq)
285 if (freq > 10000) freq -= STV0297_CLOCK_KHZ;
288 do_div(tmp, STV0297_CLOCK_KHZ);
289 if (tmp > 0xffff) tmp = 0xffff; // check this calculation
291 stv0297_writereg_mask(state, 0x25, 0x80, 0x80);
292 stv0297_writereg(state, 0x21, tmp >> 8);
293 stv0297_writereg(state, 0x20, tmp);
297 static int stv0297_set_qam(struct stv0297_state* state, fe_modulation_t modulation)
326 stv0297_writereg_mask(state, 0x00, 0x70, val << 4);
331 static int stv0297_set_inversion(struct stv0297_state* state, fe_spectral_inversion_t inversion)
348 stv0297_writereg_mask(state, 0x83, 0x08, val << 3);
365 int stv0297_enable_plli2c(struct dvb_frontend* fe)
367 struct stv0297_state* state = (struct stv0297_state*) fe->demodulator_priv;
369 stv0297_writereg(state, 0x87, 0x78);
370 stv0297_writereg(state, 0x86, 0xc8);
375 static int stv0297_init (struct dvb_frontend* fe)
377 struct stv0297_state* state = (struct stv0297_state*) fe->demodulator_priv;
381 stv0297_writereg_mask(state, 0x80, 1, 1);
382 stv0297_writereg_mask(state, 0x80, 1, 0);
384 /* reset deinterleaver */
385 stv0297_writereg_mask(state, 0x81, 1, 1);
386 stv0297_writereg_mask(state, 0x81, 1, 0);
388 /* load init table */
389 for (i=0; i<sizeof(init_tab); i+=2) {
390 stv0297_writereg (state, init_tab[i], init_tab[i+1]);
393 /* set a dummy symbol rate */
394 stv0297_set_symbolrate(state, 6900);
396 /* invert AGC1 polarity */
397 stv0297_writereg_mask(state, 0x88, 0x10, 0x10);
399 /* setup bit error counting */
400 stv0297_writereg_mask(state, 0xA0, 0x80, 0x00);
401 stv0297_writereg_mask(state, 0xA0, 0x10, 0x00);
402 stv0297_writereg_mask(state, 0xA0, 0x08, 0x00);
403 stv0297_writereg_mask(state, 0xA0, 0x07, 0x04);
406 stv0297_writereg(state, 0x4a, 0x00);
407 stv0297_writereg(state, 0x4b, state->pwm);
410 if (state->config->pll_init)
411 state->config->pll_init(fe);
416 static int stv0297_read_status(struct dvb_frontend* fe, fe_status_t* status)
418 struct stv0297_state* state = (struct stv0297_state*) fe->demodulator_priv;
420 u8 sync = stv0297_readreg (state, 0xDF);
425 FE_HAS_SYNC | FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_LOCK;
429 static int stv0297_read_ber(struct dvb_frontend* fe, u32* ber)
431 struct stv0297_state* state = (struct stv0297_state*) fe->demodulator_priv;
434 stv0297_writereg (state, 0xA0, 0x80); // Start Counting bit errors for 4096 Bytes
435 mdelay(25); // Hopefully got 4096 Bytes
436 stv0297_readregs (state, 0xA0, BER, 3);
438 *ber = (BER[2] << 8 | BER[1]) / ( 8 * 4096);
444 static int stv0297_read_signal_strength(struct dvb_frontend* fe, u16* strength)
446 struct stv0297_state* state = (struct stv0297_state*) fe->demodulator_priv;
449 stv0297_readregs (state, 0x41, STRENGTH, 2);
450 *strength = (STRENGTH[1] & 0x03) << 8 | STRENGTH[0];
455 static int stv0297_read_snr(struct dvb_frontend* fe, u16* snr)
457 struct stv0297_state* state = (struct stv0297_state*) fe->demodulator_priv;
460 stv0297_readregs (state, 0x07, SNR, 2);
461 *snr = SNR[1] << 8 | SNR[0];
466 static int stv0297_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
468 struct stv0297_state* state = (struct stv0297_state*) fe->demodulator_priv;
470 *ucblocks = (stv0297_readreg (state, 0xD5) << 8)
471 | stv0297_readreg (state, 0xD4);
476 static int stv0297_set_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters * p)
478 struct stv0297_state* state = (struct stv0297_state*) fe->demodulator_priv;
485 unsigned long starttime;
486 unsigned long timeout;
488 switch(p->u.qam.modulation) {
510 // determine inversion dependant parameters
511 carrieroffset = -330;
512 switch(p->inversion) {
517 sweeprate = -sweeprate;
518 carrieroffset = -carrieroffset;
525 state->config->pll_set(fe, p);
527 /* clear software interrupts */
528 stv0297_writereg(state, 0x82, 0x0);
530 /* set initial demodulation frequency */
531 stv0297_set_initialdemodfreq(state, state->freq_off + 7250);
534 stv0297_writereg_mask(state, 0x43, 0x10, 0x00);
535 stv0297_writereg(state, 0x41, 0x00);
536 stv0297_writereg_mask(state, 0x42, 0x03, 0x01);
537 stv0297_writereg_mask(state, 0x36, 0x60, 0x00);
538 stv0297_writereg_mask(state, 0x36, 0x18, 0x00);
539 stv0297_writereg_mask(state, 0x71, 0x80, 0x80);
540 stv0297_writereg(state, 0x72, 0x00);
541 stv0297_writereg(state, 0x73, 0x00);
542 stv0297_writereg_mask(state, 0x74, 0x0F, 0x00);
543 stv0297_writereg_mask(state, 0x43, 0x08, 0x00);
544 stv0297_writereg_mask(state, 0x71, 0x80, 0x00);
547 stv0297_writereg_mask(state, 0x5a, 0x20, 0x20);
548 stv0297_writereg_mask(state, 0x5b, 0x02, 0x02);
549 stv0297_writereg_mask(state, 0x5b, 0x02, 0x00);
550 stv0297_writereg_mask(state, 0x5b, 0x01, 0x00);
551 stv0297_writereg_mask(state, 0x5a, 0x40, 0x40);
553 /* disable frequency sweep */
554 stv0297_writereg_mask(state, 0x6a, 0x01, 0x00);
556 /* reset deinterleaver */
557 stv0297_writereg_mask(state, 0x81, 0x01, 0x01);
558 stv0297_writereg_mask(state, 0x81, 0x01, 0x00);
561 stv0297_writereg_mask(state, 0x83, 0x20, 0x20);
562 stv0297_writereg_mask(state, 0x83, 0x20, 0x00);
564 /* reset equaliser */
565 u_threshold = stv0297_readreg(state, 0x00) & 0xf;
566 initial_u = stv0297_readreg(state, 0x01) >> 4;
567 blind_u = stv0297_readreg(state, 0x01) & 0xf;
568 stv0297_writereg_mask(state, 0x84, 0x01, 0x01);
569 stv0297_writereg_mask(state, 0x84, 0x01, 0x00);
570 stv0297_writereg_mask(state, 0x00, 0x0f, u_threshold);
571 stv0297_writereg_mask(state, 0x01, 0xf0, initial_u << 4);
572 stv0297_writereg_mask(state, 0x01, 0x0f, blind_u);
574 /* data comes from internal A/D */
575 stv0297_writereg_mask(state, 0x87, 0x80, 0x00);
577 /* clear phase registers */
578 stv0297_writereg(state, 0x63, 0x00);
579 stv0297_writereg(state, 0x64, 0x00);
580 stv0297_writereg(state, 0x65, 0x00);
581 stv0297_writereg(state, 0x66, 0x00);
582 stv0297_writereg(state, 0x67, 0x00);
583 stv0297_writereg(state, 0x68, 0x00);
584 stv0297_writereg_mask(state, 0x69, 0x0f, 0x00);
587 stv0297_set_qam(state, p->u.qam.modulation);
588 stv0297_set_symbolrate(state, p->u.qam.symbol_rate/1000);
589 stv0297_set_sweeprate(state, sweeprate, p->u.qam.symbol_rate / 1000);
590 stv0297_set_carrieroffset(state, carrieroffset);
591 stv0297_set_inversion(state, p->inversion);
594 stv0297_writereg_mask(state, 0x88, 0x08, 0x08);
595 stv0297_writereg_mask(state, 0x5a, 0x20, 0x00);
596 stv0297_writereg_mask(state, 0x6a, 0x01, 0x01);
597 stv0297_writereg_mask(state, 0x43, 0x40, 0x40);
598 stv0297_writereg_mask(state, 0x5b, 0x30, 0x00);
599 stv0297_writereg_mask(state, 0x03, 0x0c, 0x0c);
600 stv0297_writereg_mask(state, 0x03, 0x03, 0x03);
601 stv0297_writereg_mask(state, 0x43, 0x10, 0x10);
603 /* wait for WGAGC lock */
605 timeout = jiffies + (200*HZ)/1000;
606 while(time_before(jiffies, timeout)) {
608 if (stv0297_readreg(state, 0x43) & 0x08)
611 if (time_after(jiffies, timeout)) {
616 /* wait for equaliser partial convergence */
617 timeout = jiffies + (50*HZ)/1000;
618 while(time_before(jiffies, timeout)) {
621 if (stv0297_readreg(state, 0x82) & 0x04) {
625 if (time_after(jiffies, timeout)) {
629 /* wait for equaliser full convergence */
630 timeout = jiffies + (delay*HZ)/1000;
631 while(time_before(jiffies, timeout)) {
634 if (stv0297_readreg(state, 0x82) & 0x08) {
638 if (time_after(jiffies, timeout)) {
643 stv0297_writereg_mask(state, 0x6a, 1, 0);
644 stv0297_writereg_mask(state, 0x88, 8, 0);
646 /* wait for main lock */
647 timeout = jiffies + (20*HZ)/1000;
648 while(time_before(jiffies, timeout)) {
651 if (stv0297_readreg(state, 0xDF) & 0x80) {
655 if (time_after(jiffies, timeout)) {
660 /* is it still locked after that delay? */
661 if (!(stv0297_readreg(state, 0xDF) & 0x80)) {
666 stv0297_writereg_mask(state, 0x5a, 0x40, 0x00);
667 state->freq_off = stv0297_get_carrieroffset(state);
668 state->base_freq = p->frequency;
672 stv0297_writereg_mask(state, 0x6a, 0x01, 0x00);
676 static int stv0297_get_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters * p)
678 struct stv0297_state* state = (struct stv0297_state*) fe->demodulator_priv;
681 reg_00 = stv0297_readreg(state, 0x00);
682 reg_83 = stv0297_readreg(state, 0x83);
684 p->frequency = state->base_freq + state->freq_off;
685 p->inversion = (reg_83 & 0x08) ? INVERSION_ON : INVERSION_OFF;
686 p->u.qam.symbol_rate = 0;
687 p->u.qam.fec_inner = 0;
689 switch((reg_00 >> 4) & 0x7) {
691 p->u.qam.modulation = QAM_16;
694 p->u.qam.modulation = QAM_32;
697 p->u.qam.modulation = QAM_128;
700 p->u.qam.modulation = QAM_256;
703 p->u.qam.modulation = QAM_64;
710 static void stv0297_release(struct dvb_frontend* fe)
712 struct stv0297_state* state = (struct stv0297_state*) fe->demodulator_priv;
716 static struct dvb_frontend_ops stv0297_ops;
718 struct dvb_frontend* stv0297_attach(const struct stv0297_config* config,
719 struct i2c_adapter *i2c, int pwm)
721 struct stv0297_state* state = NULL;
723 /* allocate memory for the internal state */
724 state = (struct stv0297_state*) kmalloc(sizeof(struct stv0297_state), GFP_KERNEL);
728 /* setup the state */
729 state->config = config;
731 memcpy(&state->ops, &stv0297_ops, sizeof(struct dvb_frontend_ops));
733 state->base_freq = 0;
736 /* check if the demod is there */
737 if ((stv0297_readreg(state, 0x80) & 0x70) != 0x20)
740 /* create dvb_frontend */
741 state->frontend.ops = &state->ops;
742 state->frontend.demodulator_priv = state;
743 return &state->frontend;
751 static struct dvb_frontend_ops stv0297_ops = {
754 .name = "ST STV0297 DVB-C",
756 .frequency_min = 64000000,
757 .frequency_max = 1300000000,
758 .frequency_stepsize = 62500,
759 .symbol_rate_min = 870000,
760 .symbol_rate_max = 11700000,
761 .caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 |
762 FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_FEC_AUTO},
764 .release = stv0297_release,
766 .init = stv0297_init,
768 .set_frontend = stv0297_set_frontend,
769 .get_frontend = stv0297_get_frontend,
771 .read_status = stv0297_read_status,
772 .read_ber = stv0297_read_ber,
773 .read_signal_strength = stv0297_read_signal_strength,
774 .read_snr = stv0297_read_snr,
775 .read_ucblocks = stv0297_read_ucblocks,
778 MODULE_DESCRIPTION("ST STV0297 DVB-C Demodulator driver");
779 MODULE_AUTHOR("Dennis Noermann and Andrew de Quincey");
780 MODULE_LICENSE("GPL");
782 EXPORT_SYMBOL(stv0297_attach);
783 EXPORT_SYMBOL(stv0297_enable_plli2c);