drivers/media/dvb/frontends/tda1004x.c

   1   /*
   2      Driver for Philips tda1004xh OFDM Demodulator
   3
   4      (c) 2003, 2004 Andrew de Quincey & Robert Schlabbach
   5
   6      This program is free software; you can redistribute it and/or modify
   7      it under the terms of the GNU General Public License as published by
   8      the Free Software Foundation; either version 2 of the License, or
   9      (at your option) any later version.
  10
  11      This program is distributed in the hope that it will be useful,
  12      but WITHOUT ANY WARRANTY; without even the implied warranty of
  13      MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14
  15      GNU General Public License for more details.
  16
  17      You should have received a copy of the GNU General Public License
  18      along with this program; if not, write to the Free Software
  19      Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20
  21    */
  22 /*
  23  * This driver needs external firmware. Please use the commands
  24  * "<kerneldir>/Documentation/dvb/get_dvb_firmware tda10045",
  25  * "<kerneldir>/Documentation/dvb/get_dvb_firmware tda10046" to
  26  * download/extract them, and then copy them to /usr/lib/hotplug/firmware
  27  * or /lib/firmware (depending on configuration of firmware hotplug).
  28  */
  29 #define TDA10045_DEFAULT_FIRMWARE "dvb-fe-tda10045.fw"
  30 #define TDA10046_DEFAULT_FIRMWARE "dvb-fe-tda10046.fw"
  31
  32 #include <linux/init.h>
  33 #include <linux/module.h>
  34 #include <linux/moduleparam.h>
  35 #include <linux/device.h>
  36 #include <linux/jiffies.h>
  37 #include <linux/string.h>
  38 #include <linux/slab.h>
  39
  40 #include "dvb_frontend.h"
  41 #include "tda1004x.h"
  42
  43 enum tda1004x_demod {
  44         TDA1004X_DEMOD_TDA10045,
  45         TDA1004X_DEMOD_TDA10046,
  46 };
  47
  48 struct tda1004x_state {
  49         struct i2c_adapter* i2c;
  50         struct dvb_frontend_ops ops;
  51         const struct tda1004x_config* config;
  52         struct dvb_frontend frontend;
  53
  54         /* private demod data */
  55         u8 initialised;
  56         enum tda1004x_demod demod_type;
  57 };
  58
  59 static int debug;
  60 #define dprintk(args...) \
  61         do { \
  62                 if (debug) printk(KERN_DEBUG "tda1004x: " args); \
  63         } while (0)
  64
  65 #define TDA1004X_CHIPID          0x00
  66 #define TDA1004X_AUTO            0x01
  67 #define TDA1004X_IN_CONF1        0x02
  68 #define TDA1004X_IN_CONF2        0x03
  69 #define TDA1004X_OUT_CONF1       0x04
  70 #define TDA1004X_OUT_CONF2       0x05
  71 #define TDA1004X_STATUS_CD       0x06
  72 #define TDA1004X_CONFC4          0x07
  73 #define TDA1004X_DSSPARE2        0x0C
  74 #define TDA10045H_CODE_IN        0x0D
  75 #define TDA10045H_FWPAGE         0x0E
  76 #define TDA1004X_SCAN_CPT        0x10
  77 #define TDA1004X_DSP_CMD         0x11
  78 #define TDA1004X_DSP_ARG         0x12
  79 #define TDA1004X_DSP_DATA1       0x13
  80 #define TDA1004X_DSP_DATA2       0x14
  81 #define TDA1004X_CONFADC1        0x15
  82 #define TDA1004X_CONFC1          0x16
  83 #define TDA10045H_S_AGC          0x1a
  84 #define TDA10046H_AGC_TUN_LEVEL  0x1a
  85 #define TDA1004X_SNR             0x1c
  86 #define TDA1004X_CONF_TS1        0x1e
  87 #define TDA1004X_CONF_TS2        0x1f
  88 #define TDA1004X_CBER_RESET      0x20
  89 #define TDA1004X_CBER_MSB        0x21
  90 #define TDA1004X_CBER_LSB        0x22
  91 #define TDA1004X_CVBER_LUT       0x23
  92 #define TDA1004X_VBER_MSB        0x24
  93 #define TDA1004X_VBER_MID        0x25
  94 #define TDA1004X_VBER_LSB        0x26
  95 #define TDA1004X_UNCOR           0x27
  96
  97 #define TDA10045H_CONFPLL_P      0x2D
  98 #define TDA10045H_CONFPLL_M_MSB  0x2E
  99 #define TDA10045H_CONFPLL_M_LSB  0x2F
 100 #define TDA10045H_CONFPLL_N      0x30
 101
 102 #define TDA10046H_CONFPLL1       0x2D
 103 #define TDA10046H_CONFPLL2       0x2F
 104 #define TDA10046H_CONFPLL3       0x30
 105 #define TDA10046H_TIME_WREF1     0x31
 106 #define TDA10046H_TIME_WREF2     0x32
 107 #define TDA10046H_TIME_WREF3     0x33
 108 #define TDA10046H_TIME_WREF4     0x34
 109 #define TDA10046H_TIME_WREF5     0x35
 110
 111 #define TDA10045H_UNSURW_MSB     0x31
 112 #define TDA10045H_UNSURW_LSB     0x32
 113 #define TDA10045H_WREF_MSB       0x33
 114 #define TDA10045H_WREF_MID       0x34
 115 #define TDA10045H_WREF_LSB       0x35
 116 #define TDA10045H_MUXOUT         0x36
 117 #define TDA1004X_CONFADC2        0x37
 118
 119 #define TDA10045H_IOFFSET        0x38
 120
 121 #define TDA10046H_CONF_TRISTATE1 0x3B
 122 #define TDA10046H_CONF_TRISTATE2 0x3C
 123 #define TDA10046H_CONF_POLARITY  0x3D
 124 #define TDA10046H_FREQ_OFFSET    0x3E
 125 #define TDA10046H_GPIO_OUT_SEL   0x41
 126 #define TDA10046H_GPIO_SELECT    0x42
 127 #define TDA10046H_AGC_CONF       0x43
 128 #define TDA10046H_AGC_THR        0x44
 129 #define TDA10046H_AGC_RENORM     0x45
 130 #define TDA10046H_AGC_GAINS      0x46
 131 #define TDA10046H_AGC_TUN_MIN    0x47
 132 #define TDA10046H_AGC_TUN_MAX    0x48
 133 #define TDA10046H_AGC_IF_MIN     0x49
 134 #define TDA10046H_AGC_IF_MAX     0x4A
 135
 136 #define TDA10046H_FREQ_PHY2_MSB  0x4D
 137 #define TDA10046H_FREQ_PHY2_LSB  0x4E
 138
 139 #define TDA10046H_CVBER_CTRL     0x4F
 140 #define TDA10046H_AGC_IF_LEVEL   0x52
 141 #define TDA10046H_CODE_CPT       0x57
 142 #define TDA10046H_CODE_IN        0x58
 143
 144
 145 static int tda1004x_write_byteI(struct tda1004x_state *state, int reg, int data)
 146 {
 147         int ret;
 148         u8 buf[] = { reg, data };
 149         struct i2c_msg msg = { .flags = 0, .buf = buf, .len = 2 };
 150
 151         dprintk("%s: reg=0x%x, data=0x%x\n", __FUNCTION__, reg, data);
 152
 153         msg.addr = state->config->demod_address;
 154         ret = i2c_transfer(state->i2c, &msg, 1);
 155
 156         if (ret != 1)
 157                 dprintk("%s: error reg=0x%x, data=0x%x, ret=%i\n",
 158                         __FUNCTION__, reg, data, ret);
 159
 160         dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __FUNCTION__,
 161                 reg, data, ret);
 162         return (ret != 1) ? -1 : 0;
 163 }
 164
 165 static int tda1004x_read_byte(struct tda1004x_state *state, int reg)
 166 {
 167         int ret;
 168         u8 b0[] = { reg };
 169         u8 b1[] = { 0 };
 170         struct i2c_msg msg[] = {{ .flags = 0, .buf = b0, .len = 1 },
 171                                 { .flags = I2C_M_RD, .buf = b1, .len = 1 }};
 172
 173         dprintk("%s: reg=0x%x\n", __FUNCTION__, reg);
 174
 175         msg[0].addr = state->config->demod_address;
 176         msg[1].addr = state->config->demod_address;
 177         ret = i2c_transfer(state->i2c, msg, 2);
 178
 179         if (ret != 2) {
 180                 dprintk("%s: error reg=0x%x, ret=%i\n", __FUNCTION__, reg,
 181                         ret);
 182                 return -1;
 183         }
 184
 185         dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __FUNCTION__,
 186                 reg, b1[0], ret);
 187         return b1[0];
 188 }
 189
 190 static int tda1004x_write_mask(struct tda1004x_state *state, int reg, int mask, int data)
 191 {
 192         int val;
 193         dprintk("%s: reg=0x%x, mask=0x%x, data=0x%x\n", __FUNCTION__, reg,
 194                 mask, data);
 195
 196         // read a byte and check
 197         val = tda1004x_read_byte(state, reg);
 198         if (val < 0)
 199                 return val;
 200
 201         // mask if off
 202         val = val & ~mask;
 203         val |= data & 0xff;
 204
 205         // write it out again
 206         return tda1004x_write_byteI(state, reg, val);
 207 }
 208
 209 static int tda1004x_write_buf(struct tda1004x_state *state, int reg, unsigned char *buf, int len)
 210 {
 211         int i;
 212         int result;
 213
 214         dprintk("%s: reg=0x%x, len=0x%x\n", __FUNCTION__, reg, len);
 215
 216         result = 0;
 217         for (i = 0; i < len; i++) {
 218                 result = tda1004x_write_byteI(state, reg + i, buf[i]);
 219                 if (result != 0)
 220                         break;
 221         }
 222
 223         return result;
 224 }
 225
 226 static int tda1004x_enable_tuner_i2c(struct tda1004x_state *state)
 227 {
 228         int result;
 229         dprintk("%s\n", __FUNCTION__);
 230
 231         result = tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 2);
 232         msleep(20);
 233         return result;
 234 }
 235
 236 static int tda1004x_disable_tuner_i2c(struct tda1004x_state *state)
 237 {
 238         dprintk("%s\n", __FUNCTION__);
 239
 240         return tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 0);
 241 }
 242
 243 static int tda10045h_set_bandwidth(struct tda1004x_state *state,
 244                                    fe_bandwidth_t bandwidth)
 245 {
 246         static u8 bandwidth_6mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x60, 0x1e, 0xa7, 0x45, 0x4f };
 247         static u8 bandwidth_7mhz[] = { 0x02, 0x00, 0x37, 0x00, 0x4a, 0x2f, 0x6d, 0x76, 0xdb };
 248         static u8 bandwidth_8mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x48, 0x17, 0x89, 0xc7, 0x14 };
 249
 250         switch (bandwidth) {
 251         case BANDWIDTH_6_MHZ:
 252                 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_6mhz, sizeof(bandwidth_6mhz));
 253                 break;
 254
 255         case BANDWIDTH_7_MHZ:
 256                 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_7mhz, sizeof(bandwidth_7mhz));
 257                 break;
 258
 259         case BANDWIDTH_8_MHZ:
 260                 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_8mhz, sizeof(bandwidth_8mhz));
 261                 break;
 262
 263         default:
 264                 return -EINVAL;
 265         }
 266
 267         tda1004x_write_byteI(state, TDA10045H_IOFFSET, 0);
 268
 269         return 0;
 270 }
 271
 272 static int tda10046h_set_bandwidth(struct tda1004x_state *state,
 273                                    fe_bandwidth_t bandwidth)
 274 {
 275         static u8 bandwidth_6mhz_53M[] = { 0x7b, 0x2e, 0x11, 0xf0, 0xd2 };
 276         static u8 bandwidth_7mhz_53M[] = { 0x6a, 0x02, 0x6a, 0x43, 0x9f };
 277         static u8 bandwidth_8mhz_53M[] = { 0x5c, 0x32, 0xc2, 0x96, 0x6d };
 278
 279         static u8 bandwidth_6mhz_48M[] = { 0x70, 0x02, 0x49, 0x24, 0x92 };
 280         static u8 bandwidth_7mhz_48M[] = { 0x60, 0x02, 0xaa, 0xaa, 0xab };
 281         static u8 bandwidth_8mhz_48M[] = { 0x54, 0x03, 0x0c, 0x30, 0xc3 };
 282         int tda10046_clk53m;
 283
 284         if ((state->config->if_freq == TDA10046_FREQ_045) ||
 285             (state->config->if_freq == TDA10046_FREQ_052))
 286                 tda10046_clk53m = 0;
 287         else
 288                 tda10046_clk53m = 1;
 289         switch (bandwidth) {
 290         case BANDWIDTH_6_MHZ:
 291                 if (tda10046_clk53m)
 292                         tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_6mhz_53M,
 293                                                   sizeof(bandwidth_6mhz_53M));
 294                 else
 295                         tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_6mhz_48M,
 296                                                   sizeof(bandwidth_6mhz_48M));
 297                 if (state->config->if_freq == TDA10046_FREQ_045) {
 298                         tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0a);
 299                         tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xab);
 300                 }
 301                 break;
 302
 303         case BANDWIDTH_7_MHZ:
 304                 if (tda10046_clk53m)
 305                         tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_7mhz_53M,
 306                                                   sizeof(bandwidth_7mhz_53M));
 307                 else
 308                         tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_7mhz_48M,
 309                                                   sizeof(bandwidth_7mhz_48M));
 310                 if (state->config->if_freq == TDA10046_FREQ_045) {
 311                         tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0c);
 312                         tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x00);
 313                 }
 314                 break;
 315
 316         case BANDWIDTH_8_MHZ:
 317                 if (tda10046_clk53m)
 318                         tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_8mhz_53M,
 319                                                   sizeof(bandwidth_8mhz_53M));
 320                 else
 321                         tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_8mhz_48M,
 322                                                   sizeof(bandwidth_8mhz_48M));
 323                 if (state->config->if_freq == TDA10046_FREQ_045) {
 324                         tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0d);
 325                         tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x55);
 326                 }
 327                 break;
 328
 329         default:
 330                 return -EINVAL;
 331         }
 332
 333         return 0;
 334 }
 335
 336 static int tda1004x_do_upload(struct tda1004x_state *state,
 337                               unsigned char *mem, unsigned int len,
 338                               u8 dspCodeCounterReg, u8 dspCodeInReg)
 339 {
 340         u8 buf[65];
 341         struct i2c_msg fw_msg = { .flags = 0, .buf = buf, .len = 0 };
 342         int tx_size;
 343         int pos = 0;
 344
 345         /* clear code counter */
 346         tda1004x_write_byteI(state, dspCodeCounterReg, 0);
 347         fw_msg.addr = state->config->demod_address;
 348
 349         buf[0] = dspCodeInReg;
 350         while (pos != len) {
 351                 // work out how much to send this time
 352                 tx_size = len - pos;
 353                 if (tx_size > 0x10)
 354                         tx_size = 0x10;
 355
 356                 // send the chunk
 357                 memcpy(buf + 1, mem + pos, tx_size);
 358                 fw_msg.len = tx_size + 1;
 359                 if (i2c_transfer(state->i2c, &fw_msg, 1) != 1) {
 360                         printk(KERN_ERR "tda1004x: Error during firmware upload\n");
 361                         return -EIO;
 362                 }
 363                 pos += tx_size;
 364
 365                 dprintk("%s: fw_pos=0x%x\n", __FUNCTION__, pos);
 366         }
 367         // give the DSP a chance to settle 03/10/05 Hac
 368         msleep(100);
 369
 370         return 0;
 371 }
 372
 373 static int tda1004x_check_upload_ok(struct tda1004x_state *state)
 374 {
 375         u8 data1, data2;
 376         unsigned long timeout;
 377
 378         if (state->demod_type == TDA1004X_DEMOD_TDA10046) {
 379                 timeout = jiffies + 2 * HZ;
 380                 while(!(tda1004x_read_byte(state, TDA1004X_STATUS_CD) & 0x20)) {
 381                         if (time_after(jiffies, timeout)) {
 382                                 printk(KERN_ERR "tda1004x: timeout waiting for DSP ready\n");
 383                                 break;
 384                         }
 385                         msleep(1);
 386                 }
 387         } else
 388                 msleep(100);
 389
 390         // check upload was OK
 391         tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0); // we want to read from the DSP
 392         tda1004x_write_byteI(state, TDA1004X_DSP_CMD, 0x67);
 393
 394         data1 = tda1004x_read_byte(state, TDA1004X_DSP_DATA1);
 395         data2 = tda1004x_read_byte(state, TDA1004X_DSP_DATA2);
 396         if (data1 != 0x67 || data2 < 0x20 || data2 > 0x2e) {
 397                 printk(KERN_INFO "tda1004x: found firmware revision %x -- invalid\n", data2);
 398                 return -EIO;
 399         }
 400         printk(KERN_INFO "tda1004x: found firmware revision %x -- ok\n", data2);
 401         return 0;
 402 }
 403
 404 static int tda10045_fwupload(struct dvb_frontend* fe)
 405 {
 406         struct tda1004x_state* state = fe->demodulator_priv;
 407         int ret;
 408         const struct firmware *fw;
 409
 410         /* don't re-upload unless necessary */
 411         if (tda1004x_check_upload_ok(state) == 0)
 412                 return 0;
 413
 414         /* request the firmware, this will block until someone uploads it */
 415         printk(KERN_INFO "tda1004x: waiting for firmware upload (%s)...\n", TDA10045_DEFAULT_FIRMWARE);
 416         ret = state->config->request_firmware(fe, &fw, TDA10045_DEFAULT_FIRMWARE);
 417         if (ret) {
 418                 printk(KERN_ERR "tda1004x: no firmware upload (timeout or file not found?)\n");
 419                 return ret;
 420         }
 421
 422         /* reset chip */
 423         tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0);
 424         tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8);
 425         tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0);
 426         msleep(10);
 427
 428         /* set parameters */
 429         tda10045h_set_bandwidth(state, BANDWIDTH_8_MHZ);
 430
 431         ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10045H_FWPAGE, TDA10045H_CODE_IN);
 432         release_firmware(fw);
 433         if (ret)
 434                 return ret;
 435         printk(KERN_INFO "tda1004x: firmware upload complete\n");
 436
 437         /* wait for DSP to initialise */
 438         /* DSPREADY doesn't seem to work on the TDA10045H */
 439         msleep(100);
 440
 441         return tda1004x_check_upload_ok(state);
 442 }
 443
 444 static void tda10046_init_plls(struct dvb_frontend* fe)
 445 {
 446         struct tda1004x_state* state = fe->demodulator_priv;
 447         int tda10046_clk53m;
 448
 449         if ((state->config->if_freq == TDA10046_FREQ_045) ||
 450             (state->config->if_freq == TDA10046_FREQ_052))
 451                 tda10046_clk53m = 0;
 452         else
 453                 tda10046_clk53m = 1;
 454
 455         tda1004x_write_byteI(state, TDA10046H_CONFPLL1, 0xf0);
 456         if(tda10046_clk53m) {
 457                 printk(KERN_INFO "tda1004x: setting up plls for 53MHz sampling clock\n");
 458                 tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 0x08); // PLL M = 8
 459         } else {
 460                 printk(KERN_INFO "tda1004x: setting up plls for 48MHz sampling clock\n");
 461                 tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 0x03); // PLL M = 3
 462         }
 463         if (state->config->xtal_freq == TDA10046_XTAL_4M ) {
 464                 dprintk("%s: setting up PLLs for a 4 MHz Xtal\n", __FUNCTION__);
 465                 tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 0); // PLL P = N = 0
 466         } else {
 467                 dprintk("%s: setting up PLLs for a 16 MHz Xtal\n", __FUNCTION__);
 468                 tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 3); // PLL P = 0, N = 3
 469         }
 470         if(tda10046_clk53m)
 471                 tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 0x67);
 472         else
 473                 tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 0x72);
 474         /* Note clock frequency is handled implicitly */
 475         switch (state->config->if_freq) {
 476         case TDA10046_FREQ_045:
 477                 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0c);
 478                 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x00);
 479                 break;
 480         case TDA10046_FREQ_052:
 481                 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0d);
 482                 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xc7);
 483                 break;
 484         case TDA10046_FREQ_3617:
 485                 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd7);
 486                 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x59);
 487                 break;
 488         case TDA10046_FREQ_3613:
 489                 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd7);
 490                 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x3f);
 491                 break;
 492         }
 493         tda10046h_set_bandwidth(state, BANDWIDTH_8_MHZ); // default bandwidth 8 MHz
 494         /* let the PLLs settle */
 495         msleep(120);
 496 }
 497
 498 static int tda10046_fwupload(struct dvb_frontend* fe)
 499 {
 500         struct tda1004x_state* state = fe->demodulator_priv;
 501         int ret;
 502         const struct firmware *fw;
 503
 504         /* reset + wake up chip */
 505         if (state->config->xtal_freq == TDA10046_XTAL_4M) {
 506                 tda1004x_write_byteI(state, TDA1004X_CONFC4, 0);
 507         } else {
 508                 dprintk("%s: 16MHz Xtal, reducing I2C speed\n", __FUNCTION__);
 509                 tda1004x_write_byteI(state, TDA1004X_CONFC4, 0x80);
 510         }
 511         tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 1, 0);
 512         /* let the clocks recover from sleep */
 513         msleep(5);
 514
 515         /* The PLLs need to be reprogrammed after sleep */
 516         tda10046_init_plls(fe);
 517
 518         /* don't re-upload unless necessary */
 519         if (tda1004x_check_upload_ok(state) == 0)
 520                 return 0;
 521
 522         if (state->config->request_firmware != NULL) {
 523                 /* request the firmware, this will block until someone uploads it */
 524                 printk(KERN_INFO "tda1004x: waiting for firmware upload...\n");
 525                 ret = state->config->request_firmware(fe, &fw, TDA10046_DEFAULT_FIRMWARE);
 526                 if (ret) {
 527                         printk(KERN_ERR "tda1004x: no firmware upload (timeout or file not found?)\n");
 528                         return ret;
 529                 }
 530                 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8); // going to boot from HOST
 531                 ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10046H_CODE_CPT, TDA10046H_CODE_IN);
 532                 release_firmware(fw);
 533                 if (ret)
 534                         return ret;
 535         } else {
 536                 /* boot from firmware eeprom */
 537                 printk(KERN_INFO "tda1004x: booting from eeprom\n");
 538                 tda1004x_write_mask(state, TDA1004X_CONFC4, 4, 4);
 539                 msleep(300);
 540         }
 541         return tda1004x_check_upload_ok(state);
 542 }
 543
 544 static int tda1004x_encode_fec(int fec)
 545 {
 546         // convert known FEC values
 547         switch (fec) {
 548         case FEC_1_2:
 549                 return 0;
 550         case FEC_2_3:
 551                 return 1;
 552         case FEC_3_4:
 553                 return 2;
 554         case FEC_5_6:
 555                 return 3;
 556         case FEC_7_8:
 557                 return 4;
 558         }
 559
 560         // unsupported
 561         return -EINVAL;
 562 }
 563
 564 static int tda1004x_decode_fec(int tdafec)
 565 {
 566         // convert known FEC values
 567         switch (tdafec) {
 568         case 0:
 569                 return FEC_1_2;
 570         case 1:
 571                 return FEC_2_3;
 572         case 2:
 573                 return FEC_3_4;
 574         case 3:
 575                 return FEC_5_6;
 576         case 4:
 577                 return FEC_7_8;
 578         }
 579
 580         // unsupported
 581         return -1;
 582 }
 583
 584 int tda1004x_write_byte(struct dvb_frontend* fe, int reg, int data)
 585 {
 586         struct tda1004x_state* state = fe->demodulator_priv;
 587
 588         return tda1004x_write_byteI(state, reg, data);
 589 }
 590
 591 static int tda10045_init(struct dvb_frontend* fe)
 592 {
 593         struct tda1004x_state* state = fe->demodulator_priv;
 594
 595         dprintk("%s\n", __FUNCTION__);
 596
 597         if (state->initialised)
 598                 return 0;
 599
 600         if (tda10045_fwupload(fe)) {
 601                 printk("tda1004x: firmware upload failed\n");
 602                 return -EIO;
 603         }
 604
 605         tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0); // wake up the ADC
 606
 607         // Init the PLL
 608         if (state->config->pll_init) {
 609                 tda1004x_enable_tuner_i2c(state);
 610                 state->config->pll_init(fe);
 611                 tda1004x_disable_tuner_i2c(state);
 612         }
 613
 614         // tda setup
 615         tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
 616         tda1004x_write_mask(state, TDA1004X_AUTO, 8, 0); // select HP stream
 617         tda1004x_write_mask(state, TDA1004X_CONFC1, 0x40, 0); // set polarity of VAGC signal
 618         tda1004x_write_mask(state, TDA1004X_CONFC1, 0x80, 0x80); // enable pulse killer
 619         tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10); // enable auto offset
 620         tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0x0); // no frequency offset
 621         tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 0); // setup MPEG2 TS interface
 622         tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0); // setup MPEG2 TS interface
 623         tda1004x_write_mask(state, TDA1004X_VBER_MSB, 0xe0, 0xa0); // 10^6 VBER measurement bits
 624         tda1004x_write_mask(state, TDA1004X_CONFC1, 0x10, 0); // VAGC polarity
 625         tda1004x_write_byteI(state, TDA1004X_CONFADC1, 0x2e);
 626
 627         tda1004x_write_mask(state, 0x1f, 0x01, state->config->invert_oclk);
 628
 629         state->initialised = 1;
 630         return 0;
 631 }
 632
 633 static int tda10046_init(struct dvb_frontend* fe)
 634 {
 635         struct tda1004x_state* state = fe->demodulator_priv;
 636         dprintk("%s\n", __FUNCTION__);
 637
 638         if (state->initialised)
 639                 return 0;
 640
 641         if (tda10046_fwupload(fe)) {
 642                 printk("tda1004x: firmware upload failed\n");
 643                         return -EIO;
 644         }
 645
 646         // Init the tuner PLL
 647         if (state->config->pll_init) {
 648                 tda1004x_enable_tuner_i2c(state);
 649                 if (state->config->pll_init(fe)) {
 650                         printk(KERN_ERR "tda1004x: pll init failed\n");
 651                         return  -EIO;
 652                 }
 653                 tda1004x_disable_tuner_i2c(state);
 654         }
 655
 656         // tda setup
 657         tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
 658         tda1004x_write_byteI(state, TDA1004X_AUTO, 0x87);    // 100 ppm crystal, select HP stream
 659         tda1004x_write_byteI(state, TDA1004X_CONFC1, 0x88);      // enable pulse killer
 660
 661         switch (state->config->agc_config) {
 662         case TDA10046_AGC_DEFAULT:
 663                 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x00); // AGC setup
 664                 tda1004x_write_byteI(state, TDA10046H_CONF_POLARITY, 0x60); // set AGC polarities
 665                 break;
 666         case TDA10046_AGC_IFO_AUTO_NEG:
 667                 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x0a); // AGC setup
 668                 tda1004x_write_byteI(state, TDA10046H_CONF_POLARITY, 0x60); // set AGC polarities
 669                 break;
 670         case TDA10046_AGC_IFO_AUTO_POS:
 671                 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x0a); // AGC setup
 672                 tda1004x_write_byteI(state, TDA10046H_CONF_POLARITY, 0x00); // set AGC polarities
 673                 break;
 674         case TDA10046_AGC_TDA827X:
 675                 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x02);   // AGC setup
 676                 tda1004x_write_byteI(state, TDA10046H_AGC_THR, 0x70);    // AGC Threshold
 677                 tda1004x_write_byteI(state, TDA10046H_AGC_RENORM, 0x08); // Gain Renormalize
 678                 tda1004x_write_byteI(state, TDA10046H_CONF_POLARITY, 0x6a); // set AGC polarities
 679                 break;
 680         case TDA10046_AGC_TDA827X_GPL:
 681                 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x02);   // AGC setup
 682                 tda1004x_write_byteI(state, TDA10046H_AGC_THR, 0x70);    // AGC Threshold
 683                 tda1004x_write_byteI(state, TDA10046H_AGC_RENORM, 0x08); // Gain Renormalize
 684                 tda1004x_write_byteI(state, TDA10046H_CONF_POLARITY, 0x60); // set AGC polarities
 685                 break;
 686         }
 687         tda1004x_write_byteI(state, TDA1004X_CONFADC2, 0x38);
 688         tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE1, 0x61); // Turn both AGC outputs on
 689         tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MIN, 0);    // }
 690         tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MAX, 0xff); // } AGC min/max values
 691         tda1004x_write_byteI(state, TDA10046H_AGC_IF_MIN, 0);     // }
 692         tda1004x_write_byteI(state, TDA10046H_AGC_IF_MAX, 0xff);  // }
 693         tda1004x_write_byteI(state, TDA10046H_AGC_GAINS, 0x12); // IF gain 2, TUN gain 1
 694         tda1004x_write_byteI(state, TDA10046H_CVBER_CTRL, 0x1a); // 10^6 VBER measurement bits
 695         tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 7); // MPEG2 interface config
 696         tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0xc0); // MPEG2 interface config
 697         // tda1004x_write_mask(state, 0x50, 0x80, 0x80);         // handle out of guard echoes
 698         tda1004x_write_mask(state, 0x3a, 0x80, state->config->invert_oclk << 7);
 699
 700         state->initialised = 1;
 701         return 0;
 702 }
 703
 704 static int tda1004x_set_fe(struct dvb_frontend* fe,
 705                            struct dvb_frontend_parameters *fe_params)
 706 {
 707         struct tda1004x_state* state = fe->demodulator_priv;
 708         int tmp;
 709         int inversion;
 710
 711         dprintk("%s\n", __FUNCTION__);
 712
 713         if (state->demod_type == TDA1004X_DEMOD_TDA10046) {
 714                 // setup auto offset
 715                 tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10);
 716                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x80, 0);
 717                 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0);
 718
 719                 // disable agc_conf[2]
 720                 tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 0);
 721         }
 722
 723         // set frequency
 724         tda1004x_enable_tuner_i2c(state);
 725         if (state->config->pll_set(fe, fe_params)) {
 726                 printk(KERN_ERR "tda1004x: pll set failed\n");
 727                 return  -EIO;
 728         }
 729         tda1004x_disable_tuner_i2c(state);
 730
 731         // Hardcoded to use auto as much as possible on the TDA10045 as it
 732         // is very unreliable if AUTO mode is _not_ used.
 733         if (state->demod_type == TDA1004X_DEMOD_TDA10045) {
 734                 fe_params->u.ofdm.code_rate_HP = FEC_AUTO;
 735                 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_AUTO;
 736                 fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_AUTO;
 737         }
 738
 739         // Set standard params.. or put them to auto
 740         if ((fe_params->u.ofdm.code_rate_HP == FEC_AUTO) ||
 741                 (fe_params->u.ofdm.code_rate_LP == FEC_AUTO) ||
 742                 (fe_params->u.ofdm.constellation == QAM_AUTO) ||
 743                 (fe_params->u.ofdm.hierarchy_information == HIERARCHY_AUTO)) {
 744                 tda1004x_write_mask(state, TDA1004X_AUTO, 1, 1);        // enable auto
 745                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x03, 0); // turn off constellation bits
 746                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0); // turn off hierarchy bits
 747                 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x3f, 0); // turn off FEC bits
 748         } else {
 749                 tda1004x_write_mask(state, TDA1004X_AUTO, 1, 0);        // disable auto
 750
 751                 // set HP FEC
 752                 tmp = tda1004x_encode_fec(fe_params->u.ofdm.code_rate_HP);
 753                 if (tmp < 0)
 754                         return tmp;
 755                 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 7, tmp);
 756
 757                 // set LP FEC
 758                 tmp = tda1004x_encode_fec(fe_params->u.ofdm.code_rate_LP);
 759                 if (tmp < 0)
 760                         return tmp;
 761                 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x38, tmp << 3);
 762
 763                 // set constellation
 764                 switch (fe_params->u.ofdm.constellation) {
 765                 case QPSK:
 766                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 0);
 767                         break;
 768
 769                 case QAM_16:
 770                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 1);
 771                         break;
 772
 773                 case QAM_64:
 774                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 2);
 775                         break;
 776
 777                 default:
 778                         return -EINVAL;
 779                 }
 780
 781                 // set hierarchy
 782                 switch (fe_params->u.ofdm.hierarchy_information) {
 783                 case HIERARCHY_NONE:
 784                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0 << 5);
 785                         break;
 786
 787                 case HIERARCHY_1:
 788                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 1 << 5);
 789                         break;
 790
 791                 case HIERARCHY_2:
 792                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 2 << 5);
 793                         break;
 794
 795                 case HIERARCHY_4:
 796                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 3 << 5);
 797                         break;
 798
 799                 default:
 800                         return -EINVAL;
 801                 }
 802         }
 803
 804         // set bandwidth
 805         switch (state->demod_type) {
 806         case TDA1004X_DEMOD_TDA10045:
 807                 tda10045h_set_bandwidth(state, fe_params->u.ofdm.bandwidth);
 808                 break;
 809
 810         case TDA1004X_DEMOD_TDA10046:
 811                 tda10046h_set_bandwidth(state, fe_params->u.ofdm.bandwidth);
 812                 break;
 813         }
 814
 815         // set inversion
 816         inversion = fe_params->inversion;
 817         if (state->config->invert)
 818                 inversion = inversion ? INVERSION_OFF : INVERSION_ON;
 819         switch (inversion) {
 820         case INVERSION_OFF:
 821                 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0);
 822                 break;
 823
 824         case INVERSION_ON:
 825                 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0x20);
 826                 break;
 827
 828         default:
 829                 return -EINVAL;
 830         }
 831
 832         // set guard interval
 833         switch (fe_params->u.ofdm.guard_interval) {
 834         case GUARD_INTERVAL_1_32:
 835                 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
 836                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2);
 837                 break;
 838
 839         case GUARD_INTERVAL_1_16:
 840                 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
 841                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 1 << 2);
 842                 break;
 843
 844         case GUARD_INTERVAL_1_8:
 845                 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
 846                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 2 << 2);
 847                 break;
 848
 849         case GUARD_INTERVAL_1_4:
 850                 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
 851                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 3 << 2);
 852                 break;
 853
 854         case GUARD_INTERVAL_AUTO:
 855                 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 2);
 856                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2);
 857                 break;
 858
 859         default:
 860                 return -EINVAL;
 861         }
 862
 863         // set transmission mode
 864         switch (fe_params->u.ofdm.transmission_mode) {
 865         case TRANSMISSION_MODE_2K:
 866                 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0);
 867                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0 << 4);
 868                 break;
 869
 870         case TRANSMISSION_MODE_8K:
 871                 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0);
 872                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 1 << 4);
 873                 break;
 874
 875         case TRANSMISSION_MODE_AUTO:
 876                 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 4);
 877                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0);
 878                 break;
 879
 880         default:
 881                 return -EINVAL;
 882         }
 883
 884         // start the lock
 885         switch (state->demod_type) {
 886         case TDA1004X_DEMOD_TDA10045:
 887                 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8);
 888                 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0);
 889                 break;
 890
 891         case TDA1004X_DEMOD_TDA10046:
 892                 tda1004x_write_mask(state, TDA1004X_AUTO, 0x40, 0x40);
 893                 msleep(1);
 894                 tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 1);
 895                 break;
 896         }
 897
 898         msleep(10);
 899
 900         return 0;
 901 }
 902
 903 static int tda1004x_get_fe(struct dvb_frontend* fe, struct dvb_frontend_parameters *fe_params)
 904 {
 905         struct tda1004x_state* state = fe->demodulator_priv;
 906
 907         dprintk("%s\n", __FUNCTION__);
 908
 909         // inversion status
 910         fe_params->inversion = INVERSION_OFF;
 911         if (tda1004x_read_byte(state, TDA1004X_CONFC1) & 0x20)
 912                 fe_params->inversion = INVERSION_ON;
 913         if (state->config->invert)
 914                 fe_params->inversion = fe_params->inversion ? INVERSION_OFF : INVERSION_ON;
 915
 916         // bandwidth
 917         switch (state->demod_type) {
 918         case TDA1004X_DEMOD_TDA10045:
 919                 switch (tda1004x_read_byte(state, TDA10045H_WREF_LSB)) {
 920                 case 0x14:
 921                         fe_params->u.ofdm.bandwidth = BANDWIDTH_8_MHZ;
 922                         break;
 923                 case 0xdb:
 924                         fe_params->u.ofdm.bandwidth = BANDWIDTH_7_MHZ;
 925                         break;
 926                 case 0x4f:
 927                         fe_params->u.ofdm.bandwidth = BANDWIDTH_6_MHZ;
 928                         break;
 929                 }
 930                 break;
 931         case TDA1004X_DEMOD_TDA10046:
 932                 switch (tda1004x_read_byte(state, TDA10046H_TIME_WREF1)) {
 933                 case 0x5c:
 934                 case 0x54:
 935                         fe_params->u.ofdm.bandwidth = BANDWIDTH_8_MHZ;
 936                         break;
 937                 case 0x6a:
 938                 case 0x60:
 939                         fe_params->u.ofdm.bandwidth = BANDWIDTH_7_MHZ;
 940                         break;
 941                 case 0x7b:
 942                 case 0x70:
 943                         fe_params->u.ofdm.bandwidth = BANDWIDTH_6_MHZ;
 944                         break;
 945                 }
 946                 break;
 947         }
 948
 949         // FEC
 950         fe_params->u.ofdm.code_rate_HP =
 951             tda1004x_decode_fec(tda1004x_read_byte(state, TDA1004X_OUT_CONF2) & 7);
 952         fe_params->u.ofdm.code_rate_LP =
 953             tda1004x_decode_fec((tda1004x_read_byte(state, TDA1004X_OUT_CONF2) >> 3) & 7);
 954
 955         // constellation
 956         switch (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 3) {
 957         case 0:
 958                 fe_params->u.ofdm.constellation = QPSK;
 959                 break;
 960         case 1:
 961                 fe_params->u.ofdm.constellation = QAM_16;
 962                 break;
 963         case 2:
 964                 fe_params->u.ofdm.constellation = QAM_64;
 965                 break;
 966         }
 967
 968         // transmission mode
 969         fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_2K;
 970         if (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x10)
 971                 fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_8K;
 972
 973         // guard interval
 974         switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x0c) >> 2) {
 975         case 0:
 976                 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_32;
 977                 break;
 978         case 1:
 979                 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_16;
 980                 break;
 981         case 2:
 982                 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_8;
 983                 break;
 984         case 3:
 985                 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_4;
 986                 break;
 987         }
 988
 989         // hierarchy
 990         switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x60) >> 5) {
 991         case 0:
 992                 fe_params->u.ofdm.hierarchy_information = HIERARCHY_NONE;
 993                 break;
 994         case 1:
 995                 fe_params->u.ofdm.hierarchy_information = HIERARCHY_1;
 996                 break;
 997         case 2:
 998                 fe_params->u.ofdm.hierarchy_information = HIERARCHY_2;
 999                 break;
1000         case 3:
1001                 fe_params->u.ofdm.hierarchy_information = HIERARCHY_4;
1002                 break;
1003         }
1004
1005         return 0;
1006 }
1007
1008 static int tda1004x_read_status(struct dvb_frontend* fe, fe_status_t * fe_status)
1009 {
1010         struct tda1004x_state* state = fe->demodulator_priv;
1011         int status;
1012         int cber;
1013         int vber;
1014
1015         dprintk("%s\n", __FUNCTION__);
1016
1017         // read status
1018         status = tda1004x_read_byte(state, TDA1004X_STATUS_CD);
1019         if (status == -1)
1020                 return -EIO;
1021
1022         // decode
1023         *fe_status = 0;
1024         if (status & 4)
1025                 *fe_status |= FE_HAS_SIGNAL;
1026         if (status & 2)
1027                 *fe_status |= FE_HAS_CARRIER;
1028         if (status & 8)
1029                 *fe_status |= FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
1030
1031         // if we don't already have VITERBI (i.e. not LOCKED), see if the viterbi
1032         // is getting anything valid
1033         if (!(*fe_status & FE_HAS_VITERBI)) {
1034                 // read the CBER
1035                 cber = tda1004x_read_byte(state, TDA1004X_CBER_LSB);
1036                 if (cber == -1)
1037                         return -EIO;
1038                 status = tda1004x_read_byte(state, TDA1004X_CBER_MSB);
1039                 if (status == -1)
1040                         return -EIO;
1041                 cber |= (status << 8);
1042                 // The address 0x20 should be read to cope with a TDA10046 bug
1043                 tda1004x_read_byte(state, TDA1004X_CBER_RESET);
1044
1045                 if (cber != 65535)
1046                         *fe_status |= FE_HAS_VITERBI;
1047         }
1048
1049         // if we DO have some valid VITERBI output, but don't already have SYNC
1050         // bytes (i.e. not LOCKED), see if the RS decoder is getting anything valid.
1051         if ((*fe_status & FE_HAS_VITERBI) && (!(*fe_status & FE_HAS_SYNC))) {
1052                 // read the VBER
1053                 vber = tda1004x_read_byte(state, TDA1004X_VBER_LSB);
1054                 if (vber == -1)
1055                         return -EIO;
1056                 status = tda1004x_read_byte(state, TDA1004X_VBER_MID);
1057                 if (status == -1)
1058                         return -EIO;
1059                 vber |= (status << 8);
1060                 status = tda1004x_read_byte(state, TDA1004X_VBER_MSB);
1061                 if (status == -1)
1062                         return -EIO;
1063                 vber |= (status & 0x0f) << 16;
1064                 // The CVBER_LUT should be read to cope with TDA10046 hardware bug
1065                 tda1004x_read_byte(state, TDA1004X_CVBER_LUT);
1066
1067                 // if RS has passed some valid TS packets, then we must be
1068                 // getting some SYNC bytes
1069                 if (vber < 16632)
1070                         *fe_status |= FE_HAS_SYNC;
1071         }
1072
1073         // success
1074         dprintk("%s: fe_status=0x%x\n", __FUNCTION__, *fe_status);
1075         return 0;
1076 }
1077
1078 static int tda1004x_read_signal_strength(struct dvb_frontend* fe, u16 * signal)
1079 {
1080         struct tda1004x_state* state = fe->demodulator_priv;
1081         int tmp;
1082         int reg = 0;
1083
1084         dprintk("%s\n", __FUNCTION__);
1085
1086         // determine the register to use
1087         switch (state->demod_type) {
1088         case TDA1004X_DEMOD_TDA10045:
1089                 reg = TDA10045H_S_AGC;
1090                 break;
1091
1092         case TDA1004X_DEMOD_TDA10046:
1093                 reg = TDA10046H_AGC_IF_LEVEL;
1094                 break;
1095         }
1096
1097         // read it
1098         tmp = tda1004x_read_byte(state, reg);
1099         if (tmp < 0)
1100                 return -EIO;
1101
1102         *signal = (tmp << 8) | tmp;
1103         dprintk("%s: signal=0x%x\n", __FUNCTION__, *signal);
1104         return 0;
1105 }
1106
1107 static int tda1004x_read_snr(struct dvb_frontend* fe, u16 * snr)
1108 {
1109         struct tda1004x_state* state = fe->demodulator_priv;
1110         int tmp;
1111
1112         dprintk("%s\n", __FUNCTION__);
1113
1114         // read it
1115         tmp = tda1004x_read_byte(state, TDA1004X_SNR);
1116         if (tmp < 0)
1117                 return -EIO;
1118         tmp = 255 - tmp;
1119
1120         *snr = ((tmp << 8) | tmp);
1121         dprintk("%s: snr=0x%x\n", __FUNCTION__, *snr);
1122         return 0;
1123 }
1124
1125 static int tda1004x_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
1126 {
1127         struct tda1004x_state* state = fe->demodulator_priv;
1128         int tmp;
1129         int tmp2;
1130         int counter;
1131
1132         dprintk("%s\n", __FUNCTION__);
1133
1134         // read the UCBLOCKS and reset
1135         counter = 0;
1136         tmp = tda1004x_read_byte(state, TDA1004X_UNCOR);
1137         if (tmp < 0)
1138                 return -EIO;
1139         tmp &= 0x7f;
1140         while (counter++ < 5) {
1141                 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1142                 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1143                 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1144
1145                 tmp2 = tda1004x_read_byte(state, TDA1004X_UNCOR);
1146                 if (tmp2 < 0)
1147                         return -EIO;
1148                 tmp2 &= 0x7f;
1149                 if ((tmp2 < tmp) || (tmp2 == 0))
1150                         break;
1151         }
1152
1153         if (tmp != 0x7f)
1154                 *ucblocks = tmp;
1155         else
1156                 *ucblocks = 0xffffffff;
1157
1158         dprintk("%s: ucblocks=0x%x\n", __FUNCTION__, *ucblocks);
1159         return 0;
1160 }
1161
1162 static int tda1004x_read_ber(struct dvb_frontend* fe, u32* ber)
1163 {
1164         struct tda1004x_state* state = fe->demodulator_priv;
1165         int tmp;
1166
1167         dprintk("%s\n", __FUNCTION__);
1168
1169         // read it in
1170         tmp = tda1004x_read_byte(state, TDA1004X_CBER_LSB);
1171         if (tmp < 0)
1172                 return -EIO;
1173         *ber = tmp << 1;
1174         tmp = tda1004x_read_byte(state, TDA1004X_CBER_MSB);
1175         if (tmp < 0)
1176                 return -EIO;
1177         *ber |= (tmp << 9);
1178         // The address 0x20 should be read to cope with a TDA10046 bug
1179         tda1004x_read_byte(state, TDA1004X_CBER_RESET);
1180
1181         dprintk("%s: ber=0x%x\n", __FUNCTION__, *ber);
1182         return 0;
1183 }
1184
1185 static int tda1004x_sleep(struct dvb_frontend* fe)
1186 {
1187         struct tda1004x_state* state = fe->demodulator_priv;
1188
1189         switch (state->demod_type) {
1190         case TDA1004X_DEMOD_TDA10045:
1191                 tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0x10);
1192                 break;
1193
1194         case TDA1004X_DEMOD_TDA10046:
1195                 if (state->config->pll_sleep != NULL) {
1196                         tda1004x_enable_tuner_i2c(state);
1197                         state->config->pll_sleep(fe);
1198                         if (state->config->if_freq != TDA10046_FREQ_052) {
1199                                 /* special hack for Philips EUROPA Based boards:
1200                                  * keep the I2c bridge open for tuner access in analog mode
1201                                  */
1202                                 tda1004x_disable_tuner_i2c(state);
1203                         }
1204                 }
1205                 /* set outputs to tristate */
1206                 tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE1, 0xff);
1207                 tda1004x_write_mask(state, TDA1004X_CONFC4, 1, 1);
1208                 break;
1209         }
1210         state->initialised = 0;
1211
1212         return 0;
1213 }
1214
1215 static int tda1004x_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings)
1216 {
1217         fesettings->min_delay_ms = 800;
1218         /* Drift compensation makes no sense for DVB-T */
1219         fesettings->step_size = 0;
1220         fesettings->max_drift = 0;
1221         return 0;
1222 }
1223
1224 static void tda1004x_release(struct dvb_frontend* fe)
1225 {
1226         struct tda1004x_state *state = fe->demodulator_priv;
1227         kfree(state);
1228 }
1229
1230 static struct dvb_frontend_ops tda10045_ops = {
1231         .info = {
1232                 .name = "Philips TDA10045H DVB-T",
1233                 .type = FE_OFDM,
1234                 .frequency_min = 51000000,
1235                 .frequency_max = 858000000,
1236                 .frequency_stepsize = 166667,
1237                 .caps =
1238                     FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1239                     FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1240                     FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
1241                     FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO
1242         },
1243
1244         .release = tda1004x_release,
1245
1246         .init = tda10045_init,
1247         .sleep = tda1004x_sleep,
1248
1249         .set_frontend = tda1004x_set_fe,
1250         .get_frontend = tda1004x_get_fe,
1251         .get_tune_settings = tda1004x_get_tune_settings,
1252
1253         .read_status = tda1004x_read_status,
1254         .read_ber = tda1004x_read_ber,
1255         .read_signal_strength = tda1004x_read_signal_strength,
1256         .read_snr = tda1004x_read_snr,
1257         .read_ucblocks = tda1004x_read_ucblocks,
1258 };
1259
1260 struct dvb_frontend* tda10045_attach(const struct tda1004x_config* config,
1261                                      struct i2c_adapter* i2c)
1262 {
1263         struct tda1004x_state *state;
1264
1265         /* allocate memory for the internal state */
1266         state = kmalloc(sizeof(struct tda1004x_state), GFP_KERNEL);
1267         if (!state)
1268                 return NULL;
1269
1270         /* setup the state */
1271         state->config = config;
1272         state->i2c = i2c;
1273         memcpy(&state->ops, &tda10045_ops, sizeof(struct dvb_frontend_ops));
1274         state->initialised = 0;
1275         state->demod_type = TDA1004X_DEMOD_TDA10045;
1276
1277         /* check if the demod is there */
1278         if (tda1004x_read_byte(state, TDA1004X_CHIPID) != 0x25) {
1279                 kfree(state);
1280                 return NULL;
1281         }
1282
1283         /* create dvb_frontend */
1284         state->frontend.ops = &state->ops;
1285         state->frontend.demodulator_priv = state;
1286         return &state->frontend;
1287 }
1288
1289 static struct dvb_frontend_ops tda10046_ops = {
1290         .info = {
1291                 .name = "Philips TDA10046H DVB-T",
1292                 .type = FE_OFDM,
1293                 .frequency_min = 51000000,
1294                 .frequency_max = 858000000,
1295                 .frequency_stepsize = 166667,
1296                 .caps =
1297                     FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1298                     FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1299                     FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
1300                     FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO
1301         },
1302
1303         .release = tda1004x_release,
1304
1305         .init = tda10046_init,
1306         .sleep = tda1004x_sleep,
1307
1308         .set_frontend = tda1004x_set_fe,
1309         .get_frontend = tda1004x_get_fe,
1310         .get_tune_settings = tda1004x_get_tune_settings,
1311
1312         .read_status = tda1004x_read_status,
1313         .read_ber = tda1004x_read_ber,
1314         .read_signal_strength = tda1004x_read_signal_strength,
1315         .read_snr = tda1004x_read_snr,
1316         .read_ucblocks = tda1004x_read_ucblocks,
1317 };
1318
1319 struct dvb_frontend* tda10046_attach(const struct tda1004x_config* config,
1320                                      struct i2c_adapter* i2c)
1321 {
1322         struct tda1004x_state *state;
1323
1324         /* allocate memory for the internal state */
1325         state = kmalloc(sizeof(struct tda1004x_state), GFP_KERNEL);
1326         if (!state)
1327                 return NULL;
1328
1329         /* setup the state */
1330         state->config = config;
1331         state->i2c = i2c;
1332         memcpy(&state->ops, &tda10046_ops, sizeof(struct dvb_frontend_ops));
1333         state->initialised = 0;
1334         state->demod_type = TDA1004X_DEMOD_TDA10046;
1335
1336         /* check if the demod is there */
1337         if (tda1004x_read_byte(state, TDA1004X_CHIPID) != 0x46) {
1338                 kfree(state);
1339                 return NULL;
1340         }
1341
1342         /* create dvb_frontend */
1343         state->frontend.ops = &state->ops;
1344         state->frontend.demodulator_priv = state;
1345         return &state->frontend;
1346 }
1347
1348 module_param(debug, int, 0644);
1349 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
1350
1351 MODULE_DESCRIPTION("Philips TDA10045H & TDA10046H DVB-T Demodulator");
1352 MODULE_AUTHOR("Andrew de Quincey & Robert Schlabbach");
1353 MODULE_LICENSE("GPL");
1354
1355 EXPORT_SYMBOL(tda10045_attach);
1356 EXPORT_SYMBOL(tda10046_attach);
1357 EXPORT_SYMBOL(tda1004x_write_byte);