2 * $Id: cx88-mpeg.c,v 1.14 2004/10/25 11:26:36 kraxel Exp $
4 * Support for the mpeg transport stream transfers
5 * PCI function #2 of the cx2388x.
7 * (c) 2004 Jelle Foks <jelle@foks.8m.com>
8 * (c) 2004 Chris Pascoe <c.pascoe@itee.uq.edu.au>
9 * (c) 2004 Gerd Knorr <kraxel@bytesex.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 #include <linux/module.h>
27 #include <linux/init.h>
28 #include <linux/device.h>
29 #include <linux/interrupt.h>
30 #include <asm/delay.h>
34 /* ------------------------------------------------------------------ */
36 MODULE_DESCRIPTION("mpeg driver for cx2388x based TV cards");
37 MODULE_AUTHOR("Jelle Foks <jelle@foks.8m.com>");
38 MODULE_AUTHOR("Chris Pascoe <c.pascoe@itee.uq.edu.au>");
39 MODULE_AUTHOR("Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]");
40 MODULE_LICENSE("GPL");
42 static unsigned int debug = 0;
43 module_param(debug,int,0644);
44 MODULE_PARM_DESC(debug,"enable debug messages [mpeg]");
46 #define dprintk(level,fmt, arg...) if (debug >= level) \
47 printk(KERN_DEBUG "%s/2: " fmt, dev->core->name , ## arg)
49 /* ------------------------------------------------------------------ */
51 static int cx8802_start_dma(struct cx8802_dev *dev,
52 struct cx88_dmaqueue *q,
53 struct cx88_buffer *buf)
55 struct cx88_core *core = dev->core;
57 dprintk(1, "cx8802_start_mpegport_dma %d\n", buf->vb.width);
59 /* setup fifo + format */
60 cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH28],
61 dev->ts_packet_size, buf->risc.dma);
63 /* write TS length to chip */
64 cx_write(MO_TS_LNGTH, buf->vb.width);
67 /* FIXME: this needs a review.
68 * also: move to cx88-blackbird + cx88-dvb source files? */
70 if (cx88_boards[core->board].dvb) {
71 /* Setup TS portion of chip */
72 cx_write(TS_GEN_CNTRL, 0x0c);
75 if (cx88_boards[core->board].blackbird) {
76 cx_write(MO_PINMUX_IO, 0x88); /* enable MPEG parallel IO */
78 // cx_write(TS_F2_CMD_STAT_MM, 0x2900106); /* F2_CMD_STAT_MM defaults + master + memory space */
79 cx_write(TS_GEN_CNTRL, 0x46); /* punctured clock TS & posedge driven & software reset */
82 cx_write(TS_HW_SOP_CNTRL, 0x408); /* mpeg start byte */
83 //cx_write(TS_HW_SOP_CNTRL, 0x2F0BC0); /* mpeg start byte ts: 0x2F0BC0 ? */
84 cx_write(TS_VALERR_CNTRL, 0x2000);
86 cx_write(TS_GEN_CNTRL, 0x06); /* punctured clock TS & posedge driven */
92 cx_write(MO_TS_GPCNTRL, GP_COUNT_CONTROL_RESET);
96 cx_set(MO_PCI_INTMSK, 0x00fc04);
97 cx_write(MO_TS_INTMSK, 0x1f0011);
100 cx_write(MO_DEV_CNTRL2, (1<<5)); /* FIXME: s/write/set/ ??? */
101 cx_write(MO_TS_DMACNTRL, 0x11);
105 static int cx8802_stop_dma(struct cx8802_dev *dev)
107 struct cx88_core *core = dev->core;
110 cx_clear(MO_TS_DMACNTRL, 0x11);
113 cx_clear(MO_PCI_INTMSK, 0x000004);
114 cx_clear(MO_TS_INTMSK, 0x1f0011);
116 /* Reset the controller */
117 cx_write(TS_GEN_CNTRL, 0xcd);
121 static int cx8802_restart_queue(struct cx8802_dev *dev,
122 struct cx88_dmaqueue *q)
124 struct cx88_buffer *buf;
125 struct list_head *item;
127 if (list_empty(&q->active))
130 buf = list_entry(q->active.next, struct cx88_buffer, vb.queue);
131 dprintk(2,"restart_queue [%p/%d]: restart dma\n",
133 cx8802_start_dma(dev, q, buf);
134 list_for_each(item,&q->active) {
135 buf = list_entry(item, struct cx88_buffer, vb.queue);
136 buf->count = q->count++;
138 mod_timer(&q->timeout, jiffies+BUFFER_TIMEOUT);
142 /* ------------------------------------------------------------------ */
144 int cx8802_buf_prepare(struct cx8802_dev *dev, struct cx88_buffer *buf)
146 int size = dev->ts_packet_size * dev->ts_packet_count;
149 dprintk(1, "%s: %p\n", __FUNCTION__, buf);
150 if (0 != buf->vb.baddr && buf->vb.bsize < size)
153 if (STATE_NEEDS_INIT == buf->vb.state) {
154 buf->vb.width = dev->ts_packet_size;
155 buf->vb.height = dev->ts_packet_count;
157 buf->vb.field = V4L2_FIELD_TOP;
159 if (0 != (rc = videobuf_iolock(dev->pci,&buf->vb,NULL)))
161 cx88_risc_databuffer(dev->pci, &buf->risc,
163 buf->vb.width, buf->vb.height);
165 buf->vb.state = STATE_PREPARED;
169 cx88_free_buffer(dev->pci,buf);
173 void cx8802_buf_queue(struct cx8802_dev *dev, struct cx88_buffer *buf)
175 struct cx88_buffer *prev;
176 struct cx88_dmaqueue *q = &dev->mpegq;
178 /* add jump to stopper */
179 buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
180 buf->risc.jmp[1] = cpu_to_le32(q->stopper.dma);
182 if (list_empty(&q->active)) {
183 list_add_tail(&buf->vb.queue,&q->active);
184 cx8802_start_dma(dev, q, buf);
185 buf->vb.state = STATE_ACTIVE;
186 buf->count = q->count++;
187 mod_timer(&q->timeout, jiffies+BUFFER_TIMEOUT);
188 dprintk(2,"[%p/%d] %s - first active\n",
189 buf, buf->vb.i, __FUNCTION__);
192 prev = list_entry(q->active.prev, struct cx88_buffer, vb.queue);
193 list_add_tail(&buf->vb.queue,&q->active);
194 buf->vb.state = STATE_ACTIVE;
195 buf->count = q->count++;
196 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
197 dprintk(2,"[%p/%d] %s - append to active\n",
198 buf, buf->vb.i, __FUNCTION__);
202 /* ----------------------------------------------------------- */
204 static void do_cancel_buffers(struct cx8802_dev *dev, char *reason, int restart)
206 struct cx88_dmaqueue *q = &dev->mpegq;
207 struct cx88_buffer *buf;
210 spin_lock_irqsave(&dev->slock,flags);
211 while (!list_empty(&q->active)) {
212 buf = list_entry(q->active.next, struct cx88_buffer, vb.queue);
213 list_del(&buf->vb.queue);
214 buf->vb.state = STATE_ERROR;
215 wake_up(&buf->vb.done);
216 dprintk(1,"[%p/%d] %s - dma=0x%08lx\n",
217 buf, buf->vb.i, reason, (unsigned long)buf->risc.dma);
220 cx8802_restart_queue(dev,q);
221 spin_unlock_irqrestore(&dev->slock,flags);
224 void cx8802_cancel_buffers(struct cx8802_dev *dev)
226 struct cx88_dmaqueue *q = &dev->mpegq;
228 del_timer_sync(&q->timeout);
229 cx8802_stop_dma(dev);
230 do_cancel_buffers(dev,"cancel",0);
233 static void cx8802_timeout(unsigned long data)
235 struct cx8802_dev *dev = (struct cx8802_dev*)data;
237 dprintk(1, "%s\n",__FUNCTION__);
240 cx88_sram_channel_dump(dev->core, &cx88_sram_channels[SRAM_CH28]);
241 cx8802_stop_dma(dev);
242 do_cancel_buffers(dev,"timeout",1);
245 static void cx8802_mpeg_irq(struct cx8802_dev *dev)
247 struct cx88_core *core = dev->core;
248 u32 status, mask, count;
250 status = cx_read(MO_TS_INTSTAT);
251 mask = cx_read(MO_TS_INTMSK);
252 if (0 == (status & mask))
255 cx_write(MO_TS_INTSTAT, status);
256 if (debug || (status & mask & ~0xff))
257 cx88_print_irqbits(core->name, "irq mpeg ",
258 cx88_mpeg_irqs, status, mask);
260 /* risc op code error */
261 if (status & (1 << 16)) {
262 printk(KERN_WARNING "%s: mpeg risc op code error\n",core->name);
263 cx_clear(MO_TS_DMACNTRL, 0x11);
264 cx88_sram_channel_dump(dev->core, &cx88_sram_channels[SRAM_CH28]);
269 spin_lock(&dev->slock);
270 count = cx_read(MO_TS_GPCNT);
271 cx88_wakeup(dev->core, &dev->mpegq, count);
272 spin_unlock(&dev->slock);
277 spin_lock(&dev->slock);
278 cx8802_restart_queue(dev,&dev->mpegq);
279 spin_unlock(&dev->slock);
282 /* other general errors */
283 if (status & 0x1f0100) {
284 spin_lock(&dev->slock);
285 cx8802_stop_dma(dev);
286 cx8802_restart_queue(dev,&dev->mpegq);
287 spin_unlock(&dev->slock);
291 static irqreturn_t cx8802_irq(int irq, void *dev_id, struct pt_regs *regs)
293 struct cx8802_dev *dev = dev_id;
294 struct cx88_core *core = dev->core;
296 int loop, handled = 0;
298 for (loop = 0; loop < 10; loop++) {
299 status = cx_read(MO_PCI_INTSTAT) & (~0x1f | 0x04);
300 mask = cx_read(MO_PCI_INTMSK);
301 if (0 == (status & mask))
304 cx_write(MO_PCI_INTSTAT, status);
306 if (status & mask & ~0x1f)
307 cx88_irq(core,status,mask);
309 cx8802_mpeg_irq(dev);
312 printk(KERN_WARNING "%s/0: irq loop -- clearing mask\n",
314 cx_write(MO_PCI_INTMSK,0);
318 return IRQ_RETVAL(handled);
321 /* ----------------------------------------------------------- */
324 int cx8802_init_common(struct cx8802_dev *dev)
329 if (pci_enable_device(dev->pci))
331 pci_set_master(dev->pci);
332 if (!pci_dma_supported(dev->pci,0xffffffff)) {
333 printk("%s/2: Oops: no 32bit PCI DMA ???\n",dev->core->name);
337 pci_read_config_byte(dev->pci, PCI_CLASS_REVISION, &dev->pci_rev);
338 pci_read_config_byte(dev->pci, PCI_LATENCY_TIMER, &dev->pci_lat);
339 printk(KERN_INFO "%s/2: found at %s, rev: %d, irq: %d, "
340 "latency: %d, mmio: 0x%lx\n", dev->core->name,
341 pci_name(dev->pci), dev->pci_rev, dev->pci->irq,
342 dev->pci_lat,pci_resource_start(dev->pci,0));
344 /* initialize driver struct */
345 init_MUTEX(&dev->lock);
346 dev->slock = SPIN_LOCK_UNLOCKED;
349 INIT_LIST_HEAD(&dev->mpegq.active);
350 INIT_LIST_HEAD(&dev->mpegq.queued);
351 dev->mpegq.timeout.function = cx8802_timeout;
352 dev->mpegq.timeout.data = (unsigned long)dev;
353 init_timer(&dev->mpegq.timeout);
354 cx88_risc_stopper(dev->pci,&dev->mpegq.stopper,
355 MO_TS_DMACNTRL,0x11,0x00);
358 /* initialize hardware */
363 err = request_irq(dev->pci->irq, cx8802_irq,
364 SA_SHIRQ | SA_INTERRUPT, dev->core->name, dev);
366 printk(KERN_ERR "%s: can't get IRQ %d\n",
367 dev->core->name, dev->pci->irq);
372 /* register i2c bus + load i2c helpers */
373 cx88_card_setup(dev);
376 /* everything worked */
377 pci_set_drvdata(dev->pci,dev);
381 void cx8802_fini_common(struct cx8802_dev *dev)
383 cx8802_stop_dma(dev);
384 pci_disable_device(dev->pci);
386 /* unregister stuff */
387 free_irq(dev->pci->irq, dev);
388 pci_set_drvdata(dev->pci, NULL);
391 btcx_riscmem_free(dev->pci,&dev->mpegq.stopper);
394 /* ----------------------------------------------------------- */
396 int cx8802_suspend_common(struct pci_dev *pci_dev, u32 state)
398 struct cx8802_dev *dev = pci_get_drvdata(pci_dev);
399 struct cx88_core *core = dev->core;
402 spin_lock(&dev->slock);
403 if (!list_empty(&dev->mpegq.active)) {
404 printk("%s: suspend mpeg\n", core->name);
405 cx8802_stop_dma(dev);
406 del_timer(&dev->mpegq.timeout);
408 spin_unlock(&dev->slock);
411 /* FIXME -- shutdown device */
412 cx88_shutdown(dev->core);
415 pci_save_state(pci_dev);
416 if (0 != pci_set_power_state(pci_dev, state)) {
417 pci_disable_device(pci_dev);
418 dev->state.disabled = 1;
423 int cx8802_resume_common(struct pci_dev *pci_dev)
425 struct cx8802_dev *dev = pci_get_drvdata(pci_dev);
426 struct cx88_core *core = dev->core;
428 if (dev->state.disabled) {
429 pci_enable_device(pci_dev);
430 dev->state.disabled = 0;
432 pci_set_power_state(pci_dev, 0);
433 pci_restore_state(pci_dev);
436 /* FIXME: re-initialize hardware */
437 cx88_reset(dev->core);
440 /* restart video+vbi capture */
441 spin_lock(&dev->slock);
442 if (!list_empty(&dev->mpegq.active)) {
443 printk("%s: resume mpeg\n", core->name);
444 cx8802_restart_queue(dev,&dev->mpegq);
446 spin_unlock(&dev->slock);
451 /* ----------------------------------------------------------- */
453 EXPORT_SYMBOL(cx8802_buf_prepare);
454 EXPORT_SYMBOL(cx8802_buf_queue);
455 EXPORT_SYMBOL(cx8802_cancel_buffers);
457 EXPORT_SYMBOL(cx8802_init_common);
458 EXPORT_SYMBOL(cx8802_fini_common);
460 EXPORT_SYMBOL(cx8802_suspend_common);
461 EXPORT_SYMBOL(cx8802_resume_common);
463 /* ----------------------------------------------------------- */